diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include')
54 files changed, 175384 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index a0a7211438f2..8889aaceec60 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -142,6 +142,7 @@ enum PP_FEATURE_MASK { enum DC_FEATURE_MASK { DC_FBC_MASK = 0x1, + DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2, }; enum amd_dpm_forced_level; diff --git a/drivers/gpu/drm/amd/include/arct_ip_offset.h b/drivers/gpu/drm/amd/include/arct_ip_offset.h new file mode 100644 index 000000000000..a7791a9e1f90 --- /dev/null +++ b/drivers/gpu/drm/amd/include/arct_ip_offset.h @@ -0,0 +1,1650 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _arct_ip_offset_HEADER +#define _arct_ip_offset_HEADER + +#define MAX_INSTANCE 8 +#define MAX_SEGMENT 6 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + + +static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } }, + { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } }, + { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } }, + { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } }, + { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } }, + { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } }, + { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE0_BASE ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA2_BASE ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA3_BASE ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA4_BASE ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA5_BASE ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA6_BASE ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA7_BASE ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } }, + { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } }, + { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } }, + { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } }, + { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } }, + { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } }, + { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } }, + { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } }; +static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } }, + { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DBGU_IO_BASE ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0 } } } }; + + + +#define ATHUB_BASE__INST0_SEG0 0x00000C20 +#define ATHUB_BASE__INST0_SEG1 0x00012460 +#define ATHUB_BASE__INST0_SEG2 0x00408C00 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 +#define ATHUB_BASE__INST0_SEG5 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 +#define ATHUB_BASE__INST1_SEG5 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 +#define ATHUB_BASE__INST2_SEG5 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 +#define ATHUB_BASE__INST3_SEG5 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 +#define ATHUB_BASE__INST4_SEG5 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 +#define ATHUB_BASE__INST5_SEG5 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 +#define ATHUB_BASE__INST6_SEG5 0 + +#define ATHUB_BASE__INST7_SEG0 0 +#define ATHUB_BASE__INST7_SEG1 0 +#define ATHUB_BASE__INST7_SEG2 0 +#define ATHUB_BASE__INST7_SEG3 0 +#define ATHUB_BASE__INST7_SEG4 0 +#define ATHUB_BASE__INST7_SEG5 0 + +#define CLK_BASE__INST0_SEG0 0x000120C0 +#define CLK_BASE__INST0_SEG1 0x00016C00 +#define CLK_BASE__INST0_SEG2 0x00401800 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 +#define CLK_BASE__INST0_SEG5 0 + +#define CLK_BASE__INST1_SEG0 0x000120E0 +#define CLK_BASE__INST1_SEG1 0x00016E00 +#define CLK_BASE__INST1_SEG2 0x00401C00 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 +#define CLK_BASE__INST1_SEG5 0 + +#define CLK_BASE__INST2_SEG0 0x00012100 +#define CLK_BASE__INST2_SEG1 0x00017000 +#define CLK_BASE__INST2_SEG2 0x00402000 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 +#define CLK_BASE__INST2_SEG5 0 + +#define CLK_BASE__INST3_SEG0 0x00012120 +#define CLK_BASE__INST3_SEG1 0x00017200 +#define CLK_BASE__INST3_SEG2 0x00402400 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 +#define CLK_BASE__INST3_SEG5 0 + +#define CLK_BASE__INST4_SEG0 0x000136C0 +#define CLK_BASE__INST4_SEG1 0x0001B000 +#define CLK_BASE__INST4_SEG2 0x0042D800 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 +#define CLK_BASE__INST4_SEG5 0 + +#define CLK_BASE__INST5_SEG0 0x00013720 +#define CLK_BASE__INST5_SEG1 0x0001B200 +#define CLK_BASE__INST5_SEG2 0x0042E400 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 +#define CLK_BASE__INST5_SEG5 0 + +#define CLK_BASE__INST6_SEG0 0x000125E0 +#define CLK_BASE__INST6_SEG1 0x00017E00 +#define CLK_BASE__INST6_SEG2 0x0040BC00 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 +#define CLK_BASE__INST6_SEG5 0 + +#define CLK_BASE__INST7_SEG0 0 +#define CLK_BASE__INST7_SEG1 0 +#define CLK_BASE__INST7_SEG2 0 +#define CLK_BASE__INST7_SEG3 0 +#define CLK_BASE__INST7_SEG4 0 +#define CLK_BASE__INST7_SEG5 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x000125C0 +#define DF_BASE__INST0_SEG2 0x0040B800 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 +#define DF_BASE__INST0_SEG5 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 +#define DF_BASE__INST1_SEG5 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 +#define DF_BASE__INST2_SEG5 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 +#define DF_BASE__INST3_SEG5 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 +#define DF_BASE__INST4_SEG5 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 +#define DF_BASE__INST5_SEG5 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 +#define DF_BASE__INST6_SEG5 0 + +#define DF_BASE__INST7_SEG0 0 +#define DF_BASE__INST7_SEG1 0 +#define DF_BASE__INST7_SEG2 0 +#define DF_BASE__INST7_SEG3 0 +#define DF_BASE__INST7_SEG4 0 +#define DF_BASE__INST7_SEG5 0 + +#define FUSE_BASE__INST0_SEG0 0x000120A0 +#define FUSE_BASE__INST0_SEG1 0x00017400 +#define FUSE_BASE__INST0_SEG2 0x00401400 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 +#define FUSE_BASE__INST0_SEG5 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 +#define FUSE_BASE__INST1_SEG5 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 +#define FUSE_BASE__INST2_SEG5 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 +#define FUSE_BASE__INST3_SEG5 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 +#define FUSE_BASE__INST4_SEG5 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 +#define FUSE_BASE__INST5_SEG5 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 +#define FUSE_BASE__INST6_SEG5 0 + +#define FUSE_BASE__INST7_SEG0 0 +#define FUSE_BASE__INST7_SEG1 0 +#define FUSE_BASE__INST7_SEG2 0 +#define FUSE_BASE__INST7_SEG3 0 +#define FUSE_BASE__INST7_SEG4 0 +#define FUSE_BASE__INST7_SEG5 0 + +#define GC_BASE__INST0_SEG0 0x00002000 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x00012160 +#define GC_BASE__INST0_SEG3 0x00402C00 +#define GC_BASE__INST0_SEG4 0 +#define GC_BASE__INST0_SEG5 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 +#define GC_BASE__INST1_SEG5 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 +#define GC_BASE__INST2_SEG5 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 +#define GC_BASE__INST3_SEG5 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 +#define GC_BASE__INST4_SEG5 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 +#define GC_BASE__INST5_SEG5 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 +#define GC_BASE__INST6_SEG5 0 + +#define GC_BASE__INST7_SEG0 0 +#define GC_BASE__INST7_SEG1 0 +#define GC_BASE__INST7_SEG2 0 +#define GC_BASE__INST7_SEG3 0 +#define GC_BASE__INST7_SEG4 0 +#define GC_BASE__INST7_SEG5 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x00012520 +#define HDP_BASE__INST0_SEG2 0x0040A400 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 +#define HDP_BASE__INST0_SEG5 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 +#define HDP_BASE__INST1_SEG5 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 +#define HDP_BASE__INST2_SEG5 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 +#define HDP_BASE__INST3_SEG5 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 +#define HDP_BASE__INST4_SEG5 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 +#define HDP_BASE__INST5_SEG5 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 +#define HDP_BASE__INST6_SEG5 0 + +#define HDP_BASE__INST7_SEG0 0 +#define HDP_BASE__INST7_SEG1 0 +#define HDP_BASE__INST7_SEG2 0 +#define HDP_BASE__INST7_SEG3 0 +#define HDP_BASE__INST7_SEG4 0 +#define HDP_BASE__INST7_SEG5 0 + +#define MMHUB_BASE__INST0_SEG0 0x00012440 +#define MMHUB_BASE__INST0_SEG1 0x0001A000 +#define MMHUB_BASE__INST0_SEG2 0x00408800 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 +#define MMHUB_BASE__INST0_SEG5 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 +#define MMHUB_BASE__INST1_SEG5 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 +#define MMHUB_BASE__INST2_SEG5 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 +#define MMHUB_BASE__INST3_SEG5 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 +#define MMHUB_BASE__INST4_SEG5 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 +#define MMHUB_BASE__INST5_SEG5 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 +#define MMHUB_BASE__INST6_SEG5 0 + +#define MMHUB_BASE__INST7_SEG0 0 +#define MMHUB_BASE__INST7_SEG1 0 +#define MMHUB_BASE__INST7_SEG2 0 +#define MMHUB_BASE__INST7_SEG3 0 +#define MMHUB_BASE__INST7_SEG4 0 +#define MMHUB_BASE__INST7_SEG5 0 + +#define MP0_BASE__INST0_SEG0 0x00013FE0 +#define MP0_BASE__INST0_SEG1 0x00016000 +#define MP0_BASE__INST0_SEG2 0x0043FC00 +#define MP0_BASE__INST0_SEG3 0x00DC0000 +#define MP0_BASE__INST0_SEG4 0x00E00000 +#define MP0_BASE__INST0_SEG5 0x00E40000 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 +#define MP0_BASE__INST1_SEG5 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 +#define MP0_BASE__INST2_SEG5 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 +#define MP0_BASE__INST3_SEG5 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 +#define MP0_BASE__INST4_SEG5 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 +#define MP0_BASE__INST5_SEG5 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 +#define MP0_BASE__INST6_SEG5 0 + +#define MP0_BASE__INST7_SEG0 0 +#define MP0_BASE__INST7_SEG1 0 +#define MP0_BASE__INST7_SEG2 0 +#define MP0_BASE__INST7_SEG3 0 +#define MP0_BASE__INST7_SEG4 0 +#define MP0_BASE__INST7_SEG5 0 + +#define MP1_BASE__INST0_SEG0 0x00012020 +#define MP1_BASE__INST0_SEG1 0x00016200 +#define MP1_BASE__INST0_SEG2 0x00400400 +#define MP1_BASE__INST0_SEG3 0x00E80000 +#define MP1_BASE__INST0_SEG4 0x00EC0000 +#define MP1_BASE__INST0_SEG5 0x00F00000 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 +#define MP1_BASE__INST1_SEG5 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 +#define MP1_BASE__INST2_SEG5 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 +#define MP1_BASE__INST3_SEG5 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 +#define MP1_BASE__INST4_SEG5 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 +#define MP1_BASE__INST5_SEG5 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 +#define MP1_BASE__INST6_SEG5 0 + +#define MP1_BASE__INST7_SEG0 0 +#define MP1_BASE__INST7_SEG1 0 +#define MP1_BASE__INST7_SEG2 0 +#define MP1_BASE__INST7_SEG3 0 +#define MP1_BASE__INST7_SEG4 0 +#define MP1_BASE__INST7_SEG5 0 + +#define NBIF0_BASE__INST0_SEG0 0x00000000 +#define NBIF0_BASE__INST0_SEG1 0x00000014 +#define NBIF0_BASE__INST0_SEG2 0x00000D20 +#define NBIF0_BASE__INST0_SEG3 0x00010400 +#define NBIF0_BASE__INST0_SEG4 0x00012D80 +#define NBIF0_BASE__INST0_SEG5 0x0041B000 + +#define NBIF0_BASE__INST1_SEG0 0 +#define NBIF0_BASE__INST1_SEG1 0 +#define NBIF0_BASE__INST1_SEG2 0 +#define NBIF0_BASE__INST1_SEG3 0 +#define NBIF0_BASE__INST1_SEG4 0 +#define NBIF0_BASE__INST1_SEG5 0 + +#define NBIF0_BASE__INST2_SEG0 0 +#define NBIF0_BASE__INST2_SEG1 0 +#define NBIF0_BASE__INST2_SEG2 0 +#define NBIF0_BASE__INST2_SEG3 0 +#define NBIF0_BASE__INST2_SEG4 0 +#define NBIF0_BASE__INST2_SEG5 0 + +#define NBIF0_BASE__INST3_SEG0 0 +#define NBIF0_BASE__INST3_SEG1 0 +#define NBIF0_BASE__INST3_SEG2 0 +#define NBIF0_BASE__INST3_SEG3 0 +#define NBIF0_BASE__INST3_SEG4 0 +#define NBIF0_BASE__INST3_SEG5 0 + +#define NBIF0_BASE__INST4_SEG0 0 +#define NBIF0_BASE__INST4_SEG1 0 +#define NBIF0_BASE__INST4_SEG2 0 +#define NBIF0_BASE__INST4_SEG3 0 +#define NBIF0_BASE__INST4_SEG4 0 +#define NBIF0_BASE__INST4_SEG5 0 + +#define NBIF0_BASE__INST5_SEG0 0 +#define NBIF0_BASE__INST5_SEG1 0 +#define NBIF0_BASE__INST5_SEG2 0 +#define NBIF0_BASE__INST5_SEG3 0 +#define NBIF0_BASE__INST5_SEG4 0 +#define NBIF0_BASE__INST5_SEG5 0 + +#define NBIF0_BASE__INST6_SEG0 0 +#define NBIF0_BASE__INST6_SEG1 0 +#define NBIF0_BASE__INST6_SEG2 0 +#define NBIF0_BASE__INST6_SEG3 0 +#define NBIF0_BASE__INST6_SEG4 0 +#define NBIF0_BASE__INST6_SEG5 0 + +#define NBIF0_BASE__INST7_SEG0 0 +#define NBIF0_BASE__INST7_SEG1 0 +#define NBIF0_BASE__INST7_SEG2 0 +#define NBIF0_BASE__INST7_SEG3 0 +#define NBIF0_BASE__INST7_SEG4 0 +#define NBIF0_BASE__INST7_SEG5 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x00012500 +#define OSSSYS_BASE__INST0_SEG2 0x0040A000 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 +#define OSSSYS_BASE__INST0_SEG5 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 +#define OSSSYS_BASE__INST1_SEG5 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 +#define OSSSYS_BASE__INST2_SEG5 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 +#define OSSSYS_BASE__INST3_SEG5 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 +#define OSSSYS_BASE__INST4_SEG5 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 +#define OSSSYS_BASE__INST5_SEG5 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 +#define OSSSYS_BASE__INST6_SEG5 0 + +#define OSSSYS_BASE__INST7_SEG0 0 +#define OSSSYS_BASE__INST7_SEG1 0 +#define OSSSYS_BASE__INST7_SEG2 0 +#define OSSSYS_BASE__INST7_SEG3 0 +#define OSSSYS_BASE__INST7_SEG4 0 +#define OSSSYS_BASE__INST7_SEG5 0 + +#define PCIE0_BASE__INST0_SEG0 0x000128C0 +#define PCIE0_BASE__INST0_SEG1 0x00411800 +#define PCIE0_BASE__INST0_SEG2 0x04440000 +#define PCIE0_BASE__INST0_SEG3 0 +#define PCIE0_BASE__INST0_SEG4 0 +#define PCIE0_BASE__INST0_SEG5 0 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 +#define PCIE0_BASE__INST1_SEG5 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 +#define PCIE0_BASE__INST2_SEG5 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 +#define PCIE0_BASE__INST3_SEG5 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 +#define PCIE0_BASE__INST4_SEG5 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 +#define PCIE0_BASE__INST5_SEG5 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 +#define PCIE0_BASE__INST6_SEG5 0 + +#define PCIE0_BASE__INST7_SEG0 0 +#define PCIE0_BASE__INST7_SEG1 0 +#define PCIE0_BASE__INST7_SEG2 0 +#define PCIE0_BASE__INST7_SEG3 0 +#define PCIE0_BASE__INST7_SEG4 0 +#define PCIE0_BASE__INST7_SEG5 0 + +#define SDMA0_BASE__INST0_SEG0 0x00001260 +#define SDMA0_BASE__INST0_SEG1 0x00012540 +#define SDMA0_BASE__INST0_SEG2 0x0040A800 +#define SDMA0_BASE__INST0_SEG3 0 +#define SDMA0_BASE__INST0_SEG4 0 +#define SDMA0_BASE__INST0_SEG5 0 + +#define SDMA0_BASE__INST1_SEG0 0 +#define SDMA0_BASE__INST1_SEG1 0 +#define SDMA0_BASE__INST1_SEG2 0 +#define SDMA0_BASE__INST1_SEG3 0 +#define SDMA0_BASE__INST1_SEG4 0 +#define SDMA0_BASE__INST1_SEG5 0 + +#define SDMA0_BASE__INST2_SEG0 0 +#define SDMA0_BASE__INST2_SEG1 0 +#define SDMA0_BASE__INST2_SEG2 0 +#define SDMA0_BASE__INST2_SEG3 0 +#define SDMA0_BASE__INST2_SEG4 0 +#define SDMA0_BASE__INST2_SEG5 0 + +#define SDMA0_BASE__INST3_SEG0 0 +#define SDMA0_BASE__INST3_SEG1 0 +#define SDMA0_BASE__INST3_SEG2 0 +#define SDMA0_BASE__INST3_SEG3 0 +#define SDMA0_BASE__INST3_SEG4 0 +#define SDMA0_BASE__INST3_SEG5 0 + +#define SDMA0_BASE__INST4_SEG0 0 +#define SDMA0_BASE__INST4_SEG1 0 +#define SDMA0_BASE__INST4_SEG2 0 +#define SDMA0_BASE__INST4_SEG3 0 +#define SDMA0_BASE__INST4_SEG4 0 +#define SDMA0_BASE__INST4_SEG5 0 + +#define SDMA0_BASE__INST5_SEG0 0 +#define SDMA0_BASE__INST5_SEG1 0 +#define SDMA0_BASE__INST5_SEG2 0 +#define SDMA0_BASE__INST5_SEG3 0 +#define SDMA0_BASE__INST5_SEG4 0 +#define SDMA0_BASE__INST5_SEG5 0 + +#define SDMA0_BASE__INST6_SEG0 0 +#define SDMA0_BASE__INST6_SEG1 0 +#define SDMA0_BASE__INST6_SEG2 0 +#define SDMA0_BASE__INST6_SEG3 0 +#define SDMA0_BASE__INST6_SEG4 0 +#define SDMA0_BASE__INST6_SEG5 0 + +#define SDMA1_BASE__INST0_SEG0 0x00001860 +#define SDMA1_BASE__INST0_SEG1 0x00012560 +#define SDMA1_BASE__INST0_SEG2 0x0040AC00 +#define SDMA1_BASE__INST0_SEG3 0 +#define SDMA1_BASE__INST0_SEG4 0 +#define SDMA1_BASE__INST0_SEG5 0 + +#define SDMA1_BASE__INST1_SEG0 0 +#define SDMA1_BASE__INST1_SEG1 0 +#define SDMA1_BASE__INST1_SEG2 0 +#define SDMA1_BASE__INST1_SEG3 0 +#define SDMA1_BASE__INST1_SEG4 0 +#define SDMA1_BASE__INST1_SEG5 0 + +#define SDMA1_BASE__INST2_SEG0 0 +#define SDMA1_BASE__INST2_SEG1 0 +#define SDMA1_BASE__INST2_SEG2 0 +#define SDMA1_BASE__INST2_SEG3 0 +#define SDMA1_BASE__INST2_SEG4 0 +#define SDMA1_BASE__INST2_SEG5 0 + +#define SDMA1_BASE__INST3_SEG0 0 +#define SDMA1_BASE__INST3_SEG1 0 +#define SDMA1_BASE__INST3_SEG2 0 +#define SDMA1_BASE__INST3_SEG3 0 +#define SDMA1_BASE__INST3_SEG4 0 +#define SDMA1_BASE__INST3_SEG5 0 + +#define SDMA1_BASE__INST4_SEG0 0 +#define SDMA1_BASE__INST4_SEG1 0 +#define SDMA1_BASE__INST4_SEG2 0 +#define SDMA1_BASE__INST4_SEG3 0 +#define SDMA1_BASE__INST4_SEG4 0 +#define SDMA1_BASE__INST4_SEG5 0 + +#define SDMA1_BASE__INST5_SEG0 0 +#define SDMA1_BASE__INST5_SEG1 0 +#define SDMA1_BASE__INST5_SEG2 0 +#define SDMA1_BASE__INST5_SEG3 0 +#define SDMA1_BASE__INST5_SEG4 0 +#define SDMA1_BASE__INST5_SEG5 0 + + +#define SDMA1_BASE__INST6_SEG0 0 +#define SDMA1_BASE__INST6_SEG1 0 +#define SDMA1_BASE__INST6_SEG2 0 +#define SDMA1_BASE__INST6_SEG3 0 +#define SDMA1_BASE__INST6_SEG4 0 +#define SDMA1_BASE__INST6_SEG5 0 + + +#define SDMA2_BASE__INST0_SEG0 0x00013760 +#define SDMA2_BASE__INST0_SEG1 0x0001E000 +#define SDMA2_BASE__INST0_SEG2 0x0042EC00 +#define SDMA2_BASE__INST0_SEG3 0 +#define SDMA2_BASE__INST0_SEG4 0 +#define SDMA2_BASE__INST0_SEG5 0 + + +#define SDMA2_BASE__INST1_SEG0 0 +#define SDMA2_BASE__INST1_SEG1 0 +#define SDMA2_BASE__INST1_SEG2 0 +#define SDMA2_BASE__INST1_SEG3 0 +#define SDMA2_BASE__INST1_SEG4 0 +#define SDMA2_BASE__INST1_SEG5 0 + +#define SDMA2_BASE__INST2_SEG0 0 +#define SDMA2_BASE__INST2_SEG1 0 +#define SDMA2_BASE__INST2_SEG2 0 +#define SDMA2_BASE__INST2_SEG3 0 +#define SDMA2_BASE__INST2_SEG4 0 +#define SDMA2_BASE__INST2_SEG5 0 + +#define SDMA2_BASE__INST3_SEG0 0 +#define SDMA2_BASE__INST3_SEG1 0 +#define SDMA2_BASE__INST3_SEG2 0 +#define SDMA2_BASE__INST3_SEG3 0 +#define SDMA2_BASE__INST3_SEG4 0 +#define SDMA2_BASE__INST3_SEG5 0 + +#define SDMA2_BASE__INST4_SEG0 0 +#define SDMA2_BASE__INST4_SEG1 0 +#define SDMA2_BASE__INST4_SEG2 0 +#define SDMA2_BASE__INST4_SEG3 0 +#define SDMA2_BASE__INST4_SEG4 0 +#define SDMA2_BASE__INST4_SEG5 0 + +#define SDMA2_BASE__INST5_SEG0 0 +#define SDMA2_BASE__INST5_SEG1 0 +#define SDMA2_BASE__INST5_SEG2 0 +#define SDMA2_BASE__INST5_SEG3 0 +#define SDMA2_BASE__INST5_SEG4 0 +#define SDMA2_BASE__INST5_SEG5 0 + +#define SDMA2_BASE__INST6_SEG0 0 +#define SDMA2_BASE__INST6_SEG1 0 +#define SDMA2_BASE__INST6_SEG2 0 +#define SDMA2_BASE__INST6_SEG3 0 +#define SDMA2_BASE__INST6_SEG4 0 +#define SDMA2_BASE__INST6_SEG5 0 + +#define SDMA3_BASE__INST0_SEG0 0x00013780 +#define SDMA3_BASE__INST0_SEG1 0x0001E400 +#define SDMA3_BASE__INST0_SEG2 0x0042F000 +#define SDMA3_BASE__INST0_SEG3 0 +#define SDMA3_BASE__INST0_SEG4 0 +#define SDMA3_BASE__INST0_SEG5 0 + +#define SDMA3_BASE__INST1_SEG0 0 +#define SDMA3_BASE__INST1_SEG1 0 +#define SDMA3_BASE__INST1_SEG2 0 +#define SDMA3_BASE__INST1_SEG3 0 +#define SDMA3_BASE__INST1_SEG4 0 +#define SDMA3_BASE__INST1_SEG5 0 + +#define SDMA3_BASE__INST2_SEG0 0 +#define SDMA3_BASE__INST2_SEG1 0 +#define SDMA3_BASE__INST2_SEG2 0 +#define SDMA3_BASE__INST2_SEG3 0 +#define SDMA3_BASE__INST2_SEG4 0 +#define SDMA3_BASE__INST2_SEG5 0 + +#define SDMA3_BASE__INST3_SEG0 0 +#define SDMA3_BASE__INST3_SEG1 0 +#define SDMA3_BASE__INST3_SEG2 0 +#define SDMA3_BASE__INST3_SEG3 0 +#define SDMA3_BASE__INST3_SEG4 0 +#define SDMA3_BASE__INST3_SEG5 0 + +#define SDMA3_BASE__INST4_SEG0 0 +#define SDMA3_BASE__INST4_SEG1 0 +#define SDMA3_BASE__INST4_SEG2 0 +#define SDMA3_BASE__INST4_SEG3 0 +#define SDMA3_BASE__INST4_SEG4 0 +#define SDMA3_BASE__INST4_SEG5 0 + +#define SDMA3_BASE__INST5_SEG0 0 +#define SDMA3_BASE__INST5_SEG1 0 +#define SDMA3_BASE__INST5_SEG2 0 +#define SDMA3_BASE__INST5_SEG3 0 +#define SDMA3_BASE__INST5_SEG4 0 +#define SDMA3_BASE__INST5_SEG5 0 + +#define SDMA3_BASE__INST6_SEG0 0 +#define SDMA3_BASE__INST6_SEG1 0 +#define SDMA3_BASE__INST6_SEG2 0 +#define SDMA3_BASE__INST6_SEG3 0 +#define SDMA3_BASE__INST6_SEG4 0 +#define SDMA3_BASE__INST6_SEG5 0 + +#define SDMA4_BASE__INST0_SEG0 0x000137A0 +#define SDMA4_BASE__INST0_SEG1 0x0001E800 +#define SDMA4_BASE__INST0_SEG2 0x0042F400 +#define SDMA4_BASE__INST0_SEG3 0 +#define SDMA4_BASE__INST0_SEG4 0 +#define SDMA4_BASE__INST0_SEG5 0 + +#define SDMA4_BASE__INST1_SEG0 0 +#define SDMA4_BASE__INST1_SEG1 0 +#define SDMA4_BASE__INST1_SEG2 0 +#define SDMA4_BASE__INST1_SEG3 0 +#define SDMA4_BASE__INST1_SEG4 0 +#define SDMA4_BASE__INST1_SEG5 0 + +#define SDMA4_BASE__INST2_SEG0 0 +#define SDMA4_BASE__INST2_SEG1 0 +#define SDMA4_BASE__INST2_SEG2 0 +#define SDMA4_BASE__INST2_SEG3 0 +#define SDMA4_BASE__INST2_SEG4 0 +#define SDMA4_BASE__INST2_SEG5 0 + +#define SDMA4_BASE__INST3_SEG0 0 +#define SDMA4_BASE__INST3_SEG1 0 +#define SDMA4_BASE__INST3_SEG2 0 +#define SDMA4_BASE__INST3_SEG3 0 +#define SDMA4_BASE__INST3_SEG4 0 +#define SDMA4_BASE__INST3_SEG5 0 + +#define SDMA4_BASE__INST4_SEG0 0 +#define SDMA4_BASE__INST4_SEG1 0 +#define SDMA4_BASE__INST4_SEG2 0 +#define SDMA4_BASE__INST4_SEG3 0 +#define SDMA4_BASE__INST4_SEG4 0 +#define SDMA4_BASE__INST4_SEG5 0 + +#define SDMA4_BASE__INST5_SEG0 0 +#define SDMA4_BASE__INST5_SEG1 0 +#define SDMA4_BASE__INST5_SEG2 0 +#define SDMA4_BASE__INST5_SEG3 0 +#define SDMA4_BASE__INST5_SEG4 0 +#define SDMA4_BASE__INST5_SEG5 0 + +#define SDMA4_BASE__INST6_SEG0 0 +#define SDMA4_BASE__INST6_SEG1 0 +#define SDMA4_BASE__INST6_SEG2 0 +#define SDMA4_BASE__INST6_SEG3 0 +#define SDMA4_BASE__INST6_SEG4 0 +#define SDMA4_BASE__INST6_SEG5 0 + +#define SDMA5_BASE__INST0_SEG0 0x000137C0 +#define SDMA5_BASE__INST0_SEG1 0x0001EC00 +#define SDMA5_BASE__INST0_SEG2 0x0042F800 +#define SDMA5_BASE__INST0_SEG3 0 +#define SDMA5_BASE__INST0_SEG4 0 +#define SDMA5_BASE__INST0_SEG5 0 + +#define SDMA5_BASE__INST1_SEG0 0 +#define SDMA5_BASE__INST1_SEG1 0 +#define SDMA5_BASE__INST1_SEG2 0 +#define SDMA5_BASE__INST1_SEG3 0 +#define SDMA5_BASE__INST1_SEG4 0 +#define SDMA5_BASE__INST1_SEG5 0 + +#define SDMA5_BASE__INST2_SEG0 0 +#define SDMA5_BASE__INST2_SEG1 0 +#define SDMA5_BASE__INST2_SEG2 0 +#define SDMA5_BASE__INST2_SEG3 0 +#define SDMA5_BASE__INST2_SEG4 0 +#define SDMA5_BASE__INST2_SEG5 0 + +#define SDMA5_BASE__INST3_SEG0 0 +#define SDMA5_BASE__INST3_SEG1 0 +#define SDMA5_BASE__INST3_SEG2 0 +#define SDMA5_BASE__INST3_SEG3 0 +#define SDMA5_BASE__INST3_SEG4 0 +#define SDMA5_BASE__INST3_SEG5 0 + +#define SDMA5_BASE__INST4_SEG0 0 +#define SDMA5_BASE__INST4_SEG1 0 +#define SDMA5_BASE__INST4_SEG2 0 +#define SDMA5_BASE__INST4_SEG3 0 +#define SDMA5_BASE__INST4_SEG4 0 +#define SDMA5_BASE__INST4_SEG5 0 + +#define SDMA5_BASE__INST5_SEG0 0 +#define SDMA5_BASE__INST5_SEG1 0 +#define SDMA5_BASE__INST5_SEG2 0 +#define SDMA5_BASE__INST5_SEG3 0 +#define SDMA5_BASE__INST5_SEG4 0 +#define SDMA5_BASE__INST5_SEG5 0 + +#define SDMA5_BASE__INST6_SEG0 0 +#define SDMA5_BASE__INST6_SEG1 0 +#define SDMA5_BASE__INST6_SEG2 0 +#define SDMA5_BASE__INST6_SEG3 0 +#define SDMA5_BASE__INST6_SEG4 0 +#define SDMA5_BASE__INST6_SEG5 0 + +#define SDMA6_BASE__INST0_SEG0 0x000137E0 +#define SDMA6_BASE__INST0_SEG1 0x0001F000 +#define SDMA6_BASE__INST0_SEG2 0x0042FC00 +#define SDMA6_BASE__INST0_SEG3 0 +#define SDMA6_BASE__INST0_SEG4 0 +#define SDMA6_BASE__INST0_SEG5 0 + +#define SDMA6_BASE__INST1_SEG0 0 +#define SDMA6_BASE__INST1_SEG1 0 +#define SDMA6_BASE__INST1_SEG2 0 +#define SDMA6_BASE__INST1_SEG3 0 +#define SDMA6_BASE__INST1_SEG4 0 +#define SDMA6_BASE__INST1_SEG5 0 + +#define SDMA6_BASE__INST2_SEG0 0 +#define SDMA6_BASE__INST2_SEG1 0 +#define SDMA6_BASE__INST2_SEG2 0 +#define SDMA6_BASE__INST2_SEG3 0 +#define SDMA6_BASE__INST2_SEG4 0 +#define SDMA6_BASE__INST2_SEG5 0 + +#define SDMA6_BASE__INST3_SEG0 0 +#define SDMA6_BASE__INST3_SEG1 0 +#define SDMA6_BASE__INST3_SEG2 0 +#define SDMA6_BASE__INST3_SEG3 0 +#define SDMA6_BASE__INST3_SEG4 0 +#define SDMA6_BASE__INST3_SEG5 0 + +#define SDMA6_BASE__INST4_SEG0 0 +#define SDMA6_BASE__INST4_SEG1 0 +#define SDMA6_BASE__INST4_SEG2 0 +#define SDMA6_BASE__INST4_SEG3 0 +#define SDMA6_BASE__INST4_SEG4 0 +#define SDMA6_BASE__INST4_SEG5 0 + +#define SDMA6_BASE__INST5_SEG0 0 +#define SDMA6_BASE__INST5_SEG1 0 +#define SDMA6_BASE__INST5_SEG2 0 +#define SDMA6_BASE__INST5_SEG3 0 +#define SDMA6_BASE__INST5_SEG4 0 +#define SDMA6_BASE__INST5_SEG5 0 + +#define SDMA6_BASE__INST6_SEG0 0 +#define SDMA6_BASE__INST6_SEG1 0 +#define SDMA6_BASE__INST6_SEG2 0 +#define SDMA6_BASE__INST6_SEG3 0 +#define SDMA6_BASE__INST6_SEG4 0 +#define SDMA6_BASE__INST6_SEG5 0 + +#define SDMA7_BASE__INST0_SEG0 0x00013800 +#define SDMA7_BASE__INST0_SEG1 0x0001F400 +#define SDMA7_BASE__INST0_SEG2 0x00430000 +#define SDMA7_BASE__INST0_SEG3 0 +#define SDMA7_BASE__INST0_SEG4 0 +#define SDMA7_BASE__INST0_SEG5 0 + +#define SDMA7_BASE__INST1_SEG0 0 +#define SDMA7_BASE__INST1_SEG1 0 +#define SDMA7_BASE__INST1_SEG2 0 +#define SDMA7_BASE__INST1_SEG3 0 +#define SDMA7_BASE__INST1_SEG4 0 +#define SDMA7_BASE__INST1_SEG5 0 + +#define SDMA7_BASE__INST2_SEG0 0 +#define SDMA7_BASE__INST2_SEG1 0 +#define SDMA7_BASE__INST2_SEG2 0 +#define SDMA7_BASE__INST2_SEG3 0 +#define SDMA7_BASE__INST2_SEG4 0 +#define SDMA7_BASE__INST2_SEG5 0 + +#define SDMA7_BASE__INST3_SEG0 0 +#define SDMA7_BASE__INST3_SEG1 0 +#define SDMA7_BASE__INST3_SEG2 0 +#define SDMA7_BASE__INST3_SEG3 0 +#define SDMA7_BASE__INST3_SEG4 0 +#define SDMA7_BASE__INST3_SEG5 0 + +#define SDMA7_BASE__INST4_SEG0 0 +#define SDMA7_BASE__INST4_SEG1 0 +#define SDMA7_BASE__INST4_SEG2 0 +#define SDMA7_BASE__INST4_SEG3 0 +#define SDMA7_BASE__INST4_SEG4 0 +#define SDMA7_BASE__INST4_SEG5 0 + +#define SDMA7_BASE__INST5_SEG0 0 +#define SDMA7_BASE__INST5_SEG1 0 +#define SDMA7_BASE__INST5_SEG2 0 +#define SDMA7_BASE__INST5_SEG3 0 +#define SDMA7_BASE__INST5_SEG4 0 +#define SDMA7_BASE__INST5_SEG5 0 + +#define SDMA7_BASE__INST6_SEG0 0 +#define SDMA7_BASE__INST6_SEG1 0 +#define SDMA7_BASE__INST6_SEG2 0 +#define SDMA7_BASE__INST6_SEG3 0 +#define SDMA7_BASE__INST6_SEG4 0 +#define SDMA7_BASE__INST6_SEG5 0 + +#define SMUIO_BASE__INST0_SEG0 0x00012080 +#define SMUIO_BASE__INST0_SEG1 0x00016800 +#define SMUIO_BASE__INST0_SEG2 0x00016A00 +#define SMUIO_BASE__INST0_SEG3 0x00401000 +#define SMUIO_BASE__INST0_SEG4 0x00440000 +#define SMUIO_BASE__INST0_SEG5 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 +#define SMUIO_BASE__INST1_SEG5 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 +#define SMUIO_BASE__INST2_SEG5 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 +#define SMUIO_BASE__INST3_SEG5 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 +#define SMUIO_BASE__INST4_SEG5 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 +#define SMUIO_BASE__INST5_SEG5 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 +#define SMUIO_BASE__INST6_SEG5 0 + +#define SMUIO_BASE__INST7_SEG0 0 +#define SMUIO_BASE__INST7_SEG1 0 +#define SMUIO_BASE__INST7_SEG2 0 +#define SMUIO_BASE__INST7_SEG3 0 +#define SMUIO_BASE__INST7_SEG4 0 +#define SMUIO_BASE__INST7_SEG5 0 + +#define THM_BASE__INST0_SEG0 0x00012060 +#define THM_BASE__INST0_SEG1 0x00016600 +#define THM_BASE__INST0_SEG2 0x00400C00 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 +#define THM_BASE__INST0_SEG5 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 +#define THM_BASE__INST1_SEG5 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 +#define THM_BASE__INST2_SEG5 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 +#define THM_BASE__INST3_SEG5 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 +#define THM_BASE__INST4_SEG5 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 +#define THM_BASE__INST5_SEG5 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 +#define THM_BASE__INST6_SEG5 0 + +#define THM_BASE__INST7_SEG0 0 +#define THM_BASE__INST7_SEG1 0 +#define THM_BASE__INST7_SEG2 0 +#define THM_BASE__INST7_SEG3 0 +#define THM_BASE__INST7_SEG4 0 +#define THM_BASE__INST7_SEG5 0 + +#define UMC_BASE__INST0_SEG0 0x000132C0 +#define UMC_BASE__INST0_SEG1 0x00014000 +#define UMC_BASE__INST0_SEG2 0x00425800 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 +#define UMC_BASE__INST0_SEG5 0 + +#define UMC_BASE__INST1_SEG0 0x000132E0 +#define UMC_BASE__INST1_SEG1 0x00054000 +#define UMC_BASE__INST1_SEG2 0x00425C00 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 +#define UMC_BASE__INST1_SEG5 0 + +#define UMC_BASE__INST2_SEG0 0x00013300 +#define UMC_BASE__INST2_SEG1 0x00094000 +#define UMC_BASE__INST2_SEG2 0x00426000 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 +#define UMC_BASE__INST2_SEG5 0 + +#define UMC_BASE__INST3_SEG0 0x00013320 +#define UMC_BASE__INST3_SEG1 0x000D4000 +#define UMC_BASE__INST3_SEG2 0x00426400 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 +#define UMC_BASE__INST3_SEG5 0 + +#define UMC_BASE__INST4_SEG0 0x00013340 +#define UMC_BASE__INST4_SEG1 0x00114000 +#define UMC_BASE__INST4_SEG2 0x00426800 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 +#define UMC_BASE__INST4_SEG5 0 + +#define UMC_BASE__INST5_SEG0 0x00013360 +#define UMC_BASE__INST5_SEG1 0x00154000 +#define UMC_BASE__INST5_SEG2 0x00426C00 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 +#define UMC_BASE__INST5_SEG5 0 + +#define UMC_BASE__INST6_SEG0 0x00013380 +#define UMC_BASE__INST6_SEG1 0x00194000 +#define UMC_BASE__INST6_SEG2 0x00427000 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 +#define UMC_BASE__INST6_SEG5 0 + +#define UMC_BASE__INST7_SEG0 0x000133A0 +#define UMC_BASE__INST7_SEG1 0x001D4000 +#define UMC_BASE__INST7_SEG2 0x00427400 +#define UMC_BASE__INST7_SEG3 0 +#define UMC_BASE__INST7_SEG4 0 +#define UMC_BASE__INST7_SEG5 0 + +#define UVD_BASE__INST0_SEG0 0x00007800 +#define UVD_BASE__INST0_SEG1 0x00007E00 +#define UVD_BASE__INST0_SEG2 0x00012180 +#define UVD_BASE__INST0_SEG3 0x00403000 +#define UVD_BASE__INST0_SEG4 0 +#define UVD_BASE__INST0_SEG5 0 + +#define UVD_BASE__INST1_SEG0 0x00007A00 +#define UVD_BASE__INST1_SEG1 0x00009000 +#define UVD_BASE__INST1_SEG2 0x000136E0 +#define UVD_BASE__INST1_SEG3 0x0042DC00 +#define UVD_BASE__INST1_SEG4 0 +#define UVD_BASE__INST1_SEG5 0 + +#define UVD_BASE__INST2_SEG0 0 +#define UVD_BASE__INST2_SEG1 0 +#define UVD_BASE__INST2_SEG2 0 +#define UVD_BASE__INST2_SEG3 0 +#define UVD_BASE__INST2_SEG4 0 +#define UVD_BASE__INST2_SEG5 0 + +#define UVD_BASE__INST3_SEG0 0 +#define UVD_BASE__INST3_SEG1 0 +#define UVD_BASE__INST3_SEG2 0 +#define UVD_BASE__INST3_SEG3 0 +#define UVD_BASE__INST3_SEG4 0 +#define UVD_BASE__INST3_SEG5 0 + +#define UVD_BASE__INST4_SEG0 0 +#define UVD_BASE__INST4_SEG1 0 +#define UVD_BASE__INST4_SEG2 0 +#define UVD_BASE__INST4_SEG3 0 +#define UVD_BASE__INST4_SEG4 0 +#define UVD_BASE__INST4_SEG5 0 + +#define UVD_BASE__INST5_SEG0 0 +#define UVD_BASE__INST5_SEG1 0 +#define UVD_BASE__INST5_SEG2 0 +#define UVD_BASE__INST5_SEG3 0 +#define UVD_BASE__INST5_SEG4 0 +#define UVD_BASE__INST5_SEG5 0 + +#define UVD_BASE__INST6_SEG0 0 +#define UVD_BASE__INST6_SEG1 0 +#define UVD_BASE__INST6_SEG2 0 +#define UVD_BASE__INST6_SEG3 0 +#define UVD_BASE__INST6_SEG4 0 +#define UVD_BASE__INST6_SEG5 0 + +#define UVD_BASE__INST7_SEG0 0 +#define UVD_BASE__INST7_SEG1 0 +#define UVD_BASE__INST7_SEG2 0 +#define UVD_BASE__INST7_SEG3 0 +#define UVD_BASE__INST7_SEG4 0 +#define UVD_BASE__INST7_SEG5 0 + +#define DBGU_IO_BASE__INST0_SEG0 0x000001E0 +#define DBGU_IO_BASE__INST0_SEG1 0x000125A0 +#define DBGU_IO_BASE__INST0_SEG2 0x0040B400 +#define DBGU_IO_BASE__INST0_SEG3 0 +#define DBGU_IO_BASE__INST0_SEG4 0 +#define DBGU_IO_BASE__INST0_SEG5 0 + +#define DBGU_IO_BASE__INST1_SEG0 0 +#define DBGU_IO_BASE__INST1_SEG1 0 +#define DBGU_IO_BASE__INST1_SEG2 0 +#define DBGU_IO_BASE__INST1_SEG3 0 +#define DBGU_IO_BASE__INST1_SEG4 0 +#define DBGU_IO_BASE__INST1_SEG5 0 + +#define DBGU_IO_BASE__INST2_SEG0 0 +#define DBGU_IO_BASE__INST2_SEG1 0 +#define DBGU_IO_BASE__INST2_SEG2 0 +#define DBGU_IO_BASE__INST2_SEG3 0 +#define DBGU_IO_BASE__INST2_SEG4 0 +#define DBGU_IO_BASE__INST2_SEG5 0 + +#define DBGU_IO_BASE__INST3_SEG0 0 +#define DBGU_IO_BASE__INST3_SEG1 0 +#define DBGU_IO_BASE__INST3_SEG2 0 +#define DBGU_IO_BASE__INST3_SEG3 0 +#define DBGU_IO_BASE__INST3_SEG4 0 +#define DBGU_IO_BASE__INST3_SEG5 0 + +#define DBGU_IO_BASE__INST4_SEG0 0 +#define DBGU_IO_BASE__INST4_SEG1 0 +#define DBGU_IO_BASE__INST4_SEG2 0 +#define DBGU_IO_BASE__INST4_SEG3 0 +#define DBGU_IO_BASE__INST4_SEG4 0 +#define DBGU_IO_BASE__INST4_SEG5 0 + +#define DBGU_IO_BASE__INST5_SEG0 0 +#define DBGU_IO_BASE__INST5_SEG1 0 +#define DBGU_IO_BASE__INST5_SEG2 0 +#define DBGU_IO_BASE__INST5_SEG3 0 +#define DBGU_IO_BASE__INST5_SEG4 0 +#define DBGU_IO_BASE__INST5_SEG5 0 + +#define DBGU_IO_BASE__INST6_SEG0 0 +#define DBGU_IO_BASE__INST6_SEG1 0 +#define DBGU_IO_BASE__INST6_SEG2 0 +#define DBGU_IO_BASE__INST6_SEG3 0 +#define DBGU_IO_BASE__INST6_SEG4 0 +#define DBGU_IO_BASE__INST6_SEG5 0 + +#define DBGU_IO_BASE__INST7_SEG0 0 +#define DBGU_IO_BASE__INST7_SEG1 0 +#define DBGU_IO_BASE__INST7_SEG2 0 +#define DBGU_IO_BASE__INST7_SEG3 0 +#define DBGU_IO_BASE__INST7_SEG4 0 +#define DBGU_IO_BASE__INST7_SEG5 0 + +#define RSMU_BASE__INST0_SEG0 0x00012000 +#define RSMU_BASE__INST0_SEG1 0 +#define RSMU_BASE__INST0_SEG2 0 +#define RSMU_BASE__INST0_SEG3 0 +#define RSMU_BASE__INST0_SEG4 0 +#define RSMU_BASE__INST0_SEG5 0 + +#define RSMU_BASE__INST1_SEG0 0 +#define RSMU_BASE__INST1_SEG1 0 +#define RSMU_BASE__INST1_SEG2 0 +#define RSMU_BASE__INST1_SEG3 0 +#define RSMU_BASE__INST1_SEG4 0 +#define RSMU_BASE__INST1_SEG5 0 + +#define RSMU_BASE__INST2_SEG0 0 +#define RSMU_BASE__INST2_SEG1 0 +#define RSMU_BASE__INST2_SEG2 0 +#define RSMU_BASE__INST2_SEG3 0 +#define RSMU_BASE__INST2_SEG4 0 +#define RSMU_BASE__INST2_SEG5 0 + +#define RSMU_BASE__INST3_SEG0 0 +#define RSMU_BASE__INST3_SEG1 0 +#define RSMU_BASE__INST3_SEG2 0 +#define RSMU_BASE__INST3_SEG3 0 +#define RSMU_BASE__INST3_SEG4 0 +#define RSMU_BASE__INST3_SEG5 0 + +#define RSMU_BASE__INST4_SEG0 0 +#define RSMU_BASE__INST4_SEG1 0 +#define RSMU_BASE__INST4_SEG2 0 +#define RSMU_BASE__INST4_SEG3 0 +#define RSMU_BASE__INST4_SEG4 0 +#define RSMU_BASE__INST4_SEG5 0 + +#define RSMU_BASE__INST5_SEG0 0 +#define RSMU_BASE__INST5_SEG1 0 +#define RSMU_BASE__INST5_SEG2 0 +#define RSMU_BASE__INST5_SEG3 0 +#define RSMU_BASE__INST5_SEG4 0 +#define RSMU_BASE__INST5_SEG5 0 + +#define RSMU_BASE__INST6_SEG0 0 +#define RSMU_BASE__INST6_SEG1 0 +#define RSMU_BASE__INST6_SEG2 0 +#define RSMU_BASE__INST6_SEG3 0 +#define RSMU_BASE__INST6_SEG4 0 +#define RSMU_BASE__INST6_SEG5 0 + +#define RSMU_BASE__INST7_SEG0 0 +#define RSMU_BASE__INST7_SEG1 0 +#define RSMU_BASE__INST7_SEG2 0 +#define RSMU_BASE__INST7_SEG3 0 +#define RSMU_BASE__INST7_SEG4 0 +#define RSMU_BASE__INST7_SEG5 0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h new file mode 100644 index 000000000000..2de450361fb5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _clk_10_0_2_OFFSET_HEADER +#define _clk_10_0_2_OFFSET_HEADER + + + +// addressBlock: clk_clk1_0_SmuClkDec +// base address: 0x5b800 +#define mmCLK1_CLK_PLL_REQ 0x000f +#define mmCLK1_CLK_PLL_REQ_BASE_IDX 1 +#define mmCLK1_CLK0_BYPASS_CNTL 0x0049 +#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX 1 +#define mmCLK1_CLK1_BYPASS_CNTL 0x0053 +#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX 1 +#define mmCLK1_CLK2_BYPASS_CNTL 0x005d +#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX 1 +#define mmCLK1_CLK2_STATUS 0x005e +#define mmCLK1_CLK2_STATUS_BASE_IDX 1 +#define mmCLK1_CLK3_DFS_CNTL 0x005f +#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX 1 +#define mmCLK1_CLK3_DS_CNTL 0x0060 +#define mmCLK1_CLK3_DS_CNTL_BASE_IDX 1 +#define mmCLK1_CLK3_ALLOW_DS 0x0061 +#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX 1 +#define mmCLK1_CLK3_BYPASS_CNTL 0x0067 +#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX 1 +#define mmCLK1_CLK0_CURRENT_CNT 0x008a +#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX 1 +#define mmCLK1_CLK1_CURRENT_CNT 0x008b +#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX 1 +#define mmCLK1_CLK2_CURRENT_CNT 0x008c +#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX 1 +#define mmCLK1_CLK3_CURRENT_CNT 0x008d +#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX 1 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h new file mode 100644 index 000000000000..c949d0e662db --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _clk_10_0_2_SH_MASK_HEADER +#define _clk_10_0_2_SH_MASK_HEADER + + +// addressBlock: clk_clk1_0_SmuClkDec +//CLK1_CLK_PLL_REQ +#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 +#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc +#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 +#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL +#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L +#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L +//CLK1_CLK0_BYPASS_CNTL +#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0 +#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10 +#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L +#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK 0x000F0000L +//CLK1_CLK1_BYPASS_CNTL +#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0 +#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10 +#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L +#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK 0x000F0000L +//CLK1_CLK2_BYPASS_CNTL +#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 +#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 +#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L +#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L +//CLK1_CLK3_DS_CNTL +#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0 +#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x00000007L +//CLK1_CLK3_ALLOW_DS +#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT 0x0 +#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK 0x00000001L +//CLK1_CLK3_BYPASS_CNTL +#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0 +#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10 +#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L +#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK 0x000F0000L +//CLK1_CLK0_CURRENT_CNT +#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 +#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL +//CLK1_CLK1_CURRENT_CNT +#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 +#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL +//CLK1_CLK2_CURRENT_CNT +#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 +#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL +//CLK1_CLK3_CURRENT_CNT +#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT 0x0 +#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h new file mode 100644 index 000000000000..be4249adb356 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h @@ -0,0 +1,13862 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_2_1_0_OFFSET_HEADER +#define _dcn_2_1_0_OFFSET_HEADER + + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +// base address: 0x48 +#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 +#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 +#define mmVGA_MEM_READ_PAGE_ADDR 0x0001 +#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] +// base address: 0x3b4 +#define mmCRTC8_IDX 0x002d +#define mmCRTC8_IDX_BASE_IDX 1 +#define mmCRTC8_DATA 0x002d +#define mmCRTC8_DATA_BASE_IDX 1 +#define mmGENFC_WT 0x002e +#define mmGENFC_WT_BASE_IDX 1 +#define mmGENS1 0x002e +#define mmGENS1_BASE_IDX 1 +#define mmATTRDW 0x0030 +#define mmATTRDW_BASE_IDX 1 +#define mmATTRX 0x0030 +#define mmATTRX_BASE_IDX 1 +#define mmATTRDR 0x0030 +#define mmATTRDR_BASE_IDX 1 +#define mmGENMO_WT 0x0030 +#define mmGENMO_WT_BASE_IDX 1 +#define mmGENS0 0x0030 +#define mmGENS0_BASE_IDX 1 +#define mmGENENB 0x0030 +#define mmGENENB_BASE_IDX 1 +#define mmSEQ8_IDX 0x0031 +#define mmSEQ8_IDX_BASE_IDX 1 +#define mmSEQ8_DATA 0x0031 +#define mmSEQ8_DATA_BASE_IDX 1 +#define mmDAC_MASK 0x0031 +#define mmDAC_MASK_BASE_IDX 1 +#define mmDAC_R_INDEX 0x0031 +#define mmDAC_R_INDEX_BASE_IDX 1 +#define mmDAC_W_INDEX 0x0032 +#define mmDAC_W_INDEX_BASE_IDX 1 +#define mmDAC_DATA 0x0032 +#define mmDAC_DATA_BASE_IDX 1 +#define mmGENFC_RD 0x0032 +#define mmGENFC_RD_BASE_IDX 1 +#define mmGENMO_RD 0x0033 +#define mmGENMO_RD_BASE_IDX 1 +#define mmGRPH8_IDX 0x0033 +#define mmGRPH8_IDX_BASE_IDX 1 +#define mmGRPH8_DATA 0x0033 +#define mmGRPH8_DATA_BASE_IDX 1 +#define mmCRTC8_IDX_1 0x0035 +#define mmCRTC8_IDX_1_BASE_IDX 1 +#define mmCRTC8_DATA_1 0x0035 +#define mmCRTC8_DATA_1_BASE_IDX 1 +#define mmGENFC_WT_1 0x0036 +#define mmGENFC_WT_1_BASE_IDX 1 +#define mmGENS1_1 0x0036 +#define mmGENS1_1_BASE_IDX 1 + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec +// base address: 0x0 +#define mmVGA_RENDER_CONTROL 0x0000 +#define mmVGA_RENDER_CONTROL_BASE_IDX 1 +#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 +#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 +#define mmVGA_MODE_CONTROL 0x0002 +#define mmVGA_MODE_CONTROL_BASE_IDX 1 +#define mmVGA_SURFACE_PITCH_SELECT 0x0003 +#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 +#define mmVGA_MEMORY_BASE_ADDRESS 0x0004 +#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 +#define mmVGA_TEST_DEBUG_INDEX 0x0005 +#define mmVGA_TEST_DEBUG_INDEX_BASE_IDX 1 +#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 +#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 +#define mmVGA_TEST_DEBUG_DATA 0x0007 +#define mmVGA_TEST_DEBUG_DATA_BASE_IDX 1 +#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 +#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 +#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 +#define mmVGA_HDP_CONTROL 0x000a +#define mmVGA_HDP_CONTROL_BASE_IDX 1 +#define mmVGA_CACHE_CONTROL 0x000b +#define mmVGA_CACHE_CONTROL_BASE_IDX 1 +#define mmD1VGA_CONTROL 0x000c +#define mmD1VGA_CONTROL_BASE_IDX 1 +#define mmVGA_SECURITY_LEVEL 0x000d +#define mmVGA_SECURITY_LEVEL_BASE_IDX 1 +#define mmD2VGA_CONTROL 0x000e +#define mmD2VGA_CONTROL_BASE_IDX 1 +#define mmVGA_HW_DEBUG 0x000f +#define mmVGA_HW_DEBUG_BASE_IDX 1 +#define mmVGA_STATUS 0x0010 +#define mmVGA_STATUS_BASE_IDX 1 +#define mmVGA_INTERRUPT_CONTROL 0x0011 +#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 +#define mmVGA_STATUS_CLEAR 0x0012 +#define mmVGA_STATUS_CLEAR_BASE_IDX 1 +#define mmVGA_INTERRUPT_STATUS 0x0013 +#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 +#define mmVGA_MAIN_CONTROL 0x0014 +#define mmVGA_MAIN_CONTROL_BASE_IDX 1 +#define mmVGA_TEST_CONTROL 0x0015 +#define mmVGA_TEST_CONTROL_BASE_IDX 1 +#define mmVGA_DEBUG_READBACK_INDEX 0x0016 +#define mmVGA_DEBUG_READBACK_INDEX_BASE_IDX 1 +#define mmVGA_DEBUG_READBACK_DATA 0x0017 +#define mmVGA_DEBUG_READBACK_DATA_BASE_IDX 1 +#define mmVGA_QOS_CTRL 0x0018 +#define mmVGA_QOS_CTRL_BASE_IDX 1 +#define mmD3VGA_CONTROL 0x0038 +#define mmD3VGA_CONTROL_BASE_IDX 1 +#define mmD4VGA_CONTROL 0x0039 +#define mmD4VGA_CONTROL_BASE_IDX 1 +#define mmD5VGA_CONTROL 0x003a +#define mmD5VGA_CONTROL_BASE_IDX 1 +#define mmD6VGA_CONTROL 0x003b +#define mmD6VGA_CONTROL_BASE_IDX 1 +#define mmVGA_SOURCE_SELECT 0x003c +#define mmVGA_SOURCE_SELECT_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +// base address: 0x0 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 +#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 +#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDP_DTO_DBUF_EN 0x0044 +#define mmDP_DTO_DBUF_EN_BASE_IDX 1 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmREFCLK_CNTL 0x0049 +#define mmREFCLK_CNTL_BASE_IDX 1 +#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c +#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define mmDCCG_PERFMON_CNTL2 0x004e +#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 +#define mmDCCG_DS_DTO_INCR 0x0053 +#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 +#define mmDCCG_DS_DTO_MODULO 0x0054 +#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 +#define mmDCCG_DS_CNTL 0x0055 +#define mmDCCG_DS_CNTL_BASE_IDX 1 +#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 +#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 +#define mmDPREFCLK_CNTL 0x0058 +#define mmDPREFCLK_CNTL_BASE_IDX 1 +#define mmDCE_VERSION 0x005e +#define mmDCE_VERSION_BASE_IDX 1 +#define mmDCCG_GTC_CNTL 0x0060 +#define mmDCCG_GTC_CNTL_BASE_IDX 1 +#define mmDCCG_GTC_DTO_INCR 0x0061 +#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 +#define mmDCCG_GTC_DTO_MODULO 0x0062 +#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 +#define mmDCCG_GTC_CURRENT 0x0063 +#define mmDCCG_GTC_CURRENT_BASE_IDX 1 +#define mmDSCCLK0_DTO_PARAM 0x006c +#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1 +#define mmDSCCLK1_DTO_PARAM 0x006d +#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1 +#define mmDSCCLK2_DTO_PARAM 0x006e +#define mmDSCCLK2_DTO_PARAM_BASE_IDX 1 +#define mmMILLISECOND_TIME_BASE_DIV 0x0070 +#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define mmDCCG_PERFMON_CNTL 0x0073 +#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 +#define mmDCCG_GATE_DISABLE_CNTL 0x0074 +#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 +#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_CAC_STATUS 0x0077 +#define mmDCCG_CAC_STATUS_BASE_IDX 1 +#define mmMICROSECOND_TIME_BASE_DIV 0x007b +#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define mmDCCG_GATE_DISABLE_CNTL2 0x007c +#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDCCG_DISP_CNTL_REG 0x007f +#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define mmOTG0_PIXEL_RATE_CNTL 0x0080 +#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO0_PHASE 0x0081 +#define mmDP_DTO0_PHASE_BASE_IDX 1 +#define mmDP_DTO0_MODULO 0x0082 +#define mmDP_DTO0_MODULO_BASE_IDX 1 +#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG1_PIXEL_RATE_CNTL 0x0084 +#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO1_PHASE 0x0085 +#define mmDP_DTO1_PHASE_BASE_IDX 1 +#define mmDP_DTO1_MODULO 0x0086 +#define mmDP_DTO1_MODULO_BASE_IDX 1 +#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG2_PIXEL_RATE_CNTL 0x0088 +#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO2_PHASE 0x0089 +#define mmDP_DTO2_PHASE_BASE_IDX 1 +#define mmDP_DTO2_MODULO 0x008a +#define mmDP_DTO2_MODULO_BASE_IDX 1 +#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b +#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmOTG3_PIXEL_RATE_CNTL 0x008c +#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDP_DTO3_PHASE 0x008d +#define mmDP_DTO3_PHASE_BASE_IDX 1 +#define mmDP_DTO3_MODULO 0x008e +#define mmDP_DTO3_MODULO_BASE_IDX 1 +#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f +#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 +#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define mmDPPCLK0_DTO_PARAM 0x0099 +#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1 +#define mmDPPCLK1_DTO_PARAM 0x009a +#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1 +#define mmDPPCLK2_DTO_PARAM 0x009b +#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1 +#define mmDPPCLK3_DTO_PARAM 0x009c +#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1 +#define mmDCCG_CAC_STATUS2 0x009f +#define mmDCCG_CAC_STATUS2_BASE_IDX 1 +#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 +#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 +#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKC_CLOCK_ENABLE 0x00a2 +#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKD_CLOCK_ENABLE 0x00a3 +#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 +#define mmSYMCLKE_CLOCK_ENABLE 0x00a4 +#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 +#define mmDCCG_SOFT_RESET 0x00a6 +#define mmDCCG_SOFT_RESET_BASE_IDX 1 +#define mmDSCCLK_DTO_CTRL 0x00a7 +#define mmDSCCLK_DTO_CTRL_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab +#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac +#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad +#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae +#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define mmDCCG_AUDIO_DTO1_MODULE 0x00af +#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 +#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 +#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 +#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 +#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 +#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 +#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 +#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 +#define mmDPPCLK_DTO_CTRL 0x00b6 +#define mmDPPCLK_DTO_CTRL_BASE_IDX 1 +#define mmDCCG_VSYNC_CNT_CTRL 0x00b8 +#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 +#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 +#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 +#define mmFORCE_SYMCLK_DISABLE 0x00ba +#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1 +#define mmDCCG_TEST_CLK_SEL 0x00be +#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +// base address: 0x0 +#define mmDENTIST_DISPCLK_CNTL 0x0064 +#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +// base address: 0x0 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 +#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 +#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CNTL 0x0003 +#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 +#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 +#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 +#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_HI 0x0007 +#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON0_PERFMON_LOW 0x0008 +#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +// base address: 0x30 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c +#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d +#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e +#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CNTL 0x000f +#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010 +#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 +#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 +#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_HI 0x0013 +#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON1_PERFMON_LOW 0x0014 +#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_pll_dispdec +// base address: 0x0 +#define mmPLL_MACRO_CNTL_RESERVED0 0x0018 +#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED1 0x0019 +#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED2 0x001a +#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED3 0x001b +#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED4 0x001c +#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED5 0x001d +#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED6 0x001e +#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED7 0x001f +#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED8 0x0020 +#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED9 0x0021 +#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED10 0x0022 +#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED11 0x0023 +#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED12 0x0024 +#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED13 0x0025 +#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED14 0x0026 +#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED15 0x0027 +#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED16 0x0028 +#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED17 0x0029 +#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED18 0x002a +#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED19 0x002b +#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED20 0x002c +#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED21 0x002d +#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED22 0x002e +#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED23 0x002f +#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED24 0x0030 +#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED25 0x0031 +#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED26 0x0032 +#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED27 0x0033 +#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED28 0x0034 +#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED29 0x0035 +#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED30 0x0036 +#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED31 0x0037 +#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED32 0x0038 +#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED33 0x0039 +#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED34 0x003a +#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED35 0x003b +#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED36 0x003c +#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED37 0x003d +#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED38 0x003e +#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED39 0x003f +#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED40 0x0040 +#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2 +#define mmPLL_MACRO_CNTL_RESERVED41 0x0041 +#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +// base address: 0x0 +#define mmRBBMIF_TIMEOUT 0x005b +#define mmRBBMIF_TIMEOUT_BASE_IDX 2 +#define mmRBBMIF_STATUS 0x005c +#define mmRBBMIF_STATUS_BASE_IDX 2 +#define mmRBBMIF_STATUS_2 0x005d +#define mmRBBMIF_STATUS_2_BASE_IDX 2 +#define mmRBBMIF_INT_STATUS 0x005e +#define mmRBBMIF_INT_STATUS_BASE_IDX 2 +#define mmRBBMIF_TIMEOUT_DIS 0x005f +#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define mmRBBMIF_TIMEOUT_DIS_2 0x0060 +#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 +#define mmRBBMIF_STATUS_FLAG 0x0061 +#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +// base address: 0x0 +#define mmDOMAIN0_PG_CONFIG 0x0080 +#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN0_PG_STATUS 0x0081 +#define mmDOMAIN0_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN1_PG_CONFIG 0x0082 +#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN1_PG_STATUS 0x0083 +#define mmDOMAIN1_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN2_PG_CONFIG 0x0084 +#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN2_PG_STATUS 0x0085 +#define mmDOMAIN2_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN3_PG_CONFIG 0x0086 +#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN3_PG_STATUS 0x0087 +#define mmDOMAIN3_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN4_PG_CONFIG 0x0088 +#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN4_PG_STATUS 0x0089 +#define mmDOMAIN4_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN5_PG_CONFIG 0x008a +#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN5_PG_STATUS 0x008b +#define mmDOMAIN5_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN6_PG_CONFIG 0x008c +#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN6_PG_STATUS 0x008d +#define mmDOMAIN6_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN7_PG_CONFIG 0x008e +#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN7_PG_STATUS 0x008f +#define mmDOMAIN7_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN16_PG_CONFIG 0x00a1 +#define mmDOMAIN16_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN16_PG_STATUS 0x00a2 +#define mmDOMAIN16_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN17_PG_CONFIG 0x00a3 +#define mmDOMAIN17_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN17_PG_STATUS 0x00a4 +#define mmDOMAIN17_PG_STATUS_BASE_IDX 2 +#define mmDOMAIN18_PG_CONFIG 0x00a5 +#define mmDOMAIN18_PG_CONFIG_BASE_IDX 2 +#define mmDOMAIN18_PG_STATUS 0x00a6 +#define mmDOMAIN18_PG_STATUS_BASE_IDX 2 +#define mmDCPG_INTERRUPT_STATUS 0x00ad +#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCPG_INTERRUPT_STATUS_2 0x00ae +#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 +#define mmDCPG_INTERRUPT_CONTROL_1 0x00af +#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 +#define mmDCPG_INTERRUPT_CONTROL_2 0x00b0 +#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 +#define mmDCPG_INTERRUPT_CONTROL_3 0x00b1 +#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 +#define mmDC_IP_REQUEST_CNTL 0x00b2 +#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +// base address: 0x2f8 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be +#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf +#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 +#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1 +#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2 +#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 +#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 +#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_HI 0x00c5 +#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON2_PERFMON_LOW 0x00c6 +#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +// base address: 0x0 +#define mmCC_DC_PIPE_DIS 0x00ca +#define mmCC_DC_PIPE_DIS_BASE_IDX 2 +#define mmDMU_CLK_CNTL 0x00cb +#define mmDMU_CLK_CNTL_BASE_IDX 2 +#define mmDMU_MEM_PWR_CNTL 0x00cc +#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 +#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd +#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 +#define mmSMU_INTERRUPT_CONTROL 0x00ce +#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6 +#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +// base address: 0x0 +#define mmDMCU_CTRL 0x00da +#define mmDMCU_CTRL_BASE_IDX 2 +#define mmDMCU_STATUS 0x00db +#define mmDMCU_STATUS_BASE_IDX 2 +#define mmDMCU_PC_START_ADDR 0x00dc +#define mmDMCU_PC_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_START_ADDR 0x00dd +#define mmDMCU_FW_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_END_ADDR 0x00de +#define mmDMCU_FW_END_ADDR_BASE_IDX 2 +#define mmDMCU_FW_ISR_START_ADDR 0x00df +#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 +#define mmDMCU_FW_CS_HI 0x00e0 +#define mmDMCU_FW_CS_HI_BASE_IDX 2 +#define mmDMCU_FW_CS_LO 0x00e1 +#define mmDMCU_FW_CS_LO_BASE_IDX 2 +#define mmDMCU_RAM_ACCESS_CTRL 0x00e2 +#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_WR_CTRL 0x00e3 +#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_WR_DATA 0x00e4 +#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 +#define mmDMCU_ERAM_RD_CTRL 0x00e5 +#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 +#define mmDMCU_ERAM_RD_DATA 0x00e6 +#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 +#define mmDMCU_IRAM_WR_CTRL 0x00e7 +#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 +#define mmDMCU_IRAM_WR_DATA 0x00e8 +#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 +#define mmDMCU_IRAM_RD_CTRL 0x00e9 +#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 +#define mmDMCU_IRAM_RD_DATA 0x00ea +#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 +#define mmDMCU_EVENT_TRIGGER 0x00eb +#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 +#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec +#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed +#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS 0x00ee +#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_1 0x00ef +#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 +#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 +#define mmDC_DMCU_SCRATCH 0x00f5 +#define mmDC_DMCU_SCRATCH_BASE_IDX 2 +#define mmDMCU_INT_CNT 0x00f6 +#define mmDMCU_INT_CNT_BASE_IDX 2 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 +#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 +#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8 +#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG1 0x00f9 +#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG2 0x00fa +#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 +#define mmMASTER_COMM_DATA_REG3 0x00fb +#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 +#define mmMASTER_COMM_CMD_REG 0x00fc +#define mmMASTER_COMM_CMD_REG_BASE_IDX 2 +#define mmMASTER_COMM_CNTL_REG 0x00fd +#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG1 0x00fe +#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG2 0x00ff +#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 +#define mmSLAVE_COMM_DATA_REG3 0x0100 +#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 +#define mmSLAVE_COMM_CMD_REG 0x0101 +#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 +#define mmSLAVE_COMM_CNTL_REG 0x0102 +#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 +#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 +#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 +#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 +#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 +#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 +#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 +#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 +#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 +#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 +#define mmDMCU_INT_CNT_CONTINUE 0x011c +#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d +#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2 +#define mmDMCU_INTERRUPT_STATUS_2 0x011e +#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2 +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f +#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_ihc_dispdec +// base address: 0x0 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 +#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 +#define mmDC_GPU_TIMER_READ 0x0128 +#define mmDC_GPU_TIMER_READ_BASE_IDX 2 +#define mmDC_GPU_TIMER_READ_CNTL 0x0129 +#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS 0x012a +#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b +#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c +#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d +#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e +#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f +#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 +#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 +#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 +#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 +#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 +#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 +#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 +#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 +#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 +#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 +#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a +#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b +#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c +#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d +#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e +#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f +#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 +#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 +#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 +#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 +#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 +#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 +#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 +#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 +#define mmDCCG_INTERRUPT_DEST 0x0147 +#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2 +#define mmDMU_INTERRUPT_DEST 0x0148 +#define mmDMU_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCPG_INTERRUPT_DEST 0x0149 +#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCPG_INTERRUPT_DEST2 0x014a +#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2 +#define mmMMHUBBUB_INTERRUPT_DEST 0x014b +#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 +#define mmWB_INTERRUPT_DEST 0x014c +#define mmWB_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCHUB_INTERRUPT_DEST 0x014d +#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x014e +#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCHUB_INTERRUPT_DEST2 0x014f +#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2 +#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0150 +#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define mmMPC_INTERRUPT_DEST 0x0151 +#define mmMPC_INTERRUPT_DEST_BASE_IDX 2 +#define mmOPP_INTERRUPT_DEST 0x0152 +#define mmOPP_INTERRUPT_DEST_BASE_IDX 2 +#define mmOPTC_INTERRUPT_DEST 0x0153 +#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG0_INTERRUPT_DEST 0x0154 +#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG1_INTERRUPT_DEST 0x0155 +#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG2_INTERRUPT_DEST 0x0156 +#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG3_INTERRUPT_DEST 0x0157 +#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG4_INTERRUPT_DEST 0x0158 +#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2 +#define mmOTG5_INTERRUPT_DEST 0x0159 +#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2 +#define mmDIG_INTERRUPT_DEST 0x015a +#define mmDIG_INTERRUPT_DEST_BASE_IDX 2 +#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015b +#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 +#define mmDIO_INTERRUPT_DEST 0x015d +#define mmDIO_INTERRUPT_DEST_BASE_IDX 2 +#define mmDCIO_INTERRUPT_DEST 0x015e +#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2 +#define mmHPD_INTERRUPT_DEST 0x015f +#define mmHPD_INTERRUPT_DEST_BASE_IDX 2 +#define mmAZ_INTERRUPT_DEST 0x0160 +#define mmAZ_INTERRUPT_DEST_BASE_IDX 2 +#define mmAUX_INTERRUPT_DEST 0x0161 +#define mmAUX_INTERRUPT_DEST_BASE_IDX 2 +#define mmDSC_INTERRUPT_DEST 0x0162 +#define mmDSC_INTERRUPT_DEST_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec +// base address: 0x0 +#define mmWB_ENABLE 0x01da +#define mmWB_ENABLE_BASE_IDX 2 +#define mmWB_EC_CONFIG 0x01db +#define mmWB_EC_CONFIG_BASE_IDX 2 +#define mmCNV_MODE 0x01dc +#define mmCNV_MODE_BASE_IDX 2 +#define mmCNV_WINDOW_START 0x01dd +#define mmCNV_WINDOW_START_BASE_IDX 2 +#define mmCNV_WINDOW_SIZE 0x01de +#define mmCNV_WINDOW_SIZE_BASE_IDX 2 +#define mmCNV_UPDATE 0x01df +#define mmCNV_UPDATE_BASE_IDX 2 +#define mmCNV_SOURCE_SIZE 0x01e0 +#define mmCNV_SOURCE_SIZE_BASE_IDX 2 +#define mmCNV_TEST_CNTL 0x01ee +#define mmCNV_TEST_CNTL_BASE_IDX 2 +#define mmCNV_TEST_CRC_RED 0x01ef +#define mmCNV_TEST_CRC_RED_BASE_IDX 2 +#define mmCNV_TEST_CRC_GREEN 0x01f0 +#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2 +#define mmCNV_TEST_CRC_BLUE 0x01f1 +#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2 +#define mmWB_DEBUG_CTRL 0x01f2 +#define mmWB_DEBUG_CTRL_BASE_IDX 2 +#define mmWB_DBG_MODE 0x01f3 +#define mmWB_DBG_MODE_BASE_IDX 2 +#define mmWB_HW_DEBUG 0x01f4 +#define mmWB_HW_DEBUG_BASE_IDX 2 +#define mmWB_SOFT_RESET 0x01f5 +#define mmWB_SOFT_RESET_BASE_IDX 2 +#define mmWB_WARM_UP_MODE_CTL1 0x01f6 +#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2 +#define mmWB_WARM_UP_MODE_CTL2 0x01f7 +#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2 +#define mmCNV_TEST_DEBUG_INDEX 0x01f8 +#define mmCNV_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmCNV_TEST_DEBUG_DATA 0x01f9 +#define mmCNV_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec +// base address: 0x0 +#define mmWBSCL_COEF_RAM_SELECT 0x020a +#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2 +#define mmWBSCL_COEF_RAM_TAP_DATA 0x020b +#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmWBSCL_MODE 0x020c +#define mmWBSCL_MODE_BASE_IDX 2 +#define mmWBSCL_TAP_CONTROL 0x020d +#define mmWBSCL_TAP_CONTROL_BASE_IDX 2 +#define mmWBSCL_DEST_SIZE 0x020e +#define mmWBSCL_DEST_SIZE_BASE_IDX 2 +#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x020f +#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210 +#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 +#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0211 +#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 +#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x0212 +#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x0213 +#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 +#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x0214 +#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 +#define mmWBSCL_ROUND_OFFSET 0x0215 +#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2 +#define mmWBSCL_OVERFLOW_STATUS 0x0216 +#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2 +#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0217 +#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 +#define mmWBSCL_TEST_CNTL 0x0218 +#define mmWBSCL_TEST_CNTL_BASE_IDX 2 +#define mmWBSCL_TEST_CRC_RED 0x0219 +#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2 +#define mmWBSCL_TEST_CRC_GREEN 0x021a +#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2 +#define mmWBSCL_TEST_CRC_BLUE 0x021b +#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2 +#define mmWBSCL_BACKPRESSURE_CNT_EN 0x021c +#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define mmWB_MCIF_BACKPRESSURE_CNT 0x021d +#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 +#define mmWBSCL_CLAMP_Y_RGB 0x021e +#define mmWBSCL_CLAMP_Y_RGB_BASE_IDX 2 +#define mmWBSCL_CLAMP_CBCR 0x021f +#define mmWBSCL_CLAMP_CBCR_BASE_IDX 2 +#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0220 +#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 +#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR 0x0221 +#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR_BASE_IDX 2 +#define mmWBSCL_DEBUG 0x0222 +#define mmWBSCL_DEBUG_BASE_IDX 2 +#define mmWBSCL_TEST_DEBUG_INDEX 0x0223 +#define mmWBSCL_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmWBSCL_TEST_DEBUG_DATA 0x0224 +#define mmWBSCL_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +// base address: 0x8e8 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a +#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b +#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c +#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CNTL 0x023d +#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CNTL2 0x023e +#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f +#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240 +#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_HI 0x0241 +#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON3_PERFMON_LOW 0x0242 +#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +// base address: 0x0 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5 +#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7 +#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9 +#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb +#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd +#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be +#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf +#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x02c0 +#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x02c1 +#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2 +#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4 +#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5 +#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6 +#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7 +#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8 +#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9 +#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL 0x02da +#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db +#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc +#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x02dd +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH 0x02de +#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x02df +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH 0x02e0 +#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x02e1 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH 0x02e2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x02e3 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH 0x02e4 +#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION 0x02e5 +#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION 0x02e6 +#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION 0x02e7 +#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION 0x02e8 +#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec +// base address: 0x100 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5 +#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7 +#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9 +#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb +#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd +#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe +#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff +#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x0300 +#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x0301 +#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312 +#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314 +#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315 +#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316 +#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317 +#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318 +#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319 +#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b +#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c +#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x031d +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH 0x031e +#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x031f +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH 0x0320 +#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x0321 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH 0x0322 +#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x0323 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH 0x0324 +#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION 0x0325 +#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION 0x0326 +#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION 0x0327 +#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION 0x0328 +#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +// base address: 0x0 +#define mmWBIF0_MISC_CTRL 0x0333 +#define mmWBIF0_MISC_CTRL_BASE_IDX 2 +#define mmWBIF0_SMU_WM_CONTROL 0x0334 +#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2 +#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 +#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 +#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmVGA_SRC_SPLIT_CNTL 0x033f +#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_MEM_PWR_STATUS 0x0340 +#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define mmMMHUBBUB_MEM_PWR_CNTL 0x0341 +#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_CLOCK_CNTL 0x0342 +#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define mmMMHUBBUB_SOFT_RESET 0x0343 +#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 +#define mmDMU_IF_ERR_STATUS 0x0347 +#define mmDMU_IF_ERR_STATUS_BASE_IDX 2 +#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0348 +#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +// base address: 0x0 +#define mmMCIF_CONTROL 0x034a +#define mmMCIF_CONTROL_BASE_IDX 2 +#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b +#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e +#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f +#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 +#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0xd48 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 +#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0354 +#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CNTL 0x0355 +#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CNTL2 0x0356 +#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 +#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 +#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_HI 0x0359 +#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON4_PERFMON_LOW 0x035a +#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +// base address: 0x0 +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e +#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f +#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +// base address: 0x8 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 +#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 +#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +// base address: 0x10 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 +#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 +#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +// base address: 0x18 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 +#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 +#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +// base address: 0x20 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 +#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 +#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +// base address: 0x28 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 +#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 +#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +// base address: 0x30 +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a +#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b +#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +// base address: 0x38 +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c +#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d +#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_misc_dispdec +// base address: 0x0 +#define mmAZ_CLOCK_CNTL 0x0372 +#define mmAZ_CLOCK_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +// base address: 0xde8 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x037a +#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b +#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x037c +#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CNTL 0x037d +#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CNTL2 0x037e +#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f +#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 +#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_HI 0x0381 +#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON5_PERFMON_LOW 0x0382 +#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +// base address: 0x0 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 +#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +// base address: 0x18 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d +#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +// base address: 0x30 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 +#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +// base address: 0x48 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 +#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +// base address: 0x60 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f +#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +// base address: 0x78 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 +#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +// base address: 0x90 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab +#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +// base address: 0xa8 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 +#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +// base address: 0x0 +#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 +#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define mmAZALIA_AUDIO_DTO 0x03c3 +#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 +#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 +#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define mmAZALIA_SOCCLK_CONTROL 0x03c5 +#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 +#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define mmAZALIA_DATA_DMA_CONTROL 0x03c7 +#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_BDL_DMA_CONTROL 0x03c8 +#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 +#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define mmAZALIA_CORB_DMA_CONTROL 0x03ca +#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 +#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 +#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 +#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 +#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 +#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 +#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 +#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 +#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 +#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da +#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db +#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc +#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd +#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de +#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df +#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 +#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 +#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 +#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL0 0x03e3 +#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL1 0x03e4 +#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL2 0x03e5 +#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define mmAZALIA_CRC0_CONTROL3 0x03e6 +#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define mmAZALIA_CRC0_RESULT 0x03e7 +#define mmAZALIA_CRC0_RESULT_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL0 0x03e8 +#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL1 0x03e9 +#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL2 0x03ea +#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define mmAZALIA_CRC1_CONTROL3 0x03eb +#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define mmAZALIA_CRC1_RESULT 0x03ec +#define mmAZALIA_CRC1_RESULT_BASE_IDX 2 +#define mmAZALIA_MEM_PWR_CTRL 0x03ee +#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define mmAZALIA_MEM_PWR_STATUS 0x03ef +#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0root_dispdec +// base address: 0x0 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 +#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 +#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 +#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d +#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 +#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 +#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 +#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 +#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 +#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 +#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 +#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 +#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a +#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 +#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b +#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c +#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d +#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +// base address: 0x320 +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 +#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 +#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +// base address: 0x328 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 +#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 +#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +// base address: 0x330 +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a +#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b +#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +// base address: 0x338 +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c +#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d +#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +// base address: 0x340 +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e +#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f +#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +// base address: 0x348 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 +#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 +#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +// base address: 0x350 +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 +#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 +#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +// base address: 0x358 +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 +#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 +#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +// base address: 0x0 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b +#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +// base address: 0x10 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f +#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +// base address: 0x20 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 +#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +// base address: 0x30 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 +#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +// base address: 0x40 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b +#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +// base address: 0x50 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f +#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +// base address: 0x60 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 +#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +// base address: 0x70 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 +#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec +// base address: 0x0 +#define mmDCHUBBUB_SDPIF_CFG0 0x048f +#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 +#define mmVM_REQUEST_PHYSICAL 0x0490 +#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2 +#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 +#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 +#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 +#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 +#define mmDCN_VM_FB_LOCATION_BASE 0x0493 +#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 +#define mmDCN_VM_FB_LOCATION_TOP 0x0494 +#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 +#define mmDCN_VM_FB_OFFSET 0x0495 +#define mmDCN_VM_FB_OFFSET_BASE_IDX 2 +#define mmDCN_VM_AGP_BOT 0x0496 +#define mmDCN_VM_AGP_BOT_BASE_IDX 2 +#define mmDCN_VM_AGP_TOP 0x0497 +#define mmDCN_VM_AGP_TOP_BASE_IDX 2 +#define mmDCN_VM_AGP_BASE 0x0498 +#define mmDCN_VM_AGP_BASE_BASE_IDX 2 +#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499 +#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 +#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a +#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 +#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b +#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8 +#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x04b9 +#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba +#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb +#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_CFG1 0x04bf +#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 +#define mmDCHUBBUB_SDPIF_CFG2 0x04c0 +#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec +// base address: 0x0 +#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf +#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 +#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 +#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 +#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 +#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9 +#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db +#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd +#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df +#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef +#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0 +#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_CRC_CTRL 0x04f1 +#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 +#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2 +#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 +#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3 +#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 +#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4 +#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 +#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5 +#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_dispdec +// base address: 0x0 +#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 +#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 +#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 +#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 +#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 +#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 +#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519 +#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a +#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b +#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c +#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d +#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e +#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 +#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f +#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 +#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 +#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 +#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 +#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 +#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 +#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 +#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 +#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 +#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 +#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 +#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 +#define mmVTG0_CONTROL 0x0528 +#define mmVTG0_CONTROL_BASE_IDX 2 +#define mmVTG1_CONTROL 0x0529 +#define mmVTG1_CONTROL_BASE_IDX 2 +#define mmVTG2_CONTROL 0x052a +#define mmVTG2_CONTROL_BASE_IDX 2 +#define mmVTG3_CONTROL 0x052b +#define mmVTG3_CONTROL_BASE_IDX 2 +#define mmDCHUBBUB_SOFT_RESET 0x052e +#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 +#define mmDCHUBBUB_CLOCK_CNTL 0x052f +#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define mmDCFCLK_CNTL 0x0530 +#define mmDCFCLK_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 +#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 +#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 +#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 +#define mmDCHUBBUB_CTRL_STATUS 0x0534 +#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a +#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 +#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b +#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 +#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c +#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d +#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e +#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546 +#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 +#define mmDCHUBBUB_ARB_HOSTVM_CNTL 0x0547 +#define mmDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 +#define mmFMON_CTRL 0x0548 +#define mmFMON_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0x1534 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x054d +#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e +#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x054f +#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CNTL 0x0550 +#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CNTL2 0x0551 +#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 +#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 +#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_HI 0x0554 +#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON6_PERFMON_LOW 0x0555 +#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec +// base address: 0x0 +#define mmDCN_VM_CONTEXT0_CNTL 0x0559 +#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f +#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_CNTL 0x0560 +#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 +#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_CNTL 0x0567 +#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d +#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_CNTL 0x056e +#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 +#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_CNTL 0x0575 +#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b +#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_CNTL 0x057c +#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 +#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_CNTL 0x0583 +#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 +#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_CNTL 0x058a +#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 +#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_CNTL 0x0591 +#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 +#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_CNTL 0x0598 +#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e +#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_CNTL 0x059f +#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 +#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_CNTL 0x05a6 +#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac +#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_CNTL 0x05ad +#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 +#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_CNTL 0x05b4 +#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba +#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_CNTL 0x05bb +#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 +#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_CNTL 0x05c2 +#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 +#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9 +#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca +#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define mmDCN_VM_FAULT_CNTL 0x05cb +#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2 +#define mmDCN_VM_FAULT_STATUS 0x05cc +#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2 +#define mmDCN_VM_FAULT_ADDR_MSB 0x05cd +#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 +#define mmDCN_VM_FAULT_ADDR_LSB 0x05ce +#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +// base address: 0x0 +#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 +#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6 +#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7 +#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb +#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec +#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef +#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 +#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 +#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP0_DCHUBP_CNTL 0x05f3 +#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP0_HUBP_CLK_CNTL 0x05f4 +#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 +#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6 +#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP0_HUBPREQ_DEBUG 0x05f7 +#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc +#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +// base address: 0x0 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 +#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609 +#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d +#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 +#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 +#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 +#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a +#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c +#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620 +#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624 +#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628 +#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x062c +#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062d +#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062e +#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062f +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0630 +#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0631 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0632 +#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0633 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0634 +#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0635 +#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0636 +#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0637 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0638 +#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0645 +#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ0_BLANK_OFFSET_0 0x0646 +#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ0_BLANK_OFFSET_1 0x0647 +#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ0_DST_DIMENSIONS 0x0648 +#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ0_DST_AFTER_SCALER 0x0649 +#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ0_PREFETCH_SETTINGS 0x064a +#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x064b +#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064c +#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064d +#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064e +#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064f +#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x0650 +#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x0651 +#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0652 +#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0653 +#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0654 +#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0655 +#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0656 +#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0657 +#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0658 +#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0659 +#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_6 0x065a +#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ0_NOM_PARAMETERS_7 0x065b +#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065c +#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065d +#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ0_CURSOR_SETTINGS 0x065e +#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065f +#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0660 +#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0661 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0662 +#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0665 +#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0666 +#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0667 +#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0668 +#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0669 +#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ0_FLIP_PARAMETERS_6 0x066a +#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +// base address: 0x0 +#define mmHUBPRET0_HUBPRET_CONTROL 0x066c +#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d +#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e +#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 +#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671 +#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672 +#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673 +#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 +#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 +#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +// base address: 0x0 +#define mmCURSOR0_0_CURSOR_CONTROL 0x0678 +#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 +#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a +#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_SIZE 0x067b +#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_POSITION 0x067c +#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d +#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e +#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f +#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 +#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 +#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 +#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 +#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_CNTL 0x0684 +#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685 +#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_STATUS 0x0686 +#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687 +#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 +#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688 +#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a74 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x069d +#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e +#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x069f +#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CNTL 0x06a0 +#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CNTL2 0x06a1 +#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 +#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 +#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_HI 0x06a4 +#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON7_PERFMON_LOW 0x06a5 +#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +// base address: 0x370 +#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 +#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2 +#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3 +#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 +#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb +#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc +#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce +#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP1_DCHUBP_CNTL 0x06cf +#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP1_HUBP_CLK_CNTL 0x06d0 +#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 +#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2 +#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP1_HUBPREQ_DEBUG 0x06d3 +#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8 +#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +// base address: 0x370 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 +#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5 +#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 +#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed +#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 +#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 +#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 +#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 +#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc +#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700 +#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704 +#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0708 +#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0709 +#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x070a +#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x070b +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x070c +#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070d +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070e +#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070f +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0710 +#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0711 +#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0712 +#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0713 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0714 +#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0721 +#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ1_BLANK_OFFSET_0 0x0722 +#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ1_BLANK_OFFSET_1 0x0723 +#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ1_DST_DIMENSIONS 0x0724 +#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ1_DST_AFTER_SCALER 0x0725 +#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0726 +#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0727 +#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0728 +#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0729 +#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x072a +#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x072b +#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072c +#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072d +#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072e +#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072f +#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_0 0x0730 +#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_1 0x0731 +#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0732 +#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0733 +#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0734 +#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0735 +#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0736 +#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0737 +#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0738 +#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0739 +#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ1_CURSOR_SETTINGS 0x073a +#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x073b +#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073c +#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073d +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073e +#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x0741 +#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0742 +#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0743 +#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0744 +#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0745 +#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0746 +#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +// base address: 0x370 +#define mmHUBPRET1_HUBPRET_CONTROL 0x0748 +#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 +#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a +#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c +#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d +#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e +#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f +#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 +#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 +#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +// base address: 0x370 +#define mmCURSOR0_1_CURSOR_CONTROL 0x0754 +#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 +#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 +#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_SIZE 0x0757 +#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_POSITION 0x0758 +#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759 +#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a +#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b +#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c +#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d +#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e +#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f +#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_CNTL 0x0760 +#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761 +#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_STATUS 0x0762 +#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763 +#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 +#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764 +#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1de4 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a +#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x077b +#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CNTL 0x077c +#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CNTL2 0x077d +#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e +#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f +#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_HI 0x0780 +#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON8_PERFMON_LOW 0x0781 +#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +// base address: 0x6e0 +#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d +#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e +#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f +#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 +#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 +#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa +#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP2_DCHUBP_CNTL 0x07ab +#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP2_HUBP_CLK_CNTL 0x07ac +#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad +#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae +#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP2_HUBPREQ_DEBUG 0x07af +#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4 +#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +// base address: 0x6e0 +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 +#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1 +#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 +#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 +#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd +#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 +#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 +#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 +#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8 +#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc +#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0 +#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e4 +#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e5 +#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e6 +#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e7 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e8 +#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e9 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07ea +#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07eb +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07ec +#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ed +#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ee +#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ef +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07f0 +#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fd +#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fe +#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ2_BLANK_OFFSET_1 0x07ff +#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ2_DST_DIMENSIONS 0x0800 +#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ2_DST_AFTER_SCALER 0x0801 +#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0802 +#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0803 +#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0804 +#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0805 +#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0806 +#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0807 +#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0808 +#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0809 +#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ2_FLIP_PARAMETERS_1 0x080a +#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x080b +#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_0 0x080c +#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_1 0x080d +#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_2 0x080e +#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_3 0x080f +#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_4 0x0810 +#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_5 0x0811 +#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0812 +#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0813 +#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0814 +#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0815 +#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ2_CURSOR_SETTINGS 0x0816 +#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0817 +#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0818 +#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0819 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x081a +#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_5 0x081d +#define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ2_VBLANK_PARAMETERS_6 0x081e +#define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ2_FLIP_PARAMETERS_3 0x081f +#define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ2_FLIP_PARAMETERS_4 0x0820 +#define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ2_FLIP_PARAMETERS_5 0x0821 +#define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ2_FLIP_PARAMETERS_6 0x0822 +#define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +// base address: 0x6e0 +#define mmHUBPRET2_HUBPRET_CONTROL 0x0824 +#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 +#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 +#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 +#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829 +#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a +#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b +#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c +#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d +#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +// base address: 0x6e0 +#define mmCURSOR0_2_CURSOR_CONTROL 0x0830 +#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 +#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 +#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_SIZE 0x0833 +#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_POSITION 0x0834 +#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835 +#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 +#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837 +#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 +#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 +#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a +#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b +#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define mmCURSOR0_2_DMDATA_CNTL 0x083c +#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 +#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d +#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 +#define mmCURSOR0_2_DMDATA_STATUS 0x083e +#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 +#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f +#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 +#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840 +#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x2154 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 +#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0857 +#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CNTL 0x0858 +#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CNTL2 0x0859 +#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a +#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b +#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_HI 0x085c +#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON9_PERFMON_LOW 0x085d +#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +// base address: 0xa50 +#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879 +#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a +#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b +#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f +#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 +#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 +#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 +#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define mmHUBP3_DCHUBP_CNTL 0x0887 +#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2 +#define mmHUBP3_HUBP_CLK_CNTL 0x0888 +#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 +#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889 +#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a +#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP3_HUBPREQ_DEBUG 0x088b +#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890 +#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +// base address: 0xa50 +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c +#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define mmHUBPREQ3_VMID_SETTINGS_0 0x089d +#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 +#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 +#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 +#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad +#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae +#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 +#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4 +#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8 +#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc +#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08c0 +#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 +#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08c1 +#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 +#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08c2 +#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c3 +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c4 +#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c5 +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c6 +#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c7 +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c8 +#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c9 +#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08ca +#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08cb +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08cc +#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d9 +#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define mmHUBPREQ3_BLANK_OFFSET_0 0x08da +#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 +#define mmHUBPREQ3_BLANK_OFFSET_1 0x08db +#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 +#define mmHUBPREQ3_DST_DIMENSIONS 0x08dc +#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 +#define mmHUBPREQ3_DST_AFTER_SCALER 0x08dd +#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 +#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08de +#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08df +#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08e0 +#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08e1 +#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e3 +#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e4 +#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e5 +#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e6 +#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e7 +#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e8 +#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e9 +#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_2 0x08ea +#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_3 0x08eb +#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ec +#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08ed +#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ee +#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ef +#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 +#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08f0 +#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08f1 +#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 +#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f2 +#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 +#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f3 +#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f4 +#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f5 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f6 +#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_5 0x08f9 +#define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ3_VBLANK_PARAMETERS_6 0x08fa +#define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define mmHUBPREQ3_FLIP_PARAMETERS_3 0x08fb +#define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 +#define mmHUBPREQ3_FLIP_PARAMETERS_4 0x08fc +#define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 +#define mmHUBPREQ3_FLIP_PARAMETERS_5 0x08fd +#define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 +#define mmHUBPREQ3_FLIP_PARAMETERS_6 0x08fe +#define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +// base address: 0xa50 +#define mmHUBPRET3_HUBPRET_CONTROL 0x0900 +#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 +#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 +#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 +#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905 +#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906 +#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907 +#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 +#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 +#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +// base address: 0xa50 +#define mmCURSOR0_3_CURSOR_CONTROL 0x090c +#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d +#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e +#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_SIZE 0x090f +#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_POSITION 0x0910 +#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911 +#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 +#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913 +#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 +#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 +#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 +#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 +#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define mmCURSOR0_3_DMDATA_CNTL 0x0918 +#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 +#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919 +#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 +#define mmCURSOR0_3_DMDATA_STATUS 0x091a +#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 +#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b +#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 +#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c +#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x24c4 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 +#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0933 +#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CNTL 0x0934 +#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CNTL2 0x0935 +#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 +#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 +#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_HI 0x0938 +#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON10_PERFMON_LOW 0x0939 +#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +// base address: 0x0 +#define mmDPP_TOP0_DPP_CONTROL 0x0cc5 +#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6 +#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 +#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 +#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9 +#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca +#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +// base address: 0x0 +#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf +#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0 +#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 +#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 +#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 +#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 +#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 +#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 +#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 +#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 +#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 +#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 +#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda +#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb +#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 +#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd +#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +// base address: 0x0 +#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0ce0 +#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0ce1 +#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0ce2 +#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0ce3 +#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +// base address: 0x0 +#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cea +#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0ceb +#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL0_SCL_MODE 0x0cec +#define mmDSCL0_SCL_MODE_BASE_IDX 2 +#define mmDSCL0_SCL_TAP_CONTROL 0x0ced +#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL0_DSCL_CONTROL 0x0cee +#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cef +#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cf0 +#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0cf1 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0cf2 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0cf3 +#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0cf4 +#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0cf5 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0cf6 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0cf7 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0cf8 +#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0cf9 +#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0cfa +#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL0_SCL_BLACK_OFFSET 0x0cfb +#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2 +#define mmDSCL0_DSCL_UPDATE 0x0cfc +#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL0_DSCL_AUTOCAL 0x0cfd +#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0cfe +#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0cff +#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL0_OTG_H_BLANK 0x0d00 +#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL0_OTG_V_BLANK 0x0d01 +#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL0_RECOUT_START 0x0d02 +#define mmDSCL0_RECOUT_START_BASE_IDX 2 +#define mmDSCL0_RECOUT_SIZE 0x0d03 +#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL0_MPC_SIZE 0x0d04 +#define mmDSCL0_MPC_SIZE_BASE_IDX 2 +#define mmDSCL0_LB_DATA_FORMAT 0x0d05 +#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL0_LB_MEMORY_CTRL 0x0d06 +#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL0_LB_V_COUNTER 0x0d07 +#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d08 +#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d09 +#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL0_OBUF_CONTROL 0x0d0a +#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d0b +#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +// base address: 0x0 +#define mmCM0_CM_CONTROL 0x0d1a +#define mmCM0_CM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_ICSC_CONTROL 0x0d1b +#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2 +#define mmCM0_CM_ICSC_C11_C12 0x0d1c +#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2 +#define mmCM0_CM_ICSC_C13_C14 0x0d1d +#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2 +#define mmCM0_CM_ICSC_C21_C22 0x0d1e +#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2 +#define mmCM0_CM_ICSC_C23_C24 0x0d1f +#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2 +#define mmCM0_CM_ICSC_C31_C32 0x0d20 +#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2 +#define mmCM0_CM_ICSC_C33_C34 0x0d21 +#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2 +#define mmCM0_CM_ICSC_B_C11_C12 0x0d22 +#define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX 2 +#define mmCM0_CM_ICSC_B_C13_C14 0x0d23 +#define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX 2 +#define mmCM0_CM_ICSC_B_C21_C22 0x0d24 +#define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX 2 +#define mmCM0_CM_ICSC_B_C23_C24 0x0d25 +#define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX 2 +#define mmCM0_CM_ICSC_B_C31_C32 0x0d26 +#define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX 2 +#define mmCM0_CM_ICSC_B_C33_C34 0x0d27 +#define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d28 +#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d29 +#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d2a +#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d2b +#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d2c +#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d2d +#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d2e +#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d2f +#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d30 +#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d31 +#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d32 +#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d33 +#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d34 +#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define mmCM0_CM_BIAS_CR_R 0x0d35 +#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2 +#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d36 +#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_CONTROL 0x0d37 +#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_DGAM_LUT_INDEX 0x0d38 +#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_DGAM_LUT_DATA 0x0d39 +#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2 +#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0d3a +#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0d3b +#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0d3c +#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0d3d +#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0d3e +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0d3f +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0d40 +#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0d41 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0d42 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0d43 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0d44 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0d45 +#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0d46 +#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0d47 +#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0d48 +#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0d49 +#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0d4a +#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0d4b +#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0d4c +#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0d4d +#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0d4e +#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0d4f +#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0d50 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0d51 +#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0d52 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0d53 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0d54 +#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0d55 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0d56 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0d57 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0d58 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0d59 +#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0d5a +#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0d5b +#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0d5c +#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0d5d +#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0d5e +#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0d5f +#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0d60 +#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0d61 +#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0d62 +#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_CONTROL 0x0d63 +#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d64 +#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d65 +#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0d66 +#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d67 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d68 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d69 +#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0d6a +#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0d6b +#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0d6c +#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d6d +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d6e +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d6f +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d70 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d71 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d72 +#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d73 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d74 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d75 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0d76 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0d77 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0d78 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0d79 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0d7a +#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0d7b +#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0d7c +#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0d7d +#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0d7e +#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0d7f +#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0d80 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0d81 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0d82 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0d83 +#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0d84 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0d85 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0d86 +#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0d87 +#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0d88 +#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0d89 +#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0d8a +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0d8b +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0d8c +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0d8d +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0d8e +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0d8f +#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0d90 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0d91 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0d92 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0d93 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0d94 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0d95 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0d96 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0d97 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0d98 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0d99 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0d9a +#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0d9b +#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0d9c +#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0d9d +#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0d9e +#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0d9f +#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0da0 +#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_HDR_MULT_COEF 0x0da1 +#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_CTRL 0x0da2 +#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_STATUS 0x0da3 +#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCM0_CM_DEALPHA 0x0da5 +#define mmCM0_CM_DEALPHA_BASE_IDX 2 +#define mmCM0_CM_COEF_FORMAT 0x0da6 +#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2 +#define mmCM0_CM_SHAPER_CONTROL 0x0da7 +#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2 +#define mmCM0_CM_SHAPER_OFFSET_R 0x0da8 +#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_OFFSET_G 0x0da9 +#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_OFFSET_B 0x0daa +#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_SCALE_R 0x0dab +#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_SCALE_G_B 0x0dac +#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_LUT_INDEX 0x0dad +#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_SHAPER_LUT_DATA 0x0dae +#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0daf +#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0db0 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0db1 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0db2 +#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0db3 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0db4 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0db5 +#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0db6 +#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0db7 +#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0db8 +#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0db9 +#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dba +#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0dbb +#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dbc +#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0dbd +#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dbe +#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0dbf +#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0dc0 +#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0dc1 +#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0dc2 +#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0dc3 +#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0dc4 +#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0dc5 +#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0dc6 +#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0dc7 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0dc8 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0dc9 +#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dca +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dcb +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dcc +#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dcd +#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dce +#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dcf +#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0dd0 +#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0dd1 +#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0dd2 +#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0dd3 +#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0dd4 +#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0dd5 +#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0dd6 +#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0dd7 +#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0dd8 +#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0dd9 +#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0dda +#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0ddb +#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0ddc +#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0ddd +#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_CTRL2 0x0dde +#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmCM0_CM_MEM_PWR_STATUS2 0x0ddf +#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define mmCM0_CM_3DLUT_MODE 0x0de0 +#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2 +#define mmCM0_CM_3DLUT_INDEX 0x0de1 +#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2 +#define mmCM0_CM_3DLUT_DATA 0x0de2 +#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2 +#define mmCM0_CM_3DLUT_DATA_30BIT 0x0de3 +#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0de4 +#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0de5 +#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0de6 +#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0de7 +#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0de8 +#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define mmCM0_CM_TEST_DEBUG_INDEX 0x0de9 +#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmCM0_CM_TEST_DEBUG_DATA 0x0dea +#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3890 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 +#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 +#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CNTL 0x0e27 +#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CNTL2 0x0e28 +#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 +#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a +#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_HI 0x0e2b +#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON11_PERFMON_LOW 0x0e2c +#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +// base address: 0x5ac +#define mmDPP_TOP1_DPP_CONTROL 0x0e30 +#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31 +#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 +#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 +#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34 +#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35 +#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +// base address: 0x5ac +#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a +#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b +#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c +#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d +#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e +#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f +#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 +#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 +#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 +#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 +#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 +#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44 +#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 +#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 +#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 +#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 +#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +// base address: 0x5ac +#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e4b +#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e4c +#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e4d +#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e4e +#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +// base address: 0x5ac +#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e55 +#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e56 +#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL1_SCL_MODE 0x0e57 +#define mmDSCL1_SCL_MODE_BASE_IDX 2 +#define mmDSCL1_SCL_TAP_CONTROL 0x0e58 +#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL1_DSCL_CONTROL 0x0e59 +#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e5a +#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e5b +#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e5c +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e5d +#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e5e +#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e5f +#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e60 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e61 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e62 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e63 +#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e64 +#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e65 +#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL1_SCL_BLACK_OFFSET 0x0e66 +#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2 +#define mmDSCL1_DSCL_UPDATE 0x0e67 +#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL1_DSCL_AUTOCAL 0x0e68 +#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e69 +#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e6a +#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL1_OTG_H_BLANK 0x0e6b +#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL1_OTG_V_BLANK 0x0e6c +#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL1_RECOUT_START 0x0e6d +#define mmDSCL1_RECOUT_START_BASE_IDX 2 +#define mmDSCL1_RECOUT_SIZE 0x0e6e +#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL1_MPC_SIZE 0x0e6f +#define mmDSCL1_MPC_SIZE_BASE_IDX 2 +#define mmDSCL1_LB_DATA_FORMAT 0x0e70 +#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL1_LB_MEMORY_CTRL 0x0e71 +#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL1_LB_V_COUNTER 0x0e72 +#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e73 +#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e74 +#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL1_OBUF_CONTROL 0x0e75 +#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e76 +#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +// base address: 0x5ac +#define mmCM1_CM_CONTROL 0x0e85 +#define mmCM1_CM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_ICSC_CONTROL 0x0e86 +#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2 +#define mmCM1_CM_ICSC_C11_C12 0x0e87 +#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2 +#define mmCM1_CM_ICSC_C13_C14 0x0e88 +#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2 +#define mmCM1_CM_ICSC_C21_C22 0x0e89 +#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2 +#define mmCM1_CM_ICSC_C23_C24 0x0e8a +#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2 +#define mmCM1_CM_ICSC_C31_C32 0x0e8b +#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2 +#define mmCM1_CM_ICSC_C33_C34 0x0e8c +#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2 +#define mmCM1_CM_ICSC_B_C11_C12 0x0e8d +#define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX 2 +#define mmCM1_CM_ICSC_B_C13_C14 0x0e8e +#define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX 2 +#define mmCM1_CM_ICSC_B_C21_C22 0x0e8f +#define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX 2 +#define mmCM1_CM_ICSC_B_C23_C24 0x0e90 +#define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX 2 +#define mmCM1_CM_ICSC_B_C31_C32 0x0e91 +#define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX 2 +#define mmCM1_CM_ICSC_B_C33_C34 0x0e92 +#define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e93 +#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e94 +#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e95 +#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e96 +#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e97 +#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e98 +#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e99 +#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0e9a +#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0e9b +#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0e9c +#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0e9d +#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0e9e +#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0e9f +#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define mmCM1_CM_BIAS_CR_R 0x0ea0 +#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2 +#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea1 +#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_CONTROL 0x0ea2 +#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_DGAM_LUT_INDEX 0x0ea3 +#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_DGAM_LUT_DATA 0x0ea4 +#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2 +#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ea5 +#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0ea6 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0ea7 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0ea8 +#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0ea9 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eaa +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab +#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0eac +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0ead +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0eae +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0eaf +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0eb0 +#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0eb1 +#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0eb2 +#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0eb3 +#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0eb4 +#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0eb5 +#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0eb6 +#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0eb7 +#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0eb8 +#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0eb9 +#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0eba +#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0ebb +#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0ebc +#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0ebd +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0ebe +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0ebf +#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0ec0 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0ec1 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0ec2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0ec3 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0ec4 +#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0ec5 +#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0ec6 +#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0ec7 +#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0ec8 +#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0ec9 +#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0eca +#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0ecb +#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0ecc +#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0ecd +#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_CONTROL 0x0ece +#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ecf +#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ed0 +#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0ed1 +#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ed2 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ed3 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ed4 +#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0ed5 +#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0ed6 +#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0ed7 +#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0ed8 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0ed9 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0eda +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0edb +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0edc +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0edd +#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0ede +#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0edf +#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0ee0 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0ee1 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0ee2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0ee3 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0ee4 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0ee5 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0ee6 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0ee7 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0ee8 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0ee9 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0eea +#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0eeb +#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0eec +#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0eed +#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0eee +#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0eef +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0ef0 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0ef1 +#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0ef2 +#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0ef3 +#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0ef4 +#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0ef5 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0ef6 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0ef7 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0ef8 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0ef9 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0efa +#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0efb +#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0efc +#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0efd +#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0efe +#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0eff +#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f00 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f01 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f02 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f03 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f04 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f05 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f06 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f07 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f08 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f09 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f0a +#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f0b +#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_HDR_MULT_COEF 0x0f0c +#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_CTRL 0x0f0d +#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_STATUS 0x0f0e +#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCM1_CM_DEALPHA 0x0f10 +#define mmCM1_CM_DEALPHA_BASE_IDX 2 +#define mmCM1_CM_COEF_FORMAT 0x0f11 +#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2 +#define mmCM1_CM_SHAPER_CONTROL 0x0f12 +#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2 +#define mmCM1_CM_SHAPER_OFFSET_R 0x0f13 +#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_OFFSET_G 0x0f14 +#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_OFFSET_B 0x0f15 +#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_SCALE_R 0x0f16 +#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f17 +#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f18 +#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_SHAPER_LUT_DATA 0x0f19 +#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f1a +#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f1b +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f1c +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f1d +#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f1e +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f1f +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f20 +#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f21 +#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f22 +#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f23 +#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f24 +#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f25 +#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f26 +#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f27 +#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f28 +#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f29 +#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f2a +#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f2b +#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f2c +#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f2d +#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f2e +#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f2f +#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f30 +#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f31 +#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f32 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f33 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f34 +#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f35 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f36 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f37 +#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f38 +#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f39 +#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f3a +#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f3b +#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f3c +#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f3d +#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f3e +#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f3f +#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f40 +#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f41 +#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f42 +#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f43 +#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f44 +#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f45 +#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f46 +#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f47 +#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f48 +#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_CTRL2 0x0f49 +#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmCM1_CM_MEM_PWR_STATUS2 0x0f4a +#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define mmCM1_CM_3DLUT_MODE 0x0f4b +#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2 +#define mmCM1_CM_3DLUT_INDEX 0x0f4c +#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2 +#define mmCM1_CM_3DLUT_DATA 0x0f4d +#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2 +#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f4e +#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f4f +#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f50 +#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f51 +#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f52 +#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f53 +#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define mmCM1_CM_TEST_DEBUG_INDEX 0x0f54 +#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmCM1_CM_TEST_DEBUG_DATA 0x0f55 +#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3e3c +#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f +#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 +#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 +#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CNTL 0x0f92 +#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CNTL2 0x0f93 +#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 +#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 +#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_HI 0x0f96 +#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON12_PERFMON_LOW 0x0f97 +#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +// base address: 0xb58 +#define mmDPP_TOP2_DPP_CONTROL 0x0f9b +#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c +#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d +#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e +#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f +#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0 +#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +// base address: 0xb58 +#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 +#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6 +#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 +#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 +#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 +#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 +#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 +#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 +#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa +#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 +#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab +#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 +#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac +#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad +#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae +#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf +#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 +#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 +#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 +#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 +#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +// base address: 0xb58 +#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fb6 +#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fb7 +#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fb8 +#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fb9 +#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +// base address: 0xb58 +#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fc0 +#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fc1 +#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL2_SCL_MODE 0x0fc2 +#define mmDSCL2_SCL_MODE_BASE_IDX 2 +#define mmDSCL2_SCL_TAP_CONTROL 0x0fc3 +#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL2_DSCL_CONTROL 0x0fc4 +#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fc5 +#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fc6 +#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fc7 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fc8 +#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fc9 +#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fca +#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fcb +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fcc +#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fcd +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fce +#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fcf +#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fd0 +#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL2_SCL_BLACK_OFFSET 0x0fd1 +#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2 +#define mmDSCL2_DSCL_UPDATE 0x0fd2 +#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL2_DSCL_AUTOCAL 0x0fd3 +#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fd4 +#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fd5 +#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL2_OTG_H_BLANK 0x0fd6 +#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL2_OTG_V_BLANK 0x0fd7 +#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL2_RECOUT_START 0x0fd8 +#define mmDSCL2_RECOUT_START_BASE_IDX 2 +#define mmDSCL2_RECOUT_SIZE 0x0fd9 +#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL2_MPC_SIZE 0x0fda +#define mmDSCL2_MPC_SIZE_BASE_IDX 2 +#define mmDSCL2_LB_DATA_FORMAT 0x0fdb +#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL2_LB_MEMORY_CTRL 0x0fdc +#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL2_LB_V_COUNTER 0x0fdd +#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fde +#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fdf +#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL2_OBUF_CONTROL 0x0fe0 +#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0fe1 +#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +// base address: 0xb58 +#define mmCM2_CM_CONTROL 0x0ff0 +#define mmCM2_CM_CONTROL_BASE_IDX 2 +#define mmCM2_CM_ICSC_CONTROL 0x0ff1 +#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2 +#define mmCM2_CM_ICSC_C11_C12 0x0ff2 +#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2 +#define mmCM2_CM_ICSC_C13_C14 0x0ff3 +#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2 +#define mmCM2_CM_ICSC_C21_C22 0x0ff4 +#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2 +#define mmCM2_CM_ICSC_C23_C24 0x0ff5 +#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2 +#define mmCM2_CM_ICSC_C31_C32 0x0ff6 +#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2 +#define mmCM2_CM_ICSC_C33_C34 0x0ff7 +#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2 +#define mmCM2_CM_ICSC_B_C11_C12 0x0ff8 +#define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX 2 +#define mmCM2_CM_ICSC_B_C13_C14 0x0ff9 +#define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX 2 +#define mmCM2_CM_ICSC_B_C21_C22 0x0ffa +#define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX 2 +#define mmCM2_CM_ICSC_B_C23_C24 0x0ffb +#define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX 2 +#define mmCM2_CM_ICSC_B_C31_C32 0x0ffc +#define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX 2 +#define mmCM2_CM_ICSC_B_C33_C34 0x0ffd +#define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ffe +#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0fff +#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1000 +#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1001 +#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1002 +#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1003 +#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x1004 +#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x1005 +#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x1006 +#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x1007 +#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x1008 +#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x1009 +#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x100a +#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define mmCM2_CM_BIAS_CR_R 0x100b +#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2 +#define mmCM2_CM_BIAS_Y_G_CB_B 0x100c +#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_CONTROL 0x100d +#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2 +#define mmCM2_CM_DGAM_LUT_INDEX 0x100e +#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM2_CM_DGAM_LUT_DATA 0x100f +#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2 +#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x1010 +#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x1011 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x1012 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x1013 +#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1014 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1015 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1016 +#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x1017 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x1018 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x1019 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x101a +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x101b +#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x101c +#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x101d +#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x101e +#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x101f +#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x1020 +#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x1021 +#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x1022 +#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x1023 +#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x1024 +#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x1025 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x1026 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x1027 +#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1028 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1029 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102a +#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x102b +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x102c +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x102d +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x102e +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x102f +#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x1030 +#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x1031 +#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x1032 +#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x1033 +#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x1034 +#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x1035 +#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x1036 +#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x1037 +#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x1038 +#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_CONTROL 0x1039 +#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x103a +#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_LUT_DATA 0x103b +#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x103c +#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x103d +#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x103e +#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x103f +#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x1040 +#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x1041 +#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x1042 +#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1043 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1044 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1045 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1046 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1047 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1048 +#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1049 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x104a +#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x104b +#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x104c +#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x104d +#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x104e +#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x104f +#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x1050 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x1051 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x1052 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x1053 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x1054 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x1055 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1056 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1057 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1058 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1059 +#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x105a +#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x105b +#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x105c +#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x105d +#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x105e +#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x105f +#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1060 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1061 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1062 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1063 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1064 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1065 +#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1066 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1067 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1068 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1069 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x106a +#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x106b +#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x106c +#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x106d +#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x106e +#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x106f +#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x1070 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x1071 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x1072 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x1073 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x1074 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x1075 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x1076 +#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM2_CM_HDR_MULT_COEF 0x1077 +#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM2_CM_MEM_PWR_CTRL 0x1078 +#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM2_CM_MEM_PWR_STATUS 0x1079 +#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCM2_CM_DEALPHA 0x107b +#define mmCM2_CM_DEALPHA_BASE_IDX 2 +#define mmCM2_CM_COEF_FORMAT 0x107c +#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2 +#define mmCM2_CM_SHAPER_CONTROL 0x107d +#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2 +#define mmCM2_CM_SHAPER_OFFSET_R 0x107e +#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define mmCM2_CM_SHAPER_OFFSET_G 0x107f +#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define mmCM2_CM_SHAPER_OFFSET_B 0x1080 +#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define mmCM2_CM_SHAPER_SCALE_R 0x1081 +#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define mmCM2_CM_SHAPER_SCALE_G_B 0x1082 +#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define mmCM2_CM_SHAPER_LUT_INDEX 0x1083 +#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define mmCM2_CM_SHAPER_LUT_DATA 0x1084 +#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x1085 +#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x1086 +#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x1087 +#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x1088 +#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x1089 +#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x108a +#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x108b +#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x108c +#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x108d +#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x108e +#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x108f +#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x1090 +#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x1091 +#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x1092 +#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x1093 +#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x1094 +#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x1095 +#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x1096 +#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x1097 +#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x1098 +#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x1099 +#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x109a +#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x109b +#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x109c +#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x109d +#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x109e +#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x109f +#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10a0 +#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10a1 +#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10a2 +#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10a3 +#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10a4 +#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10a5 +#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10a6 +#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10a7 +#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10a8 +#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10a9 +#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10aa +#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10ab +#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10ac +#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10ad +#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10ae +#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10af +#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10b0 +#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10b1 +#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10b2 +#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10b3 +#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM2_CM_MEM_PWR_CTRL2 0x10b4 +#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmCM2_CM_MEM_PWR_STATUS2 0x10b5 +#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define mmCM2_CM_3DLUT_MODE 0x10b6 +#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2 +#define mmCM2_CM_3DLUT_INDEX 0x10b7 +#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2 +#define mmCM2_CM_3DLUT_DATA 0x10b8 +#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2 +#define mmCM2_CM_3DLUT_DATA_30BIT 0x10b9 +#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ba +#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10bb +#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10bc +#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10bd +#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10be +#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define mmCM2_CM_TEST_DEBUG_INDEX 0x10bf +#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmCM2_CM_TEST_DEBUG_DATA 0x10c0 +#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x43e8 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa +#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb +#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x10fc +#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CNTL 0x10fd +#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CNTL2 0x10fe +#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff +#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 +#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_HI 0x1101 +#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON13_PERFMON_LOW 0x1102 +#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +// base address: 0x1104 +#define mmDPP_TOP3_DPP_CONTROL 0x1106 +#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2 +#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107 +#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 +#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 +#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 +#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 +#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 +#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a +#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 +#define mmDPP_TOP3_HOST_READ_CONTROL 0x110b +#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +// base address: 0x1104 +#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 +#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111 +#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 +#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 +#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 +#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 +#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 +#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 +#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 +#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 +#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 +#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 +#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 +#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 +#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 +#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a +#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b +#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 +#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c +#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 +#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e +#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +// base address: 0x1104 +#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1121 +#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 +#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1122 +#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 +#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1123 +#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 +#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1124 +#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +// base address: 0x1104 +#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x112b +#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x112c +#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define mmDSCL3_SCL_MODE 0x112d +#define mmDSCL3_SCL_MODE_BASE_IDX 2 +#define mmDSCL3_SCL_TAP_CONTROL 0x112e +#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 +#define mmDSCL3_DSCL_CONTROL 0x112f +#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2 +#define mmDSCL3_DSCL_2TAP_CONTROL 0x1130 +#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1131 +#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1132 +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1133 +#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1134 +#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1135 +#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1136 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1137 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1138 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1139 +#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x113a +#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x113b +#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define mmDSCL3_SCL_BLACK_OFFSET 0x113c +#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2 +#define mmDSCL3_DSCL_UPDATE 0x113d +#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2 +#define mmDSCL3_DSCL_AUTOCAL 0x113e +#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2 +#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x113f +#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1140 +#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define mmDSCL3_OTG_H_BLANK 0x1141 +#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2 +#define mmDSCL3_OTG_V_BLANK 0x1142 +#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2 +#define mmDSCL3_RECOUT_START 0x1143 +#define mmDSCL3_RECOUT_START_BASE_IDX 2 +#define mmDSCL3_RECOUT_SIZE 0x1144 +#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2 +#define mmDSCL3_MPC_SIZE 0x1145 +#define mmDSCL3_MPC_SIZE_BASE_IDX 2 +#define mmDSCL3_LB_DATA_FORMAT 0x1146 +#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2 +#define mmDSCL3_LB_MEMORY_CTRL 0x1147 +#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 +#define mmDSCL3_LB_V_COUNTER 0x1148 +#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2 +#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1149 +#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x114a +#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDSCL3_OBUF_CONTROL 0x114b +#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2 +#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x114c +#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +// base address: 0x1104 +#define mmCM3_CM_CONTROL 0x115b +#define mmCM3_CM_CONTROL_BASE_IDX 2 +#define mmCM3_CM_ICSC_CONTROL 0x115c +#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2 +#define mmCM3_CM_ICSC_C11_C12 0x115d +#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2 +#define mmCM3_CM_ICSC_C13_C14 0x115e +#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2 +#define mmCM3_CM_ICSC_C21_C22 0x115f +#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2 +#define mmCM3_CM_ICSC_C23_C24 0x1160 +#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2 +#define mmCM3_CM_ICSC_C31_C32 0x1161 +#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2 +#define mmCM3_CM_ICSC_C33_C34 0x1162 +#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2 +#define mmCM3_CM_ICSC_B_C11_C12 0x1163 +#define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX 2 +#define mmCM3_CM_ICSC_B_C13_C14 0x1164 +#define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX 2 +#define mmCM3_CM_ICSC_B_C21_C22 0x1165 +#define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX 2 +#define mmCM3_CM_ICSC_B_C23_C24 0x1166 +#define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX 2 +#define mmCM3_CM_ICSC_B_C31_C32 0x1167 +#define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX 2 +#define mmCM3_CM_ICSC_B_C33_C34 0x1168 +#define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1169 +#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x116a +#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x116b +#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x116c +#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x116d +#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x116e +#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x116f +#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1170 +#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1171 +#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1172 +#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1173 +#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x1174 +#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 +#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x1175 +#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 +#define mmCM3_CM_BIAS_CR_R 0x1176 +#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2 +#define mmCM3_CM_BIAS_Y_G_CB_B 0x1177 +#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_CONTROL 0x1178 +#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2 +#define mmCM3_CM_DGAM_LUT_INDEX 0x1179 +#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM3_CM_DGAM_LUT_DATA 0x117a +#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2 +#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x117b +#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x117c +#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x117d +#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x117e +#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x117f +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1180 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1181 +#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x1182 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x1183 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x1184 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x1185 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1186 +#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1187 +#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1188 +#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1189 +#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x118a +#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x118b +#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x118c +#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x118d +#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x118e +#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x118f +#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x1190 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x1191 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x1192 +#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1193 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1194 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x1195 +#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1196 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1197 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1198 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1199 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x119a +#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x119b +#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x119c +#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x119d +#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x119e +#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x119f +#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x11a0 +#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x11a1 +#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x11a2 +#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x11a3 +#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_CONTROL 0x11a4 +#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11a5 +#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11a6 +#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x11a7 +#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11a8 +#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11a9 +#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11aa +#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x11ab +#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x11ac +#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x11ad +#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11ae +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11af +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11b0 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11b1 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11b2 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11b3 +#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11b4 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11b5 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11b6 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11b7 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11b8 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11b9 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11ba +#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11bb +#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11bc +#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11bd +#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11be +#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11bf +#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11c0 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11c1 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11c2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11c3 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11c4 +#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11c5 +#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11c6 +#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11c7 +#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x11c8 +#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x11c9 +#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x11ca +#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11cb +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11cc +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11cd +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11ce +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11cf +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11d0 +#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x11d1 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x11d2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x11d3 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x11d4 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x11d5 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x11d6 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x11d7 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x11d8 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x11d9 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x11da +#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x11db +#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x11dc +#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x11dd +#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x11de +#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x11df +#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x11e0 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x11e1 +#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM3_CM_HDR_MULT_COEF 0x11e2 +#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2 +#define mmCM3_CM_MEM_PWR_CTRL 0x11e3 +#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmCM3_CM_MEM_PWR_STATUS 0x11e4 +#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define mmCM3_CM_DEALPHA 0x11e6 +#define mmCM3_CM_DEALPHA_BASE_IDX 2 +#define mmCM3_CM_COEF_FORMAT 0x11e7 +#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2 +#define mmCM3_CM_SHAPER_CONTROL 0x11e8 +#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2 +#define mmCM3_CM_SHAPER_OFFSET_R 0x11e9 +#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2 +#define mmCM3_CM_SHAPER_OFFSET_G 0x11ea +#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2 +#define mmCM3_CM_SHAPER_OFFSET_B 0x11eb +#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2 +#define mmCM3_CM_SHAPER_SCALE_R 0x11ec +#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2 +#define mmCM3_CM_SHAPER_SCALE_G_B 0x11ed +#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2 +#define mmCM3_CM_SHAPER_LUT_INDEX 0x11ee +#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2 +#define mmCM3_CM_SHAPER_LUT_DATA 0x11ef +#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2 +#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x11f0 +#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x11f1 +#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x11f2 +#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x11f3 +#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x11f4 +#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x11f5 +#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x11f6 +#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x11f7 +#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x11f8 +#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x11f9 +#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x11fa +#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x11fb +#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x11fc +#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x11fd +#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x11fe +#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x11ff +#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1200 +#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1201 +#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1202 +#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1203 +#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1204 +#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1205 +#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1206 +#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1207 +#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1208 +#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1209 +#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x120a +#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x120b +#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x120c +#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x120d +#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x120e +#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x120f +#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1210 +#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1211 +#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1212 +#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1213 +#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1214 +#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1215 +#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1216 +#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1217 +#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1218 +#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1219 +#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x121a +#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x121b +#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x121c +#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x121d +#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2 +#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x121e +#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2 +#define mmCM3_CM_MEM_PWR_CTRL2 0x121f +#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmCM3_CM_MEM_PWR_STATUS2 0x1220 +#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2 +#define mmCM3_CM_3DLUT_MODE 0x1221 +#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2 +#define mmCM3_CM_3DLUT_INDEX 0x1222 +#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2 +#define mmCM3_CM_3DLUT_DATA 0x1223 +#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2 +#define mmCM3_CM_3DLUT_DATA_30BIT 0x1224 +#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2 +#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1225 +#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2 +#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1226 +#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2 +#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1227 +#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2 +#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1228 +#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2 +#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1229 +#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2 +#define mmCM3_CM_TEST_DEBUG_INDEX 0x122a +#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmCM3_CM_TEST_DEBUG_DATA 0x122b +#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x4994 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 +#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x1267 +#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CNTL 0x1268 +#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CNTL2 0x1269 +#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a +#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b +#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_HI 0x126c +#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON14_PERFMON_LOW 0x126d +#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +// base address: 0x0 +#define mmMPCC0_MPCC_TOP_SEL 0x1271 +#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC0_MPCC_BOT_SEL 0x1272 +#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC0_MPCC_OPP_ID 0x1273 +#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC0_MPCC_CONTROL 0x1274 +#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC0_MPCC_SM_CONTROL 0x1275 +#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1276 +#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC0_MPCC_TOP_GAIN 0x1277 +#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 2 +#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x1278 +#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 +#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x1279 +#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 +#define mmMPCC0_MPCC_BG_R_CR 0x127a +#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC0_MPCC_BG_G_Y 0x127b +#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC0_MPCC_BG_B_CB 0x127c +#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x127d +#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 2 +#define mmMPCC0_MPCC_STALL_STATUS 0x127e +#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC0_MPCC_STATUS 0x127f +#define mmMPCC0_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +// base address: 0x6c +#define mmMPCC1_MPCC_TOP_SEL 0x128c +#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC1_MPCC_BOT_SEL 0x128d +#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC1_MPCC_OPP_ID 0x128e +#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC1_MPCC_CONTROL 0x128f +#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC1_MPCC_SM_CONTROL 0x1290 +#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1291 +#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC1_MPCC_TOP_GAIN 0x1292 +#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 2 +#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x1293 +#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 +#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x1294 +#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 +#define mmMPCC1_MPCC_BG_R_CR 0x1295 +#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC1_MPCC_BG_G_Y 0x1296 +#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC1_MPCC_BG_B_CB 0x1297 +#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x1298 +#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 2 +#define mmMPCC1_MPCC_STALL_STATUS 0x1299 +#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC1_MPCC_STATUS 0x129a +#define mmMPCC1_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +// base address: 0xd8 +#define mmMPCC2_MPCC_TOP_SEL 0x12a7 +#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC2_MPCC_BOT_SEL 0x12a8 +#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC2_MPCC_OPP_ID 0x12a9 +#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC2_MPCC_CONTROL 0x12aa +#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC2_MPCC_SM_CONTROL 0x12ab +#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x12ac +#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC2_MPCC_TOP_GAIN 0x12ad +#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 2 +#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x12ae +#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 +#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x12af +#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 +#define mmMPCC2_MPCC_BG_R_CR 0x12b0 +#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC2_MPCC_BG_G_Y 0x12b1 +#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC2_MPCC_BG_B_CB 0x12b2 +#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x12b3 +#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 2 +#define mmMPCC2_MPCC_STALL_STATUS 0x12b4 +#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC2_MPCC_STATUS 0x12b5 +#define mmMPCC2_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +// base address: 0x144 +#define mmMPCC3_MPCC_TOP_SEL 0x12c2 +#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC3_MPCC_BOT_SEL 0x12c3 +#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC3_MPCC_OPP_ID 0x12c4 +#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC3_MPCC_CONTROL 0x12c5 +#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC3_MPCC_SM_CONTROL 0x12c6 +#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x12c7 +#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC3_MPCC_TOP_GAIN 0x12c8 +#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 2 +#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x12c9 +#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 +#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x12ca +#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 +#define mmMPCC3_MPCC_BG_R_CR 0x12cb +#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC3_MPCC_BG_G_Y 0x12cc +#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC3_MPCC_BG_B_CB 0x12cd +#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x12ce +#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 2 +#define mmMPCC3_MPCC_STALL_STATUS 0x12cf +#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC3_MPCC_STATUS 0x12d0 +#define mmMPCC3_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc4_dispdec +// base address: 0x1b0 +#define mmMPCC4_MPCC_TOP_SEL 0x12dd +#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC4_MPCC_BOT_SEL 0x12de +#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC4_MPCC_OPP_ID 0x12df +#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC4_MPCC_CONTROL 0x12e0 +#define mmMPCC4_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC4_MPCC_SM_CONTROL 0x12e1 +#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x12e2 +#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC4_MPCC_TOP_GAIN 0x12e3 +#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 2 +#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x12e4 +#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 +#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x12e5 +#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 +#define mmMPCC4_MPCC_BG_R_CR 0x12e6 +#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC4_MPCC_BG_G_Y 0x12e7 +#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC4_MPCC_BG_B_CB 0x12e8 +#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x12e9 +#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 2 +#define mmMPCC4_MPCC_STALL_STATUS 0x12ea +#define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC4_MPCC_STATUS 0x12eb +#define mmMPCC4_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc5_dispdec +// base address: 0x21c +#define mmMPCC5_MPCC_TOP_SEL 0x12f8 +#define mmMPCC5_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC5_MPCC_BOT_SEL 0x12f9 +#define mmMPCC5_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC5_MPCC_OPP_ID 0x12fa +#define mmMPCC5_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC5_MPCC_CONTROL 0x12fb +#define mmMPCC5_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC5_MPCC_SM_CONTROL 0x12fc +#define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC5_MPCC_UPDATE_LOCK_SEL 0x12fd +#define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC5_MPCC_TOP_GAIN 0x12fe +#define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX 2 +#define mmMPCC5_MPCC_BOT_GAIN_INSIDE 0x12ff +#define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 +#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE 0x1300 +#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 +#define mmMPCC5_MPCC_BG_R_CR 0x1301 +#define mmMPCC5_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC5_MPCC_BG_G_Y 0x1302 +#define mmMPCC5_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC5_MPCC_BG_B_CB 0x1303 +#define mmMPCC5_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC5_MPCC_MEM_PWR_CTRL 0x1304 +#define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX 2 +#define mmMPCC5_MPCC_STALL_STATUS 0x1305 +#define mmMPCC5_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC5_MPCC_STATUS 0x1306 +#define mmMPCC5_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc6_dispdec +// base address: 0x288 +#define mmMPCC6_MPCC_TOP_SEL 0x1313 +#define mmMPCC6_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC6_MPCC_BOT_SEL 0x1314 +#define mmMPCC6_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC6_MPCC_OPP_ID 0x1315 +#define mmMPCC6_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC6_MPCC_CONTROL 0x1316 +#define mmMPCC6_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC6_MPCC_SM_CONTROL 0x1317 +#define mmMPCC6_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC6_MPCC_UPDATE_LOCK_SEL 0x1318 +#define mmMPCC6_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC6_MPCC_TOP_GAIN 0x1319 +#define mmMPCC6_MPCC_TOP_GAIN_BASE_IDX 2 +#define mmMPCC6_MPCC_BOT_GAIN_INSIDE 0x131a +#define mmMPCC6_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 +#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE 0x131b +#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 +#define mmMPCC6_MPCC_BG_R_CR 0x131c +#define mmMPCC6_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC6_MPCC_BG_G_Y 0x131d +#define mmMPCC6_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC6_MPCC_BG_B_CB 0x131e +#define mmMPCC6_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC6_MPCC_MEM_PWR_CTRL 0x131f +#define mmMPCC6_MPCC_MEM_PWR_CTRL_BASE_IDX 2 +#define mmMPCC6_MPCC_STALL_STATUS 0x1320 +#define mmMPCC6_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC6_MPCC_STATUS 0x1321 +#define mmMPCC6_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc7_dispdec +// base address: 0x2f4 +#define mmMPCC7_MPCC_TOP_SEL 0x132e +#define mmMPCC7_MPCC_TOP_SEL_BASE_IDX 2 +#define mmMPCC7_MPCC_BOT_SEL 0x132f +#define mmMPCC7_MPCC_BOT_SEL_BASE_IDX 2 +#define mmMPCC7_MPCC_OPP_ID 0x1330 +#define mmMPCC7_MPCC_OPP_ID_BASE_IDX 2 +#define mmMPCC7_MPCC_CONTROL 0x1331 +#define mmMPCC7_MPCC_CONTROL_BASE_IDX 2 +#define mmMPCC7_MPCC_SM_CONTROL 0x1332 +#define mmMPCC7_MPCC_SM_CONTROL_BASE_IDX 2 +#define mmMPCC7_MPCC_UPDATE_LOCK_SEL 0x1333 +#define mmMPCC7_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 +#define mmMPCC7_MPCC_TOP_GAIN 0x1334 +#define mmMPCC7_MPCC_TOP_GAIN_BASE_IDX 2 +#define mmMPCC7_MPCC_BOT_GAIN_INSIDE 0x1335 +#define mmMPCC7_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2 +#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE 0x1336 +#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2 +#define mmMPCC7_MPCC_BG_R_CR 0x1337 +#define mmMPCC7_MPCC_BG_R_CR_BASE_IDX 2 +#define mmMPCC7_MPCC_BG_G_Y 0x1338 +#define mmMPCC7_MPCC_BG_G_Y_BASE_IDX 2 +#define mmMPCC7_MPCC_BG_B_CB 0x1339 +#define mmMPCC7_MPCC_BG_B_CB_BASE_IDX 2 +#define mmMPCC7_MPCC_MEM_PWR_CTRL 0x133a +#define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX 2 +#define mmMPCC7_MPCC_STALL_STATUS 0x133b +#define mmMPCC7_MPCC_STALL_STATUS_BASE_IDX 2 +#define mmMPCC7_MPCC_STATUS 0x133c +#define mmMPCC7_MPCC_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +// base address: 0x0 +#define mmMPC_CLOCK_CONTROL 0x1349 +#define mmMPC_CLOCK_CONTROL_BASE_IDX 2 +#define mmMPC_SOFT_RESET 0x134a +#define mmMPC_SOFT_RESET_BASE_IDX 2 +#define mmMPC_CRC_CTRL 0x134b +#define mmMPC_CRC_CTRL_BASE_IDX 2 +#define mmMPC_CRC_SEL_CONTROL 0x134c +#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2 +#define mmMPC_CRC_RESULT_AR 0x134d +#define mmMPC_CRC_RESULT_AR_BASE_IDX 2 +#define mmMPC_CRC_RESULT_GB 0x134e +#define mmMPC_CRC_RESULT_GB_BASE_IDX 2 +#define mmMPC_CRC_RESULT_C 0x134f +#define mmMPC_CRC_RESULT_C_BASE_IDX 2 +#define mmMPC_PERFMON_EVENT_CTRL 0x1352 +#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2 +#define mmMPC_BYPASS_BG_AR 0x1353 +#define mmMPC_BYPASS_BG_AR_BASE_IDX 2 +#define mmMPC_BYPASS_BG_GB 0x1354 +#define mmMPC_BYPASS_BG_GB_BASE_IDX 2 +#define mmMPC_STALL_GRACE_WINDOW 0x1355 +#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2 +#define mmMPC_HOST_READ_CONTROL 0x1356 +#define mmMPC_HOST_READ_CONTROL_BASE_IDX 2 +#define mmMPC_PENDING_TAKEN_STATUS_REG1 0x1357 +#define mmMPC_PENDING_TAKEN_STATUS_REG1_BASE_IDX 2 +#define mmMPC_PENDING_TAKEN_STATUS_REG3 0x1359 +#define mmMPC_PENDING_TAKEN_STATUS_REG3_BASE_IDX 2 +#define mmMPC_UPDATE_ACK_REG5 0x135b +#define mmMPC_UPDATE_ACK_REG5_BASE_IDX 2 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x135d +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmADR_CFG_VUPDATE_LOCK_SET0 0x135e +#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmADR_VUPDATE_LOCK_SET0 0x135f +#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmCFG_VUPDATE_LOCK_SET0 0x1360 +#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmCUR_VUPDATE_LOCK_SET0 0x1361 +#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 2 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x1362 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmADR_CFG_VUPDATE_LOCK_SET1 0x1363 +#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmADR_VUPDATE_LOCK_SET1 0x1364 +#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmCFG_VUPDATE_LOCK_SET1 0x1365 +#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmCUR_VUPDATE_LOCK_SET1 0x1366 +#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 2 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x1367 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1368 +#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmADR_VUPDATE_LOCK_SET2 0x1369 +#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmCFG_VUPDATE_LOCK_SET2 0x136a +#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmCUR_VUPDATE_LOCK_SET2 0x136b +#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 2 +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x136c +#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 2 +#define mmADR_CFG_VUPDATE_LOCK_SET3 0x136d +#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2 +#define mmADR_VUPDATE_LOCK_SET3 0x136e +#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2 +#define mmCFG_VUPDATE_LOCK_SET3 0x136f +#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 2 +#define mmCUR_VUPDATE_LOCK_SET3 0x1370 +#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 2 +#define mmMPC_OUT0_MUX 0x1385 +#define mmMPC_OUT0_MUX_BASE_IDX 2 +#define mmMPC_OUT0_DENORM_CONTROL 0x1386 +#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 2 +#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x1387 +#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 2 +#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x1388 +#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 2 +#define mmMPC_OUT1_MUX 0x1389 +#define mmMPC_OUT1_MUX_BASE_IDX 2 +#define mmMPC_OUT1_DENORM_CONTROL 0x138a +#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 2 +#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x138b +#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 2 +#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x138c +#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 2 +#define mmMPC_OUT2_MUX 0x138d +#define mmMPC_OUT2_MUX_BASE_IDX 2 +#define mmMPC_OUT2_DENORM_CONTROL 0x138e +#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 2 +#define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x138f +#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 2 +#define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x1390 +#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 2 +#define mmMPC_OUT3_MUX 0x1391 +#define mmMPC_OUT3_MUX_BASE_IDX 2 +#define mmMPC_OUT3_DENORM_CONTROL 0x1392 +#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 2 +#define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x1393 +#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 2 +#define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x1394 +#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +// base address: 0x0 +#define mmMPCC_OGAM0_MPCC_OGAM_MODE 0x13ae +#define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x13af +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x13b0 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL 0x13b1 +#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x13b2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x13b3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x13b4 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13b5 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13b6 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13b7 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x13b8 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x13b9 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x13ba +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x13bb +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x13bc +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x13bd +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x13be +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x13bf +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x13c0 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x13c1 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x13c2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x13c3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x13c4 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x13c5 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x13c6 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x13c7 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x13c8 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x13c9 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x13ca +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x13cb +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x13cc +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x13cd +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x13ce +#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x13cf +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x13d0 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x13d1 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x13d2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x13d3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x13d4 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x13d5 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x13d6 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x13d7 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x13d8 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x13d9 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x13da +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x13db +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x13dc +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x13dd +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x13de +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x13df +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x13e0 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x13e1 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x13e2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x13e3 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x13e4 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x13e5 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x13e6 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x13e7 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x13e8 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x13e9 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x13ea +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x13eb +#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +// base address: 0x104 +#define mmMPCC_OGAM1_MPCC_OGAM_MODE 0x13ef +#define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x13f0 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x13f1 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL 0x13f2 +#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x13f3 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x13f4 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x13f5 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13f6 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13f7 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13f8 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x13f9 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x13fa +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x13fb +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x13fc +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x13fd +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x13fe +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x13ff +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x1400 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x1401 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x1402 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x1403 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x1404 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x1405 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x1406 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x1407 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x1408 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x1409 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x140a +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x140b +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x140c +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x140d +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x140e +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x140f +#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x1410 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x1411 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x1412 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1413 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1414 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1415 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x1416 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x1417 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x1418 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x1419 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x141a +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x141b +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x141c +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x141d +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x141e +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x141f +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x1420 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x1421 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x1422 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x1423 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x1424 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x1425 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x1426 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x1427 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x1428 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x1429 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x142a +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x142b +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x142c +#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +// base address: 0x208 +#define mmMPCC_OGAM2_MPCC_OGAM_MODE 0x1430 +#define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x1431 +#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x1432 +#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL 0x1433 +#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x1434 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x1435 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x1436 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1437 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1438 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x1439 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x143a +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x143b +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x143c +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x143d +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x143e +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x143f +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x1440 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x1441 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x1442 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x1443 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x1444 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x1445 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x1446 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x1447 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x1448 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x1449 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x144a +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x144b +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x144c +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x144d +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x144e +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x144f +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x1450 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x1451 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x1452 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x1453 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1454 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1455 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1456 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x1457 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x1458 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x1459 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x145a +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x145b +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x145c +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x145d +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x145e +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x145f +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x1460 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x1461 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x1462 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x1463 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x1464 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x1465 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x1466 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x1467 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x1468 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x1469 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x146a +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x146b +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x146c +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x146d +#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +// base address: 0x30c +#define mmMPCC_OGAM3_MPCC_OGAM_MODE 0x1471 +#define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x1472 +#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x1473 +#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL 0x1474 +#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x1475 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x1476 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x1477 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1478 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1479 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x147a +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x147b +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x147c +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x147d +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x147e +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x147f +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x1480 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x1481 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x1482 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x1483 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x1484 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x1485 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x1486 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x1487 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x1488 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x1489 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x148a +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x148b +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x148c +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x148d +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x148e +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x148f +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x1490 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x1491 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x1492 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x1493 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x1494 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1495 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1496 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1497 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x1498 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x1499 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x149a +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x149b +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x149c +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x149d +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x149e +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x149f +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x14a0 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x14a1 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x14a2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x14a3 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x14a4 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x14a5 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x14a6 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x14a7 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x14a8 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x14a9 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x14aa +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x14ab +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x14ac +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x14ad +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x14ae +#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec +// base address: 0x410 +#define mmMPCC_OGAM4_MPCC_OGAM_MODE 0x14b2 +#define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x14b3 +#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x14b4 +#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL 0x14b5 +#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x14b6 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x14b7 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x14b8 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14b9 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14ba +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14bb +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x14bc +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x14bd +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x14be +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x14bf +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x14c0 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x14c1 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x14c2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x14c3 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x14c4 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x14c5 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x14c6 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x14c7 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x14c8 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x14c9 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x14ca +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x14cb +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x14cc +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x14cd +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x14ce +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x14cf +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x14d0 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x14d1 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x14d2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x14d3 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x14d4 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x14d5 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x14d6 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x14d7 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x14d8 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x14d9 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x14da +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x14db +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x14dc +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x14dd +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x14de +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x14df +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x14e0 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x14e1 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x14e2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x14e3 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x14e4 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x14e5 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x14e6 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x14e7 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x14e8 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x14e9 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x14ea +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x14eb +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x14ec +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x14ed +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x14ee +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x14ef +#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec +// base address: 0x514 +#define mmMPCC_OGAM5_MPCC_OGAM_MODE 0x14f3 +#define mmMPCC_OGAM5_MPCC_OGAM_MODE_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX 0x14f4 +#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA 0x14f5 +#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL 0x14f6 +#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B 0x14f7 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G 0x14f8 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R 0x14f9 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14fa +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14fb +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14fc +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B 0x14fd +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B 0x14fe +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G 0x14ff +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G 0x1500 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R 0x1501 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R 0x1502 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 0x1503 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 0x1504 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 0x1505 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 0x1506 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 0x1507 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 0x1508 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 0x1509 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 0x150a +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 0x150b +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 0x150c +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 0x150d +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 0x150e +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 0x150f +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 0x1510 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 0x1511 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 0x1512 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 0x1513 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B 0x1514 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G 0x1515 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R 0x1516 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1517 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1518 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1519 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B 0x151a +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B 0x151b +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G 0x151c +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G 0x151d +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R 0x151e +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R 0x151f +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 0x1520 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 0x1521 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 0x1522 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 0x1523 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 0x1524 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 0x1525 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 0x1526 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 0x1527 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 0x1528 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 0x1529 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 0x152a +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 0x152b +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 0x152c +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 0x152d +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 0x152e +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 0x152f +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 0x1530 +#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec +// base address: 0x618 +#define mmMPCC_OGAM6_MPCC_OGAM_MODE 0x1534 +#define mmMPCC_OGAM6_MPCC_OGAM_MODE_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX 0x1535 +#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA 0x1536 +#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL 0x1537 +#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B 0x1538 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G 0x1539 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R 0x153a +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x153b +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x153c +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x153d +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B 0x153e +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B 0x153f +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G 0x1540 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G 0x1541 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R 0x1542 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R 0x1543 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1 0x1544 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3 0x1545 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5 0x1546 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7 0x1547 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9 0x1548 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11 0x1549 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13 0x154a +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15 0x154b +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17 0x154c +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19 0x154d +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21 0x154e +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23 0x154f +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25 0x1550 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27 0x1551 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29 0x1552 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31 0x1553 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33 0x1554 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B 0x1555 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G 0x1556 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R 0x1557 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1558 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1559 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x155a +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B 0x155b +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B 0x155c +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G 0x155d +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G 0x155e +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R 0x155f +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R 0x1560 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1 0x1561 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3 0x1562 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5 0x1563 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7 0x1564 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9 0x1565 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11 0x1566 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13 0x1567 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15 0x1568 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17 0x1569 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19 0x156a +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21 0x156b +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23 0x156c +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25 0x156d +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27 0x156e +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29 0x156f +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31 0x1570 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33 0x1571 +#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec +// base address: 0x71c +#define mmMPCC_OGAM7_MPCC_OGAM_MODE 0x1575 +#define mmMPCC_OGAM7_MPCC_OGAM_MODE_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX 0x1576 +#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA 0x1577 +#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL 0x1578 +#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B 0x1579 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G 0x157a +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R 0x157b +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x157c +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x157d +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x157e +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B 0x157f +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B 0x1580 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G 0x1581 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G 0x1582 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R 0x1583 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R 0x1584 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1 0x1585 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3 0x1586 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5 0x1587 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7 0x1588 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9 0x1589 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11 0x158a +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13 0x158b +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15 0x158c +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17 0x158d +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19 0x158e +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21 0x158f +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23 0x1590 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25 0x1591 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27 0x1592 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29 0x1593 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31 0x1594 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33 0x1595 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B 0x1596 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G 0x1597 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R 0x1598 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1599 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x159a +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x159b +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B 0x159c +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B 0x159d +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G 0x159e +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G 0x159f +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R 0x15a0 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R 0x15a1 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1 0x15a2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3 0x15a3 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5 0x15a4 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7 0x15a5 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9 0x15a6 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11 0x15a7 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13 0x15a8 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15 0x15a9 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17 0x15aa +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19 0x15ab +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21 0x15ac +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23 0x15ad +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25 0x15ae +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27 0x15af +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29 0x15b0 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31 0x15b1 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33 0x15b2 +#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +// base address: 0x0 +#define mmMPC_OUT_CSC_COEF_FORMAT 0x15b6 +#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 2 +#define mmMPC_OUT0_CSC_MODE 0x15b7 +#define mmMPC_OUT0_CSC_MODE_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C11_C12_A 0x15b8 +#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C13_C14_A 0x15b9 +#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C21_C22_A 0x15ba +#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C23_C24_A 0x15bb +#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C31_C32_A 0x15bc +#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C33_C34_A 0x15bd +#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C11_C12_B 0x15be +#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C13_C14_B 0x15bf +#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C21_C22_B 0x15c0 +#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C23_C24_B 0x15c1 +#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C31_C32_B 0x15c2 +#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 2 +#define mmMPC_OUT0_CSC_C33_C34_B 0x15c3 +#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 2 +#define mmMPC_OUT1_CSC_MODE 0x15c4 +#define mmMPC_OUT1_CSC_MODE_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C11_C12_A 0x15c5 +#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C13_C14_A 0x15c6 +#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C21_C22_A 0x15c7 +#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C23_C24_A 0x15c8 +#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C31_C32_A 0x15c9 +#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C33_C34_A 0x15ca +#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C11_C12_B 0x15cb +#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C13_C14_B 0x15cc +#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C21_C22_B 0x15cd +#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C23_C24_B 0x15ce +#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C31_C32_B 0x15cf +#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 2 +#define mmMPC_OUT1_CSC_C33_C34_B 0x15d0 +#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 2 +#define mmMPC_OUT2_CSC_MODE 0x15d1 +#define mmMPC_OUT2_CSC_MODE_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C11_C12_A 0x15d2 +#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C13_C14_A 0x15d3 +#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C21_C22_A 0x15d4 +#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C23_C24_A 0x15d5 +#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C31_C32_A 0x15d6 +#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C33_C34_A 0x15d7 +#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C11_C12_B 0x15d8 +#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C13_C14_B 0x15d9 +#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C21_C22_B 0x15da +#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C23_C24_B 0x15db +#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C31_C32_B 0x15dc +#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 2 +#define mmMPC_OUT2_CSC_C33_C34_B 0x15dd +#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 2 +#define mmMPC_OUT3_CSC_MODE 0x15de +#define mmMPC_OUT3_CSC_MODE_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C11_C12_A 0x15df +#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C13_C14_A 0x15e0 +#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C21_C22_A 0x15e1 +#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C23_C24_A 0x15e2 +#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C31_C32_A 0x15e3 +#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C33_C34_A 0x15e4 +#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C11_C12_B 0x15e5 +#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C13_C14_B 0x15e6 +#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C21_C22_B 0x15e7 +#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C23_C24_B 0x15e8 +#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C31_C32_B 0x15e9 +#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 2 +#define mmMPC_OUT3_CSC_C33_C34_B 0x15ea +#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +// base address: 0x5964 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x1659 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x165a +#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x165b +#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_CNTL 0x165c +#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_CNTL2 0x165d +#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x165e +#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x165f +#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_HI 0x1660 +#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON15_PERFMON_LOW 0x1661 +#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_abm0_dispdec +// base address: 0x0 +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0 +#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2 +#define mmBL1_PWM_USER_LEVEL 0x17b1 +#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2 +#define mmBL1_PWM_TARGET_ABM_LEVEL 0x17b2 +#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2 +#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x17b3 +#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2 +#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x17b4 +#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5 +#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2 +#define mmBL1_PWM_ABM_CNTL 0x17b6 +#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7 +#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2 +#define mmBL1_PWM_GRP2_REG_LOCK 0x17b8 +#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2 +#define mmDC_ABM1_CNTL 0x17b9 +#define mmDC_ABM1_CNTL_BASE_IDX 2 +#define mmDC_ABM1_IPCSC_COEFF_SEL 0x17ba +#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb +#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc +#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd +#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x17be +#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2 +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf +#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2 +#define mmDC_ABM1_ACE_THRES_12 0x17c0 +#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2 +#define mmDC_ABM1_ACE_THRES_34 0x17c1 +#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2 +#define mmDC_ABM1_ACE_CNTL_MISC 0x17c2 +#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4 +#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2 +#define mmDC_ABM1_HG_MISC_CTRL 0x17c5 +#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2 +#define mmDC_ABM1_LS_SUM_OF_LUMA 0x17c6 +#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2 +#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x17c7 +#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8 +#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2 +#define mmDC_ABM1_LS_PIXEL_COUNT 0x17c9 +#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2 +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca +#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2 +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb +#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2 +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc +#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2 +#define mmDC_ABM1_HG_SAMPLE_RATE 0x17cd +#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2 +#define mmDC_ABM1_LS_SAMPLE_RATE 0x17ce +#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf +#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0 +#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1 +#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2 +#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3 +#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_1 0x17d4 +#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_2 0x17d5 +#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_3 0x17d6 +#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_4 0x17d7 +#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_5 0x17d8 +#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_6 0x17d9 +#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_7 0x17da +#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_8 0x17db +#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_9 0x17dc +#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_10 0x17dd +#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_11 0x17de +#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_12 0x17df +#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_13 0x17e0 +#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_14 0x17e1 +#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_15 0x17e2 +#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_16 0x17e3 +#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_17 0x17e4 +#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_18 0x17e5 +#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_19 0x17e6 +#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_20 0x17e7 +#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_21 0x17e8 +#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_22 0x17e9 +#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_23 0x17ea +#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2 +#define mmDC_ABM1_HG_RESULT_24 0x17eb +#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2 +#define mmDC_ABM1_BL_MASTER_LOCK 0x17ec +#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt0_dispdec +// base address: 0x0 +#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c +#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d +#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e +#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f +#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_CONTROL 0x1840 +#define mmFMT0_FMT_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 +#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 +#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 +#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 +#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT0_FMT_CLAMP_CNTL 0x1845 +#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 +#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 +#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define mmFMT0_FMT_422_CONTROL 0x1849 +#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg0_dispdec +// base address: 0x0 +#define mmDPG0_DPG_CONTROL 0x1854 +#define mmDPG0_DPG_CONTROL_BASE_IDX 2 +#define mmDPG0_DPG_RAMP_CONTROL 0x1855 +#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 +#define mmDPG0_DPG_DIMENSIONS 0x1856 +#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2 +#define mmDPG0_DPG_COLOUR_R_CR 0x1857 +#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 +#define mmDPG0_DPG_COLOUR_G_Y 0x1858 +#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 +#define mmDPG0_DPG_COLOUR_B_CB 0x1859 +#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 +#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a +#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define mmDPG0_DPG_STATUS 0x185b +#define mmDPG0_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +// base address: 0x0 +#define mmOPPBUF0_OPPBUF_CONTROL 0x1884 +#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 +#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889 +#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +// base address: 0x0 +#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c +#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +// base address: 0x0 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 +#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt1_dispdec +// base address: 0x168 +#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 +#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 +#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 +#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 +#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_CONTROL 0x189a +#define mmFMT1_FMT_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b +#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c +#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d +#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e +#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT1_FMT_CLAMP_CNTL 0x189f +#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 +#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 +#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define mmFMT1_FMT_422_CONTROL 0x18a3 +#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg1_dispdec +// base address: 0x168 +#define mmDPG1_DPG_CONTROL 0x18ae +#define mmDPG1_DPG_CONTROL_BASE_IDX 2 +#define mmDPG1_DPG_RAMP_CONTROL 0x18af +#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 +#define mmDPG1_DPG_DIMENSIONS 0x18b0 +#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2 +#define mmDPG1_DPG_COLOUR_R_CR 0x18b1 +#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 +#define mmDPG1_DPG_COLOUR_G_Y 0x18b2 +#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 +#define mmDPG1_DPG_COLOUR_B_CB 0x18b3 +#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 +#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4 +#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define mmDPG1_DPG_STATUS 0x18b5 +#define mmDPG1_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +// base address: 0x168 +#define mmOPPBUF1_OPPBUF_CONTROL 0x18de +#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 +#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3 +#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +// base address: 0x168 +#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 +#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +// base address: 0x168 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef +#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt2_dispdec +// base address: 0x2d0 +#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 +#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 +#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 +#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 +#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT2_FMT_CONTROL 0x18f4 +#define mmFMT2_FMT_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 +#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 +#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 +#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 +#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT2_FMT_CLAMP_CNTL 0x18f9 +#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa +#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb +#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define mmFMT2_FMT_422_CONTROL 0x18fd +#define mmFMT2_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg2_dispdec +// base address: 0x2d0 +#define mmDPG2_DPG_CONTROL 0x1908 +#define mmDPG2_DPG_CONTROL_BASE_IDX 2 +#define mmDPG2_DPG_RAMP_CONTROL 0x1909 +#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 +#define mmDPG2_DPG_DIMENSIONS 0x190a +#define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2 +#define mmDPG2_DPG_COLOUR_R_CR 0x190b +#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 +#define mmDPG2_DPG_COLOUR_G_Y 0x190c +#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 +#define mmDPG2_DPG_COLOUR_B_CB 0x190d +#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 +#define mmDPG2_DPG_OFFSET_SEGMENT 0x190e +#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define mmDPG2_DPG_STATUS 0x190f +#define mmDPG2_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +// base address: 0x2d0 +#define mmOPPBUF2_OPPBUF_CONTROL 0x1938 +#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a +#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define mmOPPBUF2_OPPBUF_CONTROL1 0x193d +#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +// base address: 0x2d0 +#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 +#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +// base address: 0x2d0 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 +#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt3_dispdec +// base address: 0x438 +#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a +#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b +#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c +#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d +#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT3_FMT_CONTROL 0x194e +#define mmFMT3_FMT_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f +#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950 +#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951 +#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952 +#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT3_FMT_CLAMP_CNTL 0x1953 +#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 +#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 +#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define mmFMT3_FMT_422_CONTROL 0x1957 +#define mmFMT3_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg3_dispdec +// base address: 0x438 +#define mmDPG3_DPG_CONTROL 0x1962 +#define mmDPG3_DPG_CONTROL_BASE_IDX 2 +#define mmDPG3_DPG_RAMP_CONTROL 0x1963 +#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 +#define mmDPG3_DPG_DIMENSIONS 0x1964 +#define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2 +#define mmDPG3_DPG_COLOUR_R_CR 0x1965 +#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 +#define mmDPG3_DPG_COLOUR_G_Y 0x1966 +#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 +#define mmDPG3_DPG_COLOUR_B_CB 0x1967 +#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 +#define mmDPG3_DPG_OFFSET_SEGMENT 0x1968 +#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define mmDPG3_DPG_STATUS 0x1969 +#define mmDPG3_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +// base address: 0x438 +#define mmOPPBUF3_OPPBUF_CONTROL 0x1992 +#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 +#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define mmOPPBUF3_OPPBUF_CONTROL1 0x1997 +#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +// base address: 0x438 +#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a +#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +// base address: 0x438 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 +#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt4_dispdec +// base address: 0x5a0 +#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4 +#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5 +#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6 +#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7 +#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT4_FMT_CONTROL 0x19a8 +#define mmFMT4_FMT_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9 +#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa +#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab +#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac +#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT4_FMT_CLAMP_CNTL 0x19ad +#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae +#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af +#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define mmFMT4_FMT_422_CONTROL 0x19b1 +#define mmFMT4_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg4_dispdec +// base address: 0x5a0 +#define mmDPG4_DPG_CONTROL 0x19bc +#define mmDPG4_DPG_CONTROL_BASE_IDX 2 +#define mmDPG4_DPG_RAMP_CONTROL 0x19bd +#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2 +#define mmDPG4_DPG_DIMENSIONS 0x19be +#define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2 +#define mmDPG4_DPG_COLOUR_R_CR 0x19bf +#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2 +#define mmDPG4_DPG_COLOUR_G_Y 0x19c0 +#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2 +#define mmDPG4_DPG_COLOUR_B_CB 0x19c1 +#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2 +#define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2 +#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define mmDPG4_DPG_STATUS 0x19c3 +#define mmDPG4_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf4_dispdec +// base address: 0x5a0 +#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec +#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee +#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1 +#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe4_dispdec +// base address: 0x5a0 +#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4 +#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec +// base address: 0x5a0 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd +#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt5_dispdec +// base address: 0x708 +#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe +#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff +#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00 +#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01 +#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define mmFMT5_FMT_CONTROL 0x1a02 +#define mmFMT5_FMT_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03 +#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04 +#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05 +#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06 +#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define mmFMT5_FMT_CLAMP_CNTL 0x1a07 +#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2 +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a08 +#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a09 +#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define mmFMT5_FMT_422_CONTROL 0x1a0b +#define mmFMT5_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg5_dispdec +// base address: 0x708 +#define mmDPG5_DPG_CONTROL 0x1a16 +#define mmDPG5_DPG_CONTROL_BASE_IDX 2 +#define mmDPG5_DPG_RAMP_CONTROL 0x1a17 +#define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX 2 +#define mmDPG5_DPG_DIMENSIONS 0x1a18 +#define mmDPG5_DPG_DIMENSIONS_BASE_IDX 2 +#define mmDPG5_DPG_COLOUR_R_CR 0x1a19 +#define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX 2 +#define mmDPG5_DPG_COLOUR_G_Y 0x1a1a +#define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX 2 +#define mmDPG5_DPG_COLOUR_B_CB 0x1a1b +#define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX 2 +#define mmDPG5_DPG_OFFSET_SEGMENT 0x1a1c +#define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define mmDPG5_DPG_STATUS 0x1a1d +#define mmDPG5_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf5_dispdec +// base address: 0x708 +#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46 +#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48 +#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define mmOPPBUF5_OPPBUF_CONTROL1 0x1a4b +#define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe5_dispdec +// base address: 0x708 +#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e +#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec +// base address: 0x708 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57 +#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_top_dispdec +// base address: 0x0 +#define mmOPP_TOP_CLK_CONTROL 0x1a5e +#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +// base address: 0x0 +#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 +#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +// base address: 0x4 +#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 +#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +// base address: 0x8 +#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 +#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm3_dispdec +// base address: 0xc +#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 +#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm4_dispdec +// base address: 0x10 +#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68 +#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm5_dispdec +// base address: 0x14 +#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG 0x1a69 +#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +// base address: 0x6af8 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe +#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf +#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 +#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_CNTL 0x1ac1 +#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_CNTL2 0x1ac2 +#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 +#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 +#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_HI 0x1ac5 +#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON16_PERFMON_LOW 0x1ac6 +#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm0_dispdec +// base address: 0x0 +#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca +#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb +#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc +#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd +#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace +#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf +#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0 +#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 +#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm1_dispdec +// base address: 0x40 +#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada +#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb +#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc +#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add +#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade +#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf +#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0 +#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 +#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm2_dispdec +// base address: 0x80 +#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea +#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb +#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec +#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed +#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmODM2_OPTC_WIDTH_CONTROL 0x1aee +#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef +#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM2_OPTC_MEMORY_CONFIG 0x1af0 +#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 +#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm3_dispdec +// base address: 0xc0 +#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa +#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb +#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc +#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd +#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmODM3_OPTC_WIDTH_CONTROL 0x1afe +#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff +#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM3_OPTC_MEMORY_CONFIG 0x1b00 +#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 +#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm4_dispdec +// base address: 0x100 +#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a +#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b +#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c +#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d +#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e +#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f +#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM4_OPTC_MEMORY_CONFIG 0x1b10 +#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11 +#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm5_dispdec +// base address: 0x140 +#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a +#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b +#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define mmODM5_OPTC_DATA_FORMAT_CONTROL 0x1b1c +#define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define mmODM5_OPTC_BYTES_PER_PIXEL 0x1b1d +#define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmODM5_OPTC_WIDTH_CONTROL 0x1b1e +#define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1f +#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM5_OPTC_MEMORY_CONFIG 0x1b20 +#define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b21 +#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg0_dispdec +// base address: 0x0 +#define mmOTG0_OTG_H_TOTAL 0x1b2a +#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b +#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG0_OTG_H_SYNC_A 0x1b2c +#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d +#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e +#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL 0x1b2f +#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 +#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 +#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_MID 0x1b32 +#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 +#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 +#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 +#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_V_BLANK_START_END 0x1b36 +#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG0_OTG_V_SYNC_A 0x1b37 +#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 +#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGA_CNTL 0x1b39 +#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a +#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b +#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c +#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d +#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e +#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f +#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG0_OTG_CONTROL 0x1b41 +#define mmOTG0_OTG_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_BLANK_CONTROL 0x1b42 +#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43 +#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 +#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 +#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 +#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 +#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG0_OTG_STATUS 0x1b49 +#define mmOTG0_OTG_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_POSITION 0x1b4a +#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b +#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c +#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d +#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e +#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f +#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_COUNT_RESET 0x1b50 +#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 +#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 +#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_STATUS 0x1b53 +#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_STEREO_CONTROL 0x1b54 +#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 +#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 +#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 +#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 +#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 +#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a +#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b +#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_EN 0x1b5c +#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e +#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f +#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG0_OTG_BLACK_COLOR 0x1b60 +#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b61 +#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63 +#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65 +#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67 +#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC_CNTL 0x1b68 +#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG0_OTG_CRC_CNTL2 0x1b69 +#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a +#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b +#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c +#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d +#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e +#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f +#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70 +#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71 +#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72 +#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73 +#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74 +#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC1_DATA_B 0x1b75 +#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76 +#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC2_DATA_B 0x1b77 +#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78 +#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG0_OTG_CRC3_DATA_B 0x1b79 +#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a +#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b +#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82 +#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83 +#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84 +#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85 +#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86 +#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87 +#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88 +#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_VREADY_PARAM 0x1b89 +#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a +#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b +#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG0_OTG_GSL_CONTROL 0x1b8c +#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d +#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e +#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f +#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90 +#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91 +#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92 +#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93 +#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94 +#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95 +#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b96 +#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_DRR_CONTROL 0x1b97 +#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_REQUEST_CONTROL 0x1b98 +#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG0_OTG_DSC_START_POSITION 0x1b99 +#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 +#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9a +#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define mmOTG0_OTG_SPARE_REGISTER 0x1b9c +#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg1_dispdec +// base address: 0x200 +#define mmOTG1_OTG_H_TOTAL 0x1baa +#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG1_OTG_H_BLANK_START_END 0x1bab +#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG1_OTG_H_SYNC_A 0x1bac +#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad +#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae +#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL 0x1baf +#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 +#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 +#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 +#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 +#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 +#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 +#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 +#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG1_OTG_V_SYNC_A 0x1bb7 +#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 +#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 +#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba +#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb +#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc +#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd +#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe +#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf +#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG1_OTG_CONTROL 0x1bc1 +#define mmOTG1_OTG_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 +#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3 +#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 +#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 +#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 +#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 +#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG1_OTG_STATUS 0x1bc9 +#define mmOTG1_OTG_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_POSITION 0x1bca +#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb +#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc +#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd +#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce +#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf +#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_COUNT_RESET 0x1bd0 +#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 +#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 +#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_STATUS 0x1bd3 +#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 +#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 +#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 +#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 +#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 +#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 +#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_UPDATE_LOCK 0x1bda +#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb +#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_EN 0x1bdc +#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde +#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf +#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG1_OTG_BLACK_COLOR 0x1be0 +#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be1 +#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3 +#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5 +#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7 +#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC_CNTL 0x1be8 +#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG1_OTG_CRC_CNTL2 0x1be9 +#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea +#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb +#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec +#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed +#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee +#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC0_DATA_B 0x1bef +#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0 +#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1 +#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2 +#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3 +#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4 +#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5 +#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6 +#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7 +#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8 +#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9 +#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa +#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb +#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02 +#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03 +#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04 +#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05 +#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06 +#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07 +#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08 +#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_VREADY_PARAM 0x1c09 +#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a +#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b +#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG1_OTG_GSL_CONTROL 0x1c0c +#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d +#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e +#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f +#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10 +#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11 +#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12 +#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13 +#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14 +#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15 +#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c16 +#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_DRR_CONTROL 0x1c17 +#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_REQUEST_CONTROL 0x1c18 +#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG1_OTG_DSC_START_POSITION 0x1c19 +#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 +#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1a +#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define mmOTG1_OTG_SPARE_REGISTER 0x1c1c +#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg2_dispdec +// base address: 0x400 +#define mmOTG2_OTG_H_TOTAL 0x1c2a +#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b +#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG2_OTG_H_SYNC_A 0x1c2c +#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d +#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e +#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL 0x1c2f +#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30 +#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31 +#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_MID 0x1c32 +#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33 +#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 +#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 +#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_V_BLANK_START_END 0x1c36 +#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG2_OTG_V_SYNC_A 0x1c37 +#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38 +#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_TRIGA_CNTL 0x1c39 +#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a +#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b +#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c +#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d +#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e +#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f +#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG2_OTG_CONTROL 0x1c41 +#define mmOTG2_OTG_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_BLANK_CONTROL 0x1c42 +#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43 +#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44 +#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45 +#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 +#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 +#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG2_OTG_STATUS 0x1c49 +#define mmOTG2_OTG_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_STATUS_POSITION 0x1c4a +#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b +#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c +#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d +#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e +#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f +#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_COUNT_RESET 0x1c50 +#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 +#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 +#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_STEREO_STATUS 0x1c53 +#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_STEREO_CONTROL 0x1c54 +#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55 +#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 +#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57 +#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58 +#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59 +#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a +#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b +#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_MASTER_EN 0x1c5c +#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e +#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f +#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG2_OTG_BLACK_COLOR 0x1c60 +#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c61 +#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63 +#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65 +#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67 +#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC_CNTL 0x1c68 +#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG2_OTG_CRC_CNTL2 0x1c69 +#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a +#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b +#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c +#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d +#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e +#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG2_OTG_CRC0_DATA_B 0x1c6f +#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70 +#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71 +#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72 +#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73 +#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_DATA_RG 0x1c74 +#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG2_OTG_CRC1_DATA_B 0x1c75 +#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG2_OTG_CRC2_DATA_RG 0x1c76 +#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG2_OTG_CRC2_DATA_B 0x1c77 +#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG2_OTG_CRC3_DATA_RG 0x1c78 +#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG2_OTG_CRC3_DATA_B 0x1c79 +#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a +#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b +#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82 +#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83 +#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84 +#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85 +#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG2_OTG_CLOCK_CONTROL 0x1c86 +#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87 +#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG2_OTG_VUPDATE_PARAM 0x1c88 +#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG2_OTG_VREADY_PARAM 0x1c89 +#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a +#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b +#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG2_OTG_GSL_CONTROL 0x1c8c +#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d +#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e +#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f +#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90 +#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91 +#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92 +#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93 +#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94 +#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95 +#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c96 +#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_DRR_CONTROL 0x1c97 +#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_REQUEST_CONTROL 0x1c98 +#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG2_OTG_DSC_START_POSITION 0x1c99 +#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 +#define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9a +#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define mmOTG2_OTG_SPARE_REGISTER 0x1c9c +#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg3_dispdec +// base address: 0x600 +#define mmOTG3_OTG_H_TOTAL 0x1caa +#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG3_OTG_H_BLANK_START_END 0x1cab +#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG3_OTG_H_SYNC_A 0x1cac +#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad +#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae +#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL 0x1caf +#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0 +#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1 +#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2 +#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 +#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 +#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 +#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6 +#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG3_OTG_V_SYNC_A 0x1cb7 +#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 +#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9 +#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba +#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb +#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc +#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd +#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe +#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf +#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG3_OTG_CONTROL 0x1cc1 +#define mmOTG3_OTG_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2 +#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3 +#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4 +#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5 +#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 +#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 +#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG3_OTG_STATUS 0x1cc9 +#define mmOTG3_OTG_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_STATUS_POSITION 0x1cca +#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb +#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc +#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd +#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce +#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf +#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_COUNT_RESET 0x1cd0 +#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 +#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 +#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_STEREO_STATUS 0x1cd3 +#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4 +#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 +#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 +#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 +#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 +#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 +#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_UPDATE_LOCK 0x1cda +#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb +#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_MASTER_EN 0x1cdc +#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde +#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf +#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG3_OTG_BLACK_COLOR 0x1ce0 +#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce1 +#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3 +#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5 +#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7 +#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC_CNTL 0x1ce8 +#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG3_OTG_CRC_CNTL2 0x1ce9 +#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea +#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb +#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec +#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced +#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_DATA_RG 0x1cee +#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG3_OTG_CRC0_DATA_B 0x1cef +#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0 +#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1 +#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2 +#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3 +#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4 +#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG3_OTG_CRC1_DATA_B 0x1cf5 +#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6 +#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG3_OTG_CRC2_DATA_B 0x1cf7 +#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8 +#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG3_OTG_CRC3_DATA_B 0x1cf9 +#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa +#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb +#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02 +#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03 +#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04 +#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05 +#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG3_OTG_CLOCK_CONTROL 0x1d06 +#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07 +#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG3_OTG_VUPDATE_PARAM 0x1d08 +#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG3_OTG_VREADY_PARAM 0x1d09 +#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a +#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b +#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG3_OTG_GSL_CONTROL 0x1d0c +#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d +#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e +#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f +#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10 +#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11 +#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12 +#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13 +#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14 +#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15 +#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d16 +#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_DRR_CONTROL 0x1d17 +#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_REQUEST_CONTROL 0x1d18 +#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG3_OTG_DSC_START_POSITION 0x1d19 +#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 +#define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1a +#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define mmOTG3_OTG_SPARE_REGISTER 0x1d1c +#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg4_dispdec +// base address: 0x800 +#define mmOTG4_OTG_H_TOTAL 0x1d2a +#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b +#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG4_OTG_H_SYNC_A 0x1d2c +#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d +#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e +#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL 0x1d2f +#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30 +#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31 +#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_MID 0x1d32 +#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33 +#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34 +#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35 +#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_V_BLANK_START_END 0x1d36 +#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG4_OTG_V_SYNC_A 0x1d37 +#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38 +#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_TRIGA_CNTL 0x1d39 +#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a +#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b +#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c +#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d +#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e +#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f +#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG4_OTG_CONTROL 0x1d41 +#define mmOTG4_OTG_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_BLANK_CONTROL 0x1d42 +#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43 +#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44 +#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45 +#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47 +#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48 +#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG4_OTG_STATUS 0x1d49 +#define mmOTG4_OTG_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_STATUS_POSITION 0x1d4a +#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b +#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c +#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d +#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e +#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f +#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_COUNT_RESET 0x1d50 +#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51 +#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52 +#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_STEREO_STATUS 0x1d53 +#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_STEREO_CONTROL 0x1d54 +#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55 +#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56 +#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57 +#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58 +#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59 +#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a +#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b +#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_MASTER_EN 0x1d5c +#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e +#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f +#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG4_OTG_BLACK_COLOR 0x1d60 +#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d61 +#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63 +#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65 +#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67 +#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC_CNTL 0x1d68 +#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG4_OTG_CRC_CNTL2 0x1d69 +#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a +#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b +#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c +#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d +#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e +#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG4_OTG_CRC0_DATA_B 0x1d6f +#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70 +#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71 +#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72 +#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73 +#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_DATA_RG 0x1d74 +#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG4_OTG_CRC1_DATA_B 0x1d75 +#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG4_OTG_CRC2_DATA_RG 0x1d76 +#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG4_OTG_CRC2_DATA_B 0x1d77 +#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG4_OTG_CRC3_DATA_RG 0x1d78 +#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG4_OTG_CRC3_DATA_B 0x1d79 +#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a +#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b +#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82 +#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83 +#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84 +#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85 +#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG4_OTG_CLOCK_CONTROL 0x1d86 +#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87 +#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG4_OTG_VUPDATE_PARAM 0x1d88 +#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG4_OTG_VREADY_PARAM 0x1d89 +#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a +#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b +#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG4_OTG_GSL_CONTROL 0x1d8c +#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d +#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e +#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f +#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90 +#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91 +#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92 +#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93 +#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d94 +#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d95 +#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d96 +#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_DRR_CONTROL 0x1d97 +#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_REQUEST_CONTROL 0x1d98 +#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG4_OTG_DSC_START_POSITION 0x1d99 +#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2 +#define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1d9a +#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define mmOTG4_OTG_SPARE_REGISTER 0x1d9c +#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg5_dispdec +// base address: 0xa00 +#define mmOTG5_OTG_H_TOTAL 0x1daa +#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2 +#define mmOTG5_OTG_H_BLANK_START_END 0x1dab +#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2 +#define mmOTG5_OTG_H_SYNC_A 0x1dac +#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2 +#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad +#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae +#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL 0x1daf +#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0 +#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1 +#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_MID 0x1db2 +#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3 +#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4 +#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5 +#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_V_BLANK_START_END 0x1db6 +#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2 +#define mmOTG5_OTG_V_SYNC_A 0x1db7 +#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2 +#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8 +#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_TRIGA_CNTL 0x1db9 +#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba +#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb +#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc +#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd +#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe +#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf +#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define mmOTG5_OTG_CONTROL 0x1dc1 +#define mmOTG5_OTG_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2 +#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3 +#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4 +#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5 +#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7 +#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8 +#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define mmOTG5_OTG_STATUS 0x1dc9 +#define mmOTG5_OTG_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_STATUS_POSITION 0x1dca +#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb +#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc +#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd +#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce +#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf +#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_COUNT_RESET 0x1dd0 +#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2 +#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1 +#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2 +#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_STEREO_STATUS 0x1dd3 +#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4 +#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5 +#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6 +#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7 +#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8 +#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 +#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_UPDATE_LOCK 0x1dda +#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb +#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_MASTER_EN 0x1ddc +#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2 +#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1dde +#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2 +#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1ddf +#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 +#define mmOTG5_OTG_BLACK_COLOR 0x1de0 +#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2 +#define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de1 +#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de3 +#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de4 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de5 +#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de6 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1de7 +#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC_CNTL 0x1de8 +#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2 +#define mmOTG5_OTG_CRC_CNTL2 0x1de9 +#define mmOTG5_OTG_CRC_CNTL2_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dea +#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1deb +#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dec +#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ded +#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_DATA_RG 0x1dee +#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2 +#define mmOTG5_OTG_CRC0_DATA_B 0x1def +#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df0 +#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df1 +#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df2 +#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df3 +#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_DATA_RG 0x1df4 +#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2 +#define mmOTG5_OTG_CRC1_DATA_B 0x1df5 +#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2 +#define mmOTG5_OTG_CRC2_DATA_RG 0x1df6 +#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2 +#define mmOTG5_OTG_CRC2_DATA_B 0x1df7 +#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2 +#define mmOTG5_OTG_CRC3_DATA_RG 0x1df8 +#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2 +#define mmOTG5_OTG_CRC3_DATA_B 0x1df9 +#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2 +#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfa +#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfb +#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e02 +#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e03 +#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e04 +#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e05 +#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define mmOTG5_OTG_CLOCK_CONTROL 0x1e06 +#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e07 +#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define mmOTG5_OTG_VUPDATE_PARAM 0x1e08 +#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define mmOTG5_OTG_VREADY_PARAM 0x1e09 +#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0a +#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0b +#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define mmOTG5_OTG_GSL_CONTROL 0x1e0c +#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0d +#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e0e +#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e0f +#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e10 +#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e11 +#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e12 +#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e13 +#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e14 +#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e15 +#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e16 +#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_DRR_CONTROL 0x1e17 +#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_REQUEST_CONTROL 0x1e18 +#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define mmOTG5_OTG_DSC_START_POSITION 0x1e19 +#define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX 2 +#define mmOTG5_OTG_PIPE_UPDATE_STATUS 0x1e1a +#define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define mmOTG5_OTG_SPARE_REGISTER 0x1e1c +#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +// base address: 0x0 +#define mmDWB_SOURCE_SELECT 0x1e2a +#define mmDWB_SOURCE_SELECT_BASE_IDX 2 +#define mmGSL_SOURCE_SELECT 0x1e2b +#define mmGSL_SOURCE_SELECT_BASE_IDX 2 +#define mmOPTC_CLOCK_CONTROL 0x1e2c +#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 +#define mmODM_MEM_PWR_CTRL 0x1e2d +#define mmODM_MEM_PWR_CTRL_BASE_IDX 2 +#define mmODM_MEM_PWR_CTRL2 0x1e2e +#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmODM_MEM_PWR_CTRL3 0x1e2f +#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2 +#define mmODM_MEM_PWR_STATUS 0x1e30 +#define mmODM_MEM_PWR_STATUS_BASE_IDX 2 +#define mmOPTC_MISC_SPARE_REGISTER 0x1e31 +#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +// base address: 0x79a8 +#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a +#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b +#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c +#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_CNTL 0x1e6d +#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_CNTL2 0x1e6e +#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f +#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 +#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_HI 0x1e71 +#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON17_PERFMON_LOW 0x1e72 +#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +// base address: 0x0 +#define mmDC_I2C_CONTROL 0x1e98 +#define mmDC_I2C_CONTROL_BASE_IDX 2 +#define mmDC_I2C_ARBITRATION 0x1e99 +#define mmDC_I2C_ARBITRATION_BASE_IDX 2 +#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a +#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDC_I2C_SW_STATUS 0x1e9b +#define mmDC_I2C_SW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c +#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d +#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e +#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f +#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0 +#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 +#define mmDC_I2C_DDC1_SPEED 0x1ea2 +#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC1_SETUP 0x1ea3 +#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC2_SPEED 0x1ea4 +#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC2_SETUP 0x1ea5 +#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC3_SPEED 0x1ea6 +#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC3_SETUP 0x1ea7 +#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC4_SPEED 0x1ea8 +#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC4_SETUP 0x1ea9 +#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2 +#define mmDC_I2C_DDC5_SPEED 0x1eaa +#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2 +#define mmDC_I2C_DDC5_SETUP 0x1eab +#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION0 0x1eae +#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION1 0x1eaf +#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION2 0x1eb0 +#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 +#define mmDC_I2C_TRANSACTION3 0x1eb1 +#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 +#define mmDC_I2C_DATA 0x1eb2 +#define mmDC_I2C_DATA_BASE_IDX 2 +#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 +#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 +#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +// base address: 0x0 +#define mmDIO_SCRATCH0 0x1eca +#define mmDIO_SCRATCH0_BASE_IDX 2 +#define mmDIO_SCRATCH1 0x1ecb +#define mmDIO_SCRATCH1_BASE_IDX 2 +#define mmDIO_SCRATCH2 0x1ecc +#define mmDIO_SCRATCH2_BASE_IDX 2 +#define mmDIO_SCRATCH3 0x1ecd +#define mmDIO_SCRATCH3_BASE_IDX 2 +#define mmDIO_SCRATCH4 0x1ece +#define mmDIO_SCRATCH4_BASE_IDX 2 +#define mmDIO_SCRATCH5 0x1ecf +#define mmDIO_SCRATCH5_BASE_IDX 2 +#define mmDIO_SCRATCH6 0x1ed0 +#define mmDIO_SCRATCH6_BASE_IDX 2 +#define mmDIO_SCRATCH7 0x1ed1 +#define mmDIO_SCRATCH7_BASE_IDX 2 +#define mmDCE_VCE_CONTROL 0x1ed2 +#define mmDCE_VCE_CONTROL_BASE_IDX 2 +#define mmDIO_MEM_PWR_STATUS 0x1edd +#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 +#define mmDIO_MEM_PWR_CTRL 0x1ede +#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 +#define mmDIO_MEM_PWR_CTRL2 0x1edf +#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 +#define mmDIO_CLK_CNTL 0x1ee0 +#define mmDIO_CLK_CNTL_BASE_IDX 2 +#define mmDIO_MEM_PWR_CTRL3 0x1ee1 +#define mmDIO_MEM_PWR_CTRL3_BASE_IDX 2 +#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 +#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define mmDIG_SOFT_RESET 0x1eee +#define mmDIG_SOFT_RESET_BASE_IDX 2 +#define mmDIO_MEM_PWR_STATUS1 0x1ef0 +#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2 +#define mmDIO_CLK_CNTL2 0x1ef2 +#define mmDIO_CLK_CNTL2_BASE_IDX 2 +#define mmDIO_CLK_CNTL3 0x1ef3 +#define mmDIO_CLK_CNTL3_BASE_IDX 2 +#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff +#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define mmDIO_PSP_INTERRUPT_STATUS 0x1f00 +#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01 +#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 +#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 +#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 +#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 +#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd0_dispdec +// base address: 0x0 +#define mmHPD0_DC_HPD_INT_STATUS 0x1f14 +#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 +#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD0_DC_HPD_CONTROL 0x1f16 +#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 +#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 +#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd1_dispdec +// base address: 0x20 +#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c +#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d +#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD1_DC_HPD_CONTROL 0x1f1e +#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f +#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 +#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd2_dispdec +// base address: 0x40 +#define mmHPD2_DC_HPD_INT_STATUS 0x1f24 +#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25 +#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD2_DC_HPD_CONTROL 0x1f26 +#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 +#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 +#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd3_dispdec +// base address: 0x60 +#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c +#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d +#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD3_DC_HPD_CONTROL 0x1f2e +#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f +#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 +#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_hpd4_dispdec +// base address: 0x80 +#define mmHPD4_DC_HPD_INT_STATUS 0x1f34 +#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 +#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35 +#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define mmHPD4_DC_HPD_CONTROL 0x1f36 +#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 +#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 +#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +// base address: 0x7d10 +#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 +#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 +#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 +#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_CNTL 0x1f47 +#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_CNTL2 0x1f48 +#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 +#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a +#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_HI 0x1f4b +#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON18_PERFMON_LOW 0x1f4c +#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +// base address: 0x0 +#define mmDP_AUX0_AUX_CONTROL 0x1f50 +#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 +#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 +#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 +#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_STATUS 0x1f54 +#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_LS_STATUS 0x1f55 +#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_SW_DATA 0x1f56 +#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX0_AUX_LS_DATA 0x1f57 +#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 +#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 +#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b +#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c +#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d +#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f +#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 +#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 +#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 +#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +// base address: 0x70 +#define mmDP_AUX1_AUX_CONTROL 0x1f6c +#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d +#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e +#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f +#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_STATUS 0x1f70 +#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_LS_STATUS 0x1f71 +#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_SW_DATA 0x1f72 +#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX1_AUX_LS_DATA 0x1f73 +#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 +#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 +#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 +#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 +#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 +#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b +#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c +#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d +#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 +#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +// base address: 0xe0 +#define mmDP_AUX2_AUX_CONTROL 0x1f88 +#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89 +#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a +#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b +#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c +#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d +#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_SW_DATA 0x1f8e +#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX2_AUX_LS_DATA 0x1f8f +#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 +#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 +#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 +#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 +#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 +#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 +#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 +#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 +#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e +#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +// base address: 0x150 +#define mmDP_AUX3_AUX_CONTROL 0x1fa4 +#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5 +#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6 +#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 +#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8 +#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9 +#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_SW_DATA 0x1faa +#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX3_AUX_LS_DATA 0x1fab +#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac +#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad +#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf +#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 +#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 +#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 +#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 +#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 +#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba +#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +// base address: 0x1c0 +#define mmDP_AUX4_AUX_CONTROL 0x1fc0 +#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1 +#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2 +#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 +#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4 +#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5 +#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_SW_DATA 0x1fc6 +#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2 +#define mmDP_AUX4_AUX_LS_DATA 0x1fc7 +#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 +#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 +#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb +#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc +#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd +#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf +#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 +#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 +#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 +#define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 +#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dispdec +// base address: 0x0 +#define mmDIG0_DIG_FE_CNTL 0x2068 +#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069 +#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a +#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG0_DIG_CLOCK_PATTERN 0x206b +#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG0_DIG_TEST_PATTERN 0x206c +#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d +#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG0_DIG_FIFO_STATUS 0x206e +#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x206f +#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x2070 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define mmDIG0_HDMI_CONTROL 0x2071 +#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_STATUS 0x2072 +#define mmDIG0_HDMI_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073 +#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074 +#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075 +#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076 +#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077 +#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079 +#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG0_HDMI_GC 0x207b +#define mmDIG0_HDMI_GC_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_0 0x207d +#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_1 0x207e +#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_2 0x207f +#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_3 0x2080 +#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC1_4 0x2081 +#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_0 0x2082 +#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_1 0x2083 +#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_2 0x2084 +#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG0_AFMT_ISRC2_3 0x2085 +#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG0_HDMI_DB_CONTROL 0x2088 +#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG0_DME_CONTROL 0x2089 +#define mmDIG0_DME_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_MPEG_INFO0 0x208a +#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG0_AFMT_MPEG_INFO1 0x208b +#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_HDR 0x208c +#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_0 0x208d +#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_1 0x208e +#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_2 0x208f +#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_3 0x2090 +#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_4 0x2091 +#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_5 0x2092 +#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_6 0x2093 +#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG0_AFMT_GENERIC_7 0x2094 +#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_32_0 0x2096 +#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_32_1 0x2097 +#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_44_0 0x2098 +#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_44_1 0x2099 +#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_48_0 0x209a +#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_48_1 0x209b +#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_STATUS_0 0x209c +#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG0_HDMI_ACR_STATUS_1 0x209d +#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_INFO0 0x209e +#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_INFO1 0x209f +#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG0_AFMT_60958_0 0x20a0 +#define mmDIG0_AFMT_60958_0_BASE_IDX 2 +#define mmDIG0_AFMT_60958_1 0x20a1 +#define mmDIG0_AFMT_60958_1_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2 +#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3 +#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4 +#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5 +#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6 +#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG0_AFMT_60958_2 0x20a7 +#define mmDIG0_AFMT_60958_2_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8 +#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG0_AFMT_STATUS 0x20a9 +#define mmDIG0_AFMT_STATUS_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa +#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab +#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac +#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad +#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG0_DIG_BE_CNTL 0x20af +#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_BE_EN_CNTL 0x20b0 +#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CNTL 0x20d3 +#define mmDIG0_TMDS_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4 +#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5 +#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6 +#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8 +#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG0_TMDS_CTL_BITS 0x20da +#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db +#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20dc +#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd +#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de +#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG0_DIG_VERSION 0x20e0 +#define mmDIG0_DIG_VERSION_BASE_IDX 2 +#define mmDIG0_DIG_LANE_ENABLE 0x20e1 +#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG0_AFMT_CNTL 0x20e6 +#define mmDIG0_AFMT_CNTL_BASE_IDX 2 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7 +#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20f6 +#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define mmDIG0_FORCE_DIG_DISABLE 0x20f7 +#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp0_dispdec +// base address: 0x0 +#define mmDP0_DP_LINK_CNTL 0x2108 +#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP0_DP_PIXEL_FORMAT 0x2109 +#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP0_DP_MSA_COLORIMETRY 0x210a +#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP0_DP_CONFIG 0x210b +#define mmDP0_DP_CONFIG_BASE_IDX 2 +#define mmDP0_DP_VID_STREAM_CNTL 0x210c +#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP0_DP_STEER_FIFO 0x210d +#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP0_DP_MSA_MISC 0x210e +#define mmDP0_DP_MSA_MISC_BASE_IDX 2 +#define mmDP0_DP_VID_TIMING 0x2110 +#define mmDP0_DP_VID_TIMING_BASE_IDX 2 +#define mmDP0_DP_VID_N 0x2111 +#define mmDP0_DP_VID_N_BASE_IDX 2 +#define mmDP0_DP_VID_M 0x2112 +#define mmDP0_DP_VID_M_BASE_IDX 2 +#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 +#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 +#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP0_DP_VID_MSA_VBID 0x2115 +#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 +#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CNTL 0x2117 +#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 +#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM0 0x2119 +#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM1 0x211a +#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP0_DP_DPHY_SYM2 0x211b +#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c +#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d +#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e +#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_EN 0x211f +#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_CNTL 0x2120 +#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_RESULT 0x2121 +#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 +#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 +#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 +#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 +#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL 0x212b +#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL1 0x212c +#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING1 0x212d +#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING2 0x212e +#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING3 0x212f +#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP0_DP_SEC_FRAMING4 0x2130 +#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_N 0x2131 +#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 +#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_M 0x2133 +#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 +#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP0_DP_SEC_TIMESTAMP 0x2135 +#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP0_DP_SEC_PACKET_CNTL 0x2136 +#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSE_RATE_CNTL 0x2137 +#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSE_RATE_UPDATE 0x2139 +#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT0 0x213a +#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT1 0x213b +#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT2 0x213c +#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT_UPDATE 0x213d +#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP0_DP_MSE_LINK_TIMING 0x213e +#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP0_DP_MSE_MISC_CNTL 0x213f +#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 +#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 +#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT0_STATUS 0x2147 +#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT1_STATUS 0x2148 +#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSE_SAT2_STATUS 0x2149 +#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c +#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d +#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e +#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f +#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP0_DP_MSO_CNTL 0x2150 +#define mmDP0_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSO_CNTL1 0x2151 +#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP0_DP_DSC_CNTL 0x2152 +#define mmDP0_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL2 0x2153 +#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL3 0x2154 +#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL4 0x2155 +#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL5 0x2156 +#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL6 0x2157 +#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP0_DP_SEC_CNTL7 0x2158 +#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP0_DP_DB_CNTL 0x2159 +#define mmDP0_DP_DB_CNTL_BASE_IDX 2 +#define mmDP0_DP_MSA_VBID_MISC 0x215a +#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 +#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b +#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c +#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmDP0_DP_ALPM_CNTL 0x215d +#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dispdec +// base address: 0x400 +#define mmDIG1_DIG_FE_CNTL 0x2168 +#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169 +#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a +#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG1_DIG_CLOCK_PATTERN 0x216b +#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG1_DIG_TEST_PATTERN 0x216c +#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d +#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG1_DIG_FIFO_STATUS 0x216e +#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x216f +#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x2170 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define mmDIG1_HDMI_CONTROL 0x2171 +#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_STATUS 0x2172 +#define mmDIG1_HDMI_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173 +#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174 +#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175 +#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176 +#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177 +#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179 +#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG1_HDMI_GC 0x217b +#define mmDIG1_HDMI_GC_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_0 0x217d +#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_1 0x217e +#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_2 0x217f +#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_3 0x2180 +#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC1_4 0x2181 +#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_0 0x2182 +#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_1 0x2183 +#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_2 0x2184 +#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG1_AFMT_ISRC2_3 0x2185 +#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG1_HDMI_DB_CONTROL 0x2188 +#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG1_DME_CONTROL 0x2189 +#define mmDIG1_DME_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_MPEG_INFO0 0x218a +#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG1_AFMT_MPEG_INFO1 0x218b +#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_HDR 0x218c +#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_0 0x218d +#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_1 0x218e +#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_2 0x218f +#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_3 0x2190 +#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_4 0x2191 +#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_5 0x2192 +#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_6 0x2193 +#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG1_AFMT_GENERIC_7 0x2194 +#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_32_0 0x2196 +#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_32_1 0x2197 +#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_44_0 0x2198 +#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_44_1 0x2199 +#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_48_0 0x219a +#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_48_1 0x219b +#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_STATUS_0 0x219c +#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG1_HDMI_ACR_STATUS_1 0x219d +#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_INFO0 0x219e +#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_INFO1 0x219f +#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG1_AFMT_60958_0 0x21a0 +#define mmDIG1_AFMT_60958_0_BASE_IDX 2 +#define mmDIG1_AFMT_60958_1 0x21a1 +#define mmDIG1_AFMT_60958_1_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2 +#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3 +#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4 +#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5 +#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6 +#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG1_AFMT_60958_2 0x21a7 +#define mmDIG1_AFMT_60958_2_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8 +#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG1_AFMT_STATUS 0x21a9 +#define mmDIG1_AFMT_STATUS_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa +#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab +#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac +#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad +#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG1_DIG_BE_CNTL 0x21af +#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_BE_EN_CNTL 0x21b0 +#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CNTL 0x21d3 +#define mmDIG1_TMDS_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4 +#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5 +#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6 +#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8 +#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG1_TMDS_CTL_BITS 0x21da +#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db +#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21dc +#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd +#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de +#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG1_DIG_VERSION 0x21e0 +#define mmDIG1_DIG_VERSION_BASE_IDX 2 +#define mmDIG1_DIG_LANE_ENABLE 0x21e1 +#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG1_AFMT_CNTL 0x21e6 +#define mmDIG1_AFMT_CNTL_BASE_IDX 2 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7 +#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21f6 +#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define mmDIG1_FORCE_DIG_DISABLE 0x21f7 +#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp1_dispdec +// base address: 0x400 +#define mmDP1_DP_LINK_CNTL 0x2208 +#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP1_DP_PIXEL_FORMAT 0x2209 +#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP1_DP_MSA_COLORIMETRY 0x220a +#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP1_DP_CONFIG 0x220b +#define mmDP1_DP_CONFIG_BASE_IDX 2 +#define mmDP1_DP_VID_STREAM_CNTL 0x220c +#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP1_DP_STEER_FIFO 0x220d +#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP1_DP_MSA_MISC 0x220e +#define mmDP1_DP_MSA_MISC_BASE_IDX 2 +#define mmDP1_DP_VID_TIMING 0x2210 +#define mmDP1_DP_VID_TIMING_BASE_IDX 2 +#define mmDP1_DP_VID_N 0x2211 +#define mmDP1_DP_VID_N_BASE_IDX 2 +#define mmDP1_DP_VID_M 0x2212 +#define mmDP1_DP_VID_M_BASE_IDX 2 +#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 +#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 +#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP1_DP_VID_MSA_VBID 0x2215 +#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 +#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CNTL 0x2217 +#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 +#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM0 0x2219 +#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM1 0x221a +#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP1_DP_DPHY_SYM2 0x221b +#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c +#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d +#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e +#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_EN 0x221f +#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_CNTL 0x2220 +#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_RESULT 0x2221 +#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 +#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 +#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 +#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 +#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL 0x222b +#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL1 0x222c +#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING1 0x222d +#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING2 0x222e +#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING3 0x222f +#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP1_DP_SEC_FRAMING4 0x2230 +#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_N 0x2231 +#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 +#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_M 0x2233 +#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 +#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP1_DP_SEC_TIMESTAMP 0x2235 +#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP1_DP_SEC_PACKET_CNTL 0x2236 +#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSE_RATE_CNTL 0x2237 +#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSE_RATE_UPDATE 0x2239 +#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT0 0x223a +#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT1 0x223b +#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT2 0x223c +#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT_UPDATE 0x223d +#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP1_DP_MSE_LINK_TIMING 0x223e +#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP1_DP_MSE_MISC_CNTL 0x223f +#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 +#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 +#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT0_STATUS 0x2247 +#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT1_STATUS 0x2248 +#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSE_SAT2_STATUS 0x2249 +#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c +#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d +#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e +#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f +#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP1_DP_MSO_CNTL 0x2250 +#define mmDP1_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSO_CNTL1 0x2251 +#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP1_DP_DSC_CNTL 0x2252 +#define mmDP1_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL2 0x2253 +#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL3 0x2254 +#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL4 0x2255 +#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL5 0x2256 +#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL6 0x2257 +#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP1_DP_SEC_CNTL7 0x2258 +#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP1_DP_DB_CNTL 0x2259 +#define mmDP1_DP_DB_CNTL_BASE_IDX 2 +#define mmDP1_DP_MSA_VBID_MISC 0x225a +#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 +#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b +#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c +#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmDP1_DP_ALPM_CNTL 0x225d +#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dispdec +// base address: 0x800 +#define mmDIG2_DIG_FE_CNTL 0x2268 +#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269 +#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a +#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG2_DIG_CLOCK_PATTERN 0x226b +#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG2_DIG_TEST_PATTERN 0x226c +#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d +#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG2_DIG_FIFO_STATUS 0x226e +#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x226f +#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x2270 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define mmDIG2_HDMI_CONTROL 0x2271 +#define mmDIG2_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_STATUS 0x2272 +#define mmDIG2_HDMI_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273 +#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274 +#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275 +#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276 +#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277 +#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279 +#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG2_HDMI_GC 0x227b +#define mmDIG2_HDMI_GC_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_0 0x227d +#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_1 0x227e +#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_2 0x227f +#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_3 0x2280 +#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC1_4 0x2281 +#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_0 0x2282 +#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_1 0x2283 +#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_2 0x2284 +#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG2_AFMT_ISRC2_3 0x2285 +#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG2_HDMI_DB_CONTROL 0x2288 +#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG2_DME_CONTROL 0x2289 +#define mmDIG2_DME_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_MPEG_INFO0 0x228a +#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG2_AFMT_MPEG_INFO1 0x228b +#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_HDR 0x228c +#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_0 0x228d +#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_1 0x228e +#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_2 0x228f +#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_3 0x2290 +#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_4 0x2291 +#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_5 0x2292 +#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_6 0x2293 +#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG2_AFMT_GENERIC_7 0x2294 +#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_32_0 0x2296 +#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_32_1 0x2297 +#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_44_0 0x2298 +#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_44_1 0x2299 +#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_48_0 0x229a +#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_48_1 0x229b +#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_STATUS_0 0x229c +#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG2_HDMI_ACR_STATUS_1 0x229d +#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_INFO0 0x229e +#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_INFO1 0x229f +#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG2_AFMT_60958_0 0x22a0 +#define mmDIG2_AFMT_60958_0_BASE_IDX 2 +#define mmDIG2_AFMT_60958_1 0x22a1 +#define mmDIG2_AFMT_60958_1_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2 +#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3 +#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4 +#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5 +#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6 +#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG2_AFMT_60958_2 0x22a7 +#define mmDIG2_AFMT_60958_2_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8 +#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG2_AFMT_STATUS 0x22a9 +#define mmDIG2_AFMT_STATUS_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa +#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab +#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac +#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad +#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG2_DIG_BE_CNTL 0x22af +#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_BE_EN_CNTL 0x22b0 +#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CNTL 0x22d3 +#define mmDIG2_TMDS_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CONTROL_CHAR 0x22d4 +#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5 +#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6 +#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8 +#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG2_TMDS_CTL_BITS 0x22da +#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db +#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22dc +#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd +#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de +#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG2_DIG_VERSION 0x22e0 +#define mmDIG2_DIG_VERSION_BASE_IDX 2 +#define mmDIG2_DIG_LANE_ENABLE 0x22e1 +#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG2_AFMT_CNTL 0x22e6 +#define mmDIG2_AFMT_CNTL_BASE_IDX 2 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7 +#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22f6 +#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define mmDIG2_FORCE_DIG_DISABLE 0x22f7 +#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp2_dispdec +// base address: 0x800 +#define mmDP2_DP_LINK_CNTL 0x2308 +#define mmDP2_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP2_DP_PIXEL_FORMAT 0x2309 +#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP2_DP_MSA_COLORIMETRY 0x230a +#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP2_DP_CONFIG 0x230b +#define mmDP2_DP_CONFIG_BASE_IDX 2 +#define mmDP2_DP_VID_STREAM_CNTL 0x230c +#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP2_DP_STEER_FIFO 0x230d +#define mmDP2_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP2_DP_MSA_MISC 0x230e +#define mmDP2_DP_MSA_MISC_BASE_IDX 2 +#define mmDP2_DP_VID_TIMING 0x2310 +#define mmDP2_DP_VID_TIMING_BASE_IDX 2 +#define mmDP2_DP_VID_N 0x2311 +#define mmDP2_DP_VID_N_BASE_IDX 2 +#define mmDP2_DP_VID_M 0x2312 +#define mmDP2_DP_VID_M_BASE_IDX 2 +#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313 +#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314 +#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP2_DP_VID_MSA_VBID 0x2315 +#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316 +#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CNTL 0x2317 +#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 +#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM0 0x2319 +#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM1 0x231a +#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP2_DP_DPHY_SYM2 0x231b +#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c +#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d +#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e +#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_EN 0x231f +#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_CNTL 0x2320 +#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_RESULT 0x2321 +#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322 +#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323 +#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324 +#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 +#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL 0x232b +#define mmDP2_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL1 0x232c +#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING1 0x232d +#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING2 0x232e +#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING3 0x232f +#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP2_DP_SEC_FRAMING4 0x2330 +#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_N 0x2331 +#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332 +#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_M 0x2333 +#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334 +#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP2_DP_SEC_TIMESTAMP 0x2335 +#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP2_DP_SEC_PACKET_CNTL 0x2336 +#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSE_RATE_CNTL 0x2337 +#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSE_RATE_UPDATE 0x2339 +#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT0 0x233a +#define mmDP2_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT1 0x233b +#define mmDP2_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT2 0x233c +#define mmDP2_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT_UPDATE 0x233d +#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP2_DP_MSE_LINK_TIMING 0x233e +#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP2_DP_MSE_MISC_CNTL 0x233f +#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 +#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 +#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT0_STATUS 0x2347 +#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT1_STATUS 0x2348 +#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSE_SAT2_STATUS 0x2349 +#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c +#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d +#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e +#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f +#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP2_DP_MSO_CNTL 0x2350 +#define mmDP2_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSO_CNTL1 0x2351 +#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP2_DP_DSC_CNTL 0x2352 +#define mmDP2_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL2 0x2353 +#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL3 0x2354 +#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL4 0x2355 +#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL5 0x2356 +#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL6 0x2357 +#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP2_DP_SEC_CNTL7 0x2358 +#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP2_DP_DB_CNTL 0x2359 +#define mmDP2_DP_DB_CNTL_BASE_IDX 2 +#define mmDP2_DP_MSA_VBID_MISC 0x235a +#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2 +#define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b +#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c +#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmDP2_DP_ALPM_CNTL 0x235d +#define mmDP2_DP_ALPM_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dispdec +// base address: 0xc00 +#define mmDIG3_DIG_FE_CNTL 0x2368 +#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369 +#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a +#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG3_DIG_CLOCK_PATTERN 0x236b +#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG3_DIG_TEST_PATTERN 0x236c +#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d +#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG3_DIG_FIFO_STATUS 0x236e +#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x236f +#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2370 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define mmDIG3_HDMI_CONTROL 0x2371 +#define mmDIG3_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_STATUS 0x2372 +#define mmDIG3_HDMI_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373 +#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374 +#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375 +#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376 +#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377 +#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379 +#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG3_HDMI_GC 0x237b +#define mmDIG3_HDMI_GC_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_0 0x237d +#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_1 0x237e +#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_2 0x237f +#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_3 0x2380 +#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC1_4 0x2381 +#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_0 0x2382 +#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_1 0x2383 +#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_2 0x2384 +#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG3_AFMT_ISRC2_3 0x2385 +#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG3_HDMI_DB_CONTROL 0x2388 +#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG3_DME_CONTROL 0x2389 +#define mmDIG3_DME_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_MPEG_INFO0 0x238a +#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG3_AFMT_MPEG_INFO1 0x238b +#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_HDR 0x238c +#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_0 0x238d +#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_1 0x238e +#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_2 0x238f +#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_3 0x2390 +#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_4 0x2391 +#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_5 0x2392 +#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_6 0x2393 +#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG3_AFMT_GENERIC_7 0x2394 +#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_32_0 0x2396 +#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_32_1 0x2397 +#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_44_0 0x2398 +#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_44_1 0x2399 +#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_48_0 0x239a +#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_48_1 0x239b +#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_STATUS_0 0x239c +#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG3_HDMI_ACR_STATUS_1 0x239d +#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_INFO0 0x239e +#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_INFO1 0x239f +#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG3_AFMT_60958_0 0x23a0 +#define mmDIG3_AFMT_60958_0_BASE_IDX 2 +#define mmDIG3_AFMT_60958_1 0x23a1 +#define mmDIG3_AFMT_60958_1_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2 +#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3 +#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4 +#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5 +#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6 +#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG3_AFMT_60958_2 0x23a7 +#define mmDIG3_AFMT_60958_2_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8 +#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG3_AFMT_STATUS 0x23a9 +#define mmDIG3_AFMT_STATUS_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa +#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab +#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac +#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad +#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG3_DIG_BE_CNTL 0x23af +#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_BE_EN_CNTL 0x23b0 +#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CNTL 0x23d3 +#define mmDIG3_TMDS_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CONTROL_CHAR 0x23d4 +#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5 +#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6 +#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8 +#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG3_TMDS_CTL_BITS 0x23da +#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db +#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23dc +#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd +#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de +#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG3_DIG_VERSION 0x23e0 +#define mmDIG3_DIG_VERSION_BASE_IDX 2 +#define mmDIG3_DIG_LANE_ENABLE 0x23e1 +#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG3_AFMT_CNTL 0x23e6 +#define mmDIG3_AFMT_CNTL_BASE_IDX 2 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7 +#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x23f6 +#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define mmDIG3_FORCE_DIG_DISABLE 0x23f7 +#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp3_dispdec +// base address: 0xc00 +#define mmDP3_DP_LINK_CNTL 0x2408 +#define mmDP3_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP3_DP_PIXEL_FORMAT 0x2409 +#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP3_DP_MSA_COLORIMETRY 0x240a +#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP3_DP_CONFIG 0x240b +#define mmDP3_DP_CONFIG_BASE_IDX 2 +#define mmDP3_DP_VID_STREAM_CNTL 0x240c +#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP3_DP_STEER_FIFO 0x240d +#define mmDP3_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP3_DP_MSA_MISC 0x240e +#define mmDP3_DP_MSA_MISC_BASE_IDX 2 +#define mmDP3_DP_VID_TIMING 0x2410 +#define mmDP3_DP_VID_TIMING_BASE_IDX 2 +#define mmDP3_DP_VID_N 0x2411 +#define mmDP3_DP_VID_N_BASE_IDX 2 +#define mmDP3_DP_VID_M 0x2412 +#define mmDP3_DP_VID_M_BASE_IDX 2 +#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413 +#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414 +#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP3_DP_VID_MSA_VBID 0x2415 +#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416 +#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CNTL 0x2417 +#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 +#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM0 0x2419 +#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM1 0x241a +#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP3_DP_DPHY_SYM2 0x241b +#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c +#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d +#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e +#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_EN 0x241f +#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_CNTL 0x2420 +#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_RESULT 0x2421 +#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422 +#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423 +#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424 +#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 +#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL 0x242b +#define mmDP3_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL1 0x242c +#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING1 0x242d +#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING2 0x242e +#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING3 0x242f +#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP3_DP_SEC_FRAMING4 0x2430 +#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_N 0x2431 +#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432 +#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_M 0x2433 +#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434 +#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP3_DP_SEC_TIMESTAMP 0x2435 +#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP3_DP_SEC_PACKET_CNTL 0x2436 +#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSE_RATE_CNTL 0x2437 +#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSE_RATE_UPDATE 0x2439 +#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT0 0x243a +#define mmDP3_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT1 0x243b +#define mmDP3_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT2 0x243c +#define mmDP3_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT_UPDATE 0x243d +#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP3_DP_MSE_LINK_TIMING 0x243e +#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP3_DP_MSE_MISC_CNTL 0x243f +#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 +#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 +#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT0_STATUS 0x2447 +#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT1_STATUS 0x2448 +#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSE_SAT2_STATUS 0x2449 +#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c +#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d +#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e +#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f +#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP3_DP_MSO_CNTL 0x2450 +#define mmDP3_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSO_CNTL1 0x2451 +#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP3_DP_DSC_CNTL 0x2452 +#define mmDP3_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL2 0x2453 +#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL3 0x2454 +#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL4 0x2455 +#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL5 0x2456 +#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL6 0x2457 +#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP3_DP_SEC_CNTL7 0x2458 +#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP3_DP_DB_CNTL 0x2459 +#define mmDP3_DP_DB_CNTL_BASE_IDX 2 +#define mmDP3_DP_MSA_VBID_MISC 0x245a +#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2 +#define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b +#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c +#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmDP3_DP_ALPM_CNTL 0x245d +#define mmDP3_DP_ALPM_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_dispdec +// base address: 0x1000 +#define mmDIG4_DIG_FE_CNTL 0x2468 +#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469 +#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a +#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define mmDIG4_DIG_CLOCK_PATTERN 0x246b +#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define mmDIG4_DIG_TEST_PATTERN 0x246c +#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2 +#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d +#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define mmDIG4_DIG_FIFO_STATUS 0x246e +#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x246f +#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x2470 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define mmDIG4_HDMI_CONTROL 0x2471 +#define mmDIG4_HDMI_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_STATUS 0x2472 +#define mmDIG4_HDMI_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473 +#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474 +#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475 +#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476 +#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477 +#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479 +#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDIG4_HDMI_GC 0x247b +#define mmDIG4_HDMI_GC_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_0 0x247d +#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_1 0x247e +#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_2 0x247f +#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_3 0x2480 +#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC1_4 0x2481 +#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_0 0x2482 +#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_1 0x2483 +#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_2 0x2484 +#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2 +#define mmDIG4_AFMT_ISRC2_3 0x2485 +#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define mmDIG4_HDMI_DB_CONTROL 0x2488 +#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2 +#define mmDIG4_DME_CONTROL 0x2489 +#define mmDIG4_DME_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_MPEG_INFO0 0x248a +#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2 +#define mmDIG4_AFMT_MPEG_INFO1 0x248b +#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_HDR 0x248c +#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_0 0x248d +#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_1 0x248e +#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_2 0x248f +#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_3 0x2490 +#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_4 0x2491 +#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_5 0x2492 +#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_6 0x2493 +#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2 +#define mmDIG4_AFMT_GENERIC_7 0x2494 +#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_32_0 0x2496 +#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_32_1 0x2497 +#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_44_0 0x2498 +#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_44_1 0x2499 +#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_48_0 0x249a +#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_48_1 0x249b +#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_STATUS_0 0x249c +#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define mmDIG4_HDMI_ACR_STATUS_1 0x249d +#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_INFO0 0x249e +#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_INFO1 0x249f +#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2 +#define mmDIG4_AFMT_60958_0 0x24a0 +#define mmDIG4_AFMT_60958_0_BASE_IDX 2 +#define mmDIG4_AFMT_60958_1 0x24a1 +#define mmDIG4_AFMT_60958_1_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2 +#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3 +#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4 +#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5 +#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2 +#define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6 +#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2 +#define mmDIG4_AFMT_60958_2 0x24a7 +#define mmDIG4_AFMT_60958_2_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8 +#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 +#define mmDIG4_AFMT_STATUS 0x24a9 +#define mmDIG4_AFMT_STATUS_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa +#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab +#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 +#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac +#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad +#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 +#define mmDIG4_DIG_BE_CNTL 0x24af +#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_BE_EN_CNTL 0x24b0 +#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CNTL 0x24d3 +#define mmDIG4_TMDS_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CONTROL_CHAR 0x24d4 +#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5 +#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6 +#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8 +#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define mmDIG4_TMDS_CTL_BITS 0x24da +#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2 +#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db +#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24dc +#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd +#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de +#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define mmDIG4_DIG_VERSION 0x24e0 +#define mmDIG4_DIG_VERSION_BASE_IDX 2 +#define mmDIG4_DIG_LANE_ENABLE 0x24e1 +#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2 +#define mmDIG4_AFMT_CNTL 0x24e6 +#define mmDIG4_AFMT_CNTL_BASE_IDX 2 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7 +#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x24f6 +#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define mmDIG4_FORCE_DIG_DISABLE 0x24f7 +#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp4_dispdec +// base address: 0x1000 +#define mmDP4_DP_LINK_CNTL 0x2508 +#define mmDP4_DP_LINK_CNTL_BASE_IDX 2 +#define mmDP4_DP_PIXEL_FORMAT 0x2509 +#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2 +#define mmDP4_DP_MSA_COLORIMETRY 0x250a +#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define mmDP4_DP_CONFIG 0x250b +#define mmDP4_DP_CONFIG_BASE_IDX 2 +#define mmDP4_DP_VID_STREAM_CNTL 0x250c +#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define mmDP4_DP_STEER_FIFO 0x250d +#define mmDP4_DP_STEER_FIFO_BASE_IDX 2 +#define mmDP4_DP_MSA_MISC 0x250e +#define mmDP4_DP_MSA_MISC_BASE_IDX 2 +#define mmDP4_DP_VID_TIMING 0x2510 +#define mmDP4_DP_VID_TIMING_BASE_IDX 2 +#define mmDP4_DP_VID_N 0x2511 +#define mmDP4_DP_VID_N_BASE_IDX 2 +#define mmDP4_DP_VID_M 0x2512 +#define mmDP4_DP_VID_M_BASE_IDX 2 +#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513 +#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514 +#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define mmDP4_DP_VID_MSA_VBID 0x2515 +#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2 +#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516 +#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CNTL 0x2517 +#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 +#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM0 0x2519 +#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM1 0x251a +#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2 +#define mmDP4_DP_DPHY_SYM2 0x251b +#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2 +#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c +#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d +#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e +#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_EN 0x251f +#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_CNTL 0x2520 +#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_RESULT 0x2521 +#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522 +#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523 +#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 +#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524 +#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 +#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL 0x252b +#define mmDP4_DP_SEC_CNTL_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL1 0x252c +#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING1 0x252d +#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING2 0x252e +#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING3 0x252f +#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2 +#define mmDP4_DP_SEC_FRAMING4 0x2530 +#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_N 0x2531 +#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532 +#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_M 0x2533 +#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2 +#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534 +#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define mmDP4_DP_SEC_TIMESTAMP 0x2535 +#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define mmDP4_DP_SEC_PACKET_CNTL 0x2536 +#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSE_RATE_CNTL 0x2537 +#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSE_RATE_UPDATE 0x2539 +#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT0 0x253a +#define mmDP4_DP_MSE_SAT0_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT1 0x253b +#define mmDP4_DP_MSE_SAT1_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT2 0x253c +#define mmDP4_DP_MSE_SAT2_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT_UPDATE 0x253d +#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define mmDP4_DP_MSE_LINK_TIMING 0x253e +#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define mmDP4_DP_MSE_MISC_CNTL 0x253f +#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 +#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 +#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT0_STATUS 0x2547 +#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT1_STATUS 0x2548 +#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSE_SAT2_STATUS 0x2549 +#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c +#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d +#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e +#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f +#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define mmDP4_DP_MSO_CNTL 0x2550 +#define mmDP4_DP_MSO_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSO_CNTL1 0x2551 +#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2 +#define mmDP4_DP_DSC_CNTL 0x2552 +#define mmDP4_DP_DSC_CNTL_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL2 0x2553 +#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL3 0x2554 +#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL4 0x2555 +#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL5 0x2556 +#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL6 0x2557 +#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2 +#define mmDP4_DP_SEC_CNTL7 0x2558 +#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2 +#define mmDP4_DP_DB_CNTL 0x2559 +#define mmDP4_DP_DB_CNTL_BASE_IDX 2 +#define mmDP4_DP_MSA_VBID_MISC 0x255a +#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2 +#define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b +#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c +#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2 +#define mmDP4_DP_ALPM_CNTL 0x255d +#define mmDP4_DP_ALPM_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_dispdec +// base address: 0x0 +#define mmDC_GENERICA 0x2868 +#define mmDC_GENERICA_BASE_IDX 2 +#define mmDC_GENERICB 0x2869 +#define mmDC_GENERICB_BASE_IDX 2 +#define mmDC_REF_CLK_CNTL 0x286b +#define mmDC_REF_CLK_CNTL_BASE_IDX 2 +#define mmUNIPHYA_LINK_CNTL 0x286d +#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYB_LINK_CNTL 0x286f +#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYC_LINK_CNTL 0x2871 +#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 +#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYD_LINK_CNTL 0x2873 +#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 +#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmUNIPHYE_LINK_CNTL 0x2875 +#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2 +#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 +#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define mmDCIO_WRCMD_DELAY 0x287e +#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 +#define mmDC_PINSTRAPS 0x2880 +#define mmDC_PINSTRAPS_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_CNTL 0x2883 +#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_STATE 0x2884 +#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_REF_DIV 0x2885 +#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_DELAY1 0x2886 +#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 +#define mmLVTMA_PWRSEQ_DELAY2 0x2887 +#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 +#define mmBL_PWM_CNTL 0x2888 +#define mmBL_PWM_CNTL_BASE_IDX 2 +#define mmBL_PWM_CNTL2 0x2889 +#define mmBL_PWM_CNTL2_BASE_IDX 2 +#define mmBL_PWM_PERIOD_CNTL 0x288a +#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 +#define mmBL_PWM_GRP1_REG_LOCK 0x288b +#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 +#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define mmDCIO_CLOCK_CNTL 0x2895 +#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 +#define mmDCIO_SOFT_RESET 0x289e +#define mmDCIO_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +// base address: 0x0 +#define mmDC_GPIO_GENERIC_MASK 0x28c8 +#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_A 0x28c9 +#define mmDC_GPIO_GENERIC_A_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_EN 0x28ca +#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 +#define mmDC_GPIO_GENERIC_Y 0x28cb +#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC1_MASK 0x28d0 +#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC1_A 0x28d1 +#define mmDC_GPIO_DDC1_A_BASE_IDX 2 +#define mmDC_GPIO_DDC1_EN 0x28d2 +#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC1_Y 0x28d3 +#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC2_MASK 0x28d4 +#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC2_A 0x28d5 +#define mmDC_GPIO_DDC2_A_BASE_IDX 2 +#define mmDC_GPIO_DDC2_EN 0x28d6 +#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC2_Y 0x28d7 +#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC3_MASK 0x28d8 +#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC3_A 0x28d9 +#define mmDC_GPIO_DDC3_A_BASE_IDX 2 +#define mmDC_GPIO_DDC3_EN 0x28da +#define mmDC_GPIO_DDC3_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC3_Y 0x28db +#define mmDC_GPIO_DDC3_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC4_MASK 0x28dc +#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC4_A 0x28dd +#define mmDC_GPIO_DDC4_A_BASE_IDX 2 +#define mmDC_GPIO_DDC4_EN 0x28de +#define mmDC_GPIO_DDC4_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC4_Y 0x28df +#define mmDC_GPIO_DDC4_Y_BASE_IDX 2 +#define mmDC_GPIO_DDC5_MASK 0x28e0 +#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDC5_A 0x28e1 +#define mmDC_GPIO_DDC5_A_BASE_IDX 2 +#define mmDC_GPIO_DDC5_EN 0x28e2 +#define mmDC_GPIO_DDC5_EN_BASE_IDX 2 +#define mmDC_GPIO_DDC5_Y 0x28e3 +#define mmDC_GPIO_DDC5_Y_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_MASK 0x28e8 +#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_A 0x28e9 +#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_EN 0x28ea +#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define mmDC_GPIO_DDCVGA_Y 0x28eb +#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define mmDC_GPIO_GENLK_MASK 0x28f0 +#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 +#define mmDC_GPIO_GENLK_A 0x28f1 +#define mmDC_GPIO_GENLK_A_BASE_IDX 2 +#define mmDC_GPIO_GENLK_EN 0x28f2 +#define mmDC_GPIO_GENLK_EN_BASE_IDX 2 +#define mmDC_GPIO_GENLK_Y 0x28f3 +#define mmDC_GPIO_GENLK_Y_BASE_IDX 2 +#define mmDC_GPIO_HPD_MASK 0x28f4 +#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 +#define mmDC_GPIO_HPD_A 0x28f5 +#define mmDC_GPIO_HPD_A_BASE_IDX 2 +#define mmDC_GPIO_HPD_EN 0x28f6 +#define mmDC_GPIO_HPD_EN_BASE_IDX 2 +#define mmDC_GPIO_HPD_Y 0x28f7 +#define mmDC_GPIO_HPD_Y_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_MASK 0x28f8 +#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_A 0x28f9 +#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_EN 0x28fa +#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 +#define mmDC_GPIO_PWRSEQ_Y 0x28fb +#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 +#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc +#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd +#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 +#define mmPHY_AUX_CNTL 0x28ff +#define mmPHY_AUX_CNTL_BASE_IDX 2 +#define mmDC_GPIO_TX12_EN 0x2915 +#define mmDC_GPIO_TX12_EN_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_0 0x2916 +#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_1 0x2917 +#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_2 0x2918 +#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 +#define mmDC_GPIO_RXEN 0x2919 +#define mmDC_GPIO_RXEN_BASE_IDX 2 +#define mmDC_GPIO_PULLUPEN 0x291a +#define mmDC_GPIO_PULLUPEN_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_3 0x291b +#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_4 0x291c +#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2 +#define mmDC_GPIO_AUX_CTRL_5 0x291d +#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2 +#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e +#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +// base address: 0x0 +#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000 +#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 +#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 +#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +// base address: 0x0 +#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005 +#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 +#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006 +#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +// base address: 0x0 +#define mmDSCC0_DSCC_CONFIG0 0x300a +#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2 +#define mmDSCC0_DSCC_CONFIG1 0x300b +#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2 +#define mmDSCC0_DSCC_STATUS 0x300c +#define mmDSCC0_DSCC_STATUS_BASE_IDX 2 +#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d +#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e +#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f +#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010 +#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011 +#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012 +#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013 +#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014 +#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015 +#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016 +#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017 +#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018 +#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019 +#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a +#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b +#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c +#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d +#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e +#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f +#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020 +#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021 +#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022 +#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023 +#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024 +#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 +#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 +#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 +#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 +#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 +#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a +#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b +#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c +#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d +#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e +#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f +#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 +#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 +#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 +#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a +#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc140 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 +#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x3052 +#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_CNTL 0x3053 +#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_CNTL2 0x3054 +#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 +#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 +#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_HI 0x3057 +#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON19_PERFMON_LOW 0x3058 +#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +// base address: 0x170 +#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c +#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 +#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d +#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +// base address: 0x170 +#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061 +#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 +#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062 +#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +// base address: 0x170 +#define mmDSCC1_DSCC_CONFIG0 0x3066 +#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2 +#define mmDSCC1_DSCC_CONFIG1 0x3067 +#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2 +#define mmDSCC1_DSCC_STATUS 0x3068 +#define mmDSCC1_DSCC_STATUS_BASE_IDX 2 +#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 +#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a +#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b +#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c +#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d +#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e +#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f +#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070 +#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071 +#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072 +#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073 +#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074 +#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075 +#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076 +#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077 +#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078 +#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079 +#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a +#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b +#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c +#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d +#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e +#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f +#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080 +#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 +#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 +#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 +#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 +#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 +#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 +#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 +#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 +#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 +#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a +#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b +#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c +#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d +#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 +#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 +#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc2b0 +#define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac +#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad +#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON20_PERFCOUNTER_STATE 0x30ae +#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON20_PERFMON_CNTL 0x30af +#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON20_PERFMON_CNTL2 0x30b0 +#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 +#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 +#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON20_PERFMON_HI 0x30b3 +#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON20_PERFMON_LOW 0x30b4 +#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +// base address: 0x2e0 +#define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8 +#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 +#define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 +#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +// base address: 0x2e0 +#define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd +#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 +#define mmDSCCIF2_DSCCIF_CONFIG1 0x30be +#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +// base address: 0x2e0 +#define mmDSCC2_DSCC_CONFIG0 0x30c2 +#define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2 +#define mmDSCC2_DSCC_CONFIG1 0x30c3 +#define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2 +#define mmDSCC2_DSCC_STATUS 0x30c4 +#define mmDSCC2_DSCC_STATUS_BASE_IDX 2 +#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 +#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6 +#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7 +#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8 +#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9 +#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca +#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb +#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc +#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd +#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce +#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf +#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0 +#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1 +#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2 +#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3 +#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4 +#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5 +#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6 +#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7 +#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8 +#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9 +#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG20 0x30da +#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG21 0x30db +#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc +#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd +#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de +#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df +#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 +#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 +#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 +#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 +#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 +#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 +#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 +#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 +#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 +#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 +#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea +#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb +#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec +#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed +#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 +#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc420 +#define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 +#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 +#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON21_PERFCOUNTER_STATE 0x310a +#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON21_PERFMON_CNTL 0x310b +#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON21_PERFMON_CNTL2 0x310c +#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d +#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e +#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON21_PERFMON_HI 0x310f +#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON21_PERFMON_LOW 0x3110 +#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec +// base address: 0x450 +#define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114 +#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 +#define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 +#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec +// base address: 0x450 +#define mmDSCCIF3_DSCCIF_CONFIG0 0x3119 +#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 +#define mmDSCCIF3_DSCCIF_CONFIG1 0x311a +#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec +// base address: 0x450 +#define mmDSCC3_DSCC_CONFIG0 0x311e +#define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2 +#define mmDSCC3_DSCC_CONFIG1 0x311f +#define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2 +#define mmDSCC3_DSCC_STATUS 0x3120 +#define mmDSCC3_DSCC_STATUS_BASE_IDX 2 +#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 +#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG0 0x3122 +#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG1 0x3123 +#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG2 0x3124 +#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG3 0x3125 +#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG4 0x3126 +#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG5 0x3127 +#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG6 0x3128 +#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG7 0x3129 +#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG8 0x312a +#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG9 0x312b +#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG10 0x312c +#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG11 0x312d +#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG12 0x312e +#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG13 0x312f +#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG14 0x3130 +#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG15 0x3131 +#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG16 0x3132 +#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG17 0x3133 +#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG18 0x3134 +#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG19 0x3135 +#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG20 0x3136 +#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG21 0x3137 +#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define mmDSCC3_DSCC_PPS_CONFIG22 0x3138 +#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 +#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a +#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b +#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c +#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d +#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e +#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f +#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 +#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 +#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 +#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 +#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 +#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 +#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 +#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 +#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 +#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 +#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e +#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + +// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc590 +#define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x3164 +#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x3165 +#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON22_PERFCOUNTER_STATE 0x3166 +#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON22_PERFMON_CNTL 0x3167 +#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON22_PERFMON_CNTL2 0x3168 +#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x3169 +#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x316a +#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON22_PERFMON_HI 0x316b +#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON22_PERFMON_LOW 0x316c +#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec +// base address: 0x5c0 +#define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170 +#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2 +#define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171 +#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec +// base address: 0x5c0 +#define mmDSCCIF4_DSCCIF_CONFIG0 0x3175 +#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2 +#define mmDSCCIF4_DSCCIF_CONFIG1 0x3176 +#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec +// base address: 0x5c0 +#define mmDSCC4_DSCC_CONFIG0 0x317a +#define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2 +#define mmDSCC4_DSCC_CONFIG1 0x317b +#define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2 +#define mmDSCC4_DSCC_STATUS 0x317c +#define mmDSCC4_DSCC_STATUS_BASE_IDX 2 +#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d +#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG0 0x317e +#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG1 0x317f +#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG2 0x3180 +#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG3 0x3181 +#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG4 0x3182 +#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG5 0x3183 +#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG6 0x3184 +#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG7 0x3185 +#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG8 0x3186 +#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG9 0x3187 +#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG10 0x3188 +#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG11 0x3189 +#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG12 0x318a +#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG13 0x318b +#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG14 0x318c +#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG15 0x318d +#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG16 0x318e +#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG17 0x318f +#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG18 0x3190 +#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG19 0x3191 +#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG20 0x3192 +#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG21 0x3193 +#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define mmDSCC4_DSCC_PPS_CONFIG22 0x3194 +#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195 +#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196 +#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197 +#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198 +#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199 +#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a +#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b +#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c +#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d +#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e +#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f +#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0 +#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1 +#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2 +#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3 +#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4 +#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5 +#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE 0x31aa +#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + +// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc700 +#define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x31c0 +#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x31c1 +#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON23_PERFCOUNTER_STATE 0x31c2 +#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON23_PERFMON_CNTL 0x31c3 +#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON23_PERFMON_CNTL2 0x31c4 +#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x31c5 +#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x31c6 +#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON23_PERFMON_HI 0x31c7 +#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON23_PERFMON_LOW 0x31c8 +#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec +// base address: 0x730 +#define mmDSC_TOP5_DSC_TOP_CONTROL 0x31cc +#define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX 2 +#define mmDSC_TOP5_DSC_DEBUG_CONTROL 0x31cd +#define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec +// base address: 0x730 +#define mmDSCCIF5_DSCCIF_CONFIG0 0x31d1 +#define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX 2 +#define mmDSCCIF5_DSCCIF_CONFIG1 0x31d2 +#define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec +// base address: 0x730 +#define mmDSCC5_DSCC_CONFIG0 0x31d6 +#define mmDSCC5_DSCC_CONFIG0_BASE_IDX 2 +#define mmDSCC5_DSCC_CONFIG1 0x31d7 +#define mmDSCC5_DSCC_CONFIG1_BASE_IDX 2 +#define mmDSCC5_DSCC_STATUS 0x31d8 +#define mmDSCC5_DSCC_STATUS_BASE_IDX 2 +#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS 0x31d9 +#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG0 0x31da +#define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG1 0x31db +#define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG2 0x31dc +#define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG3 0x31dd +#define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG4 0x31de +#define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG5 0x31df +#define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG6 0x31e0 +#define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG7 0x31e1 +#define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG8 0x31e2 +#define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG9 0x31e3 +#define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG10 0x31e4 +#define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG11 0x31e5 +#define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG12 0x31e6 +#define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG13 0x31e7 +#define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG14 0x31e8 +#define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG15 0x31e9 +#define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG16 0x31ea +#define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG17 0x31eb +#define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG18 0x31ec +#define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG19 0x31ed +#define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG20 0x31ee +#define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG21 0x31ef +#define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define mmDSCC5_DSCC_PPS_CONFIG22 0x31f0 +#define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define mmDSCC5_DSCC_MEM_POWER_CONTROL 0x31f1 +#define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 +#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER 0x31f2 +#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER 0x31f3 +#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER 0x31f4 +#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER 0x31f5 +#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER 0x31f6 +#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER 0x31f7 +#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define mmDSCC5_DSCC_MAX_ABS_ERROR0 0x31f8 +#define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define mmDSCC5_DSCC_MAX_ABS_ERROR1 0x31f9 +#define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x31fa +#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x31fb +#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31fc +#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31fd +#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31fe +#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31ff +#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3200 +#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201 +#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 +#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE 0x3206 +#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc870 +#define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x321c +#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2 +#define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x321d +#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON24_PERFCOUNTER_STATE 0x321e +#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2 +#define mmDC_PERFMON24_PERFMON_CNTL 0x321f +#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2 +#define mmDC_PERFMON24_PERFMON_CNTL2 0x3220 +#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2 +#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x3221 +#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x3222 +#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define mmDC_PERFMON24_PERFMON_HI 0x3223 +#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2 +#define mmDC_PERFMON24_PERFMON_LOW 0x3224 +#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +// base address: 0x0 +#define mmDMCUB_REGION0_OFFSET 0x3238 +#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION0_OFFSET_HIGH 0x3239 +#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION1_OFFSET 0x323a +#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION1_OFFSET_HIGH 0x323b +#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION2_OFFSET 0x323c +#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION2_OFFSET_HIGH 0x323d +#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION4_OFFSET 0x3240 +#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION4_OFFSET_HIGH 0x3241 +#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION5_OFFSET 0x3242 +#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION5_OFFSET_HIGH 0x3243 +#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION6_OFFSET 0x3244 +#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION6_OFFSET_HIGH 0x3245 +#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION7_OFFSET 0x3246 +#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION7_OFFSET_HIGH 0x3247 +#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION0_TOP_ADDRESS 0x3248 +#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION1_TOP_ADDRESS 0x3249 +#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION2_TOP_ADDRESS 0x324a +#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION4_TOP_ADDRESS 0x324b +#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION5_TOP_ADDRESS 0x324c +#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION6_TOP_ADDRESS 0x324d +#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION7_TOP_ADDRESS 0x324e +#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x324f +#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x3250 +#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x3251 +#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x3252 +#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x3253 +#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x3254 +#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x3255 +#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x3256 +#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x3257 +#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x3258 +#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x3259 +#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x325a +#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x325b +#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x325c +#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x325d +#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x325e +#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 +#define mmDMCUB_REGION3_CW0_OFFSET 0x325f +#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x3260 +#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW1_OFFSET 0x3261 +#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x3262 +#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW2_OFFSET 0x3263 +#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x3264 +#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW3_OFFSET 0x3265 +#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x3266 +#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW4_OFFSET 0x3267 +#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x3268 +#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW5_OFFSET 0x3269 +#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x326a +#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW6_OFFSET 0x326b +#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x326c +#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_REGION3_CW7_OFFSET 0x326d +#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 +#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x326e +#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 +#define mmDMCUB_INTERRUPT_ENABLE 0x326f +#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 +#define mmDMCUB_INTERRUPT_ACK 0x3270 +#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2 +#define mmDMCUB_INTERRUPT_STATUS 0x3271 +#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDMCUB_INTERRUPT_TYPE 0x3272 +#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2 +#define mmDMCUB_EXT_INTERRUPT_STATUS 0x3273 +#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 +#define mmDMCUB_EXT_INTERRUPT_CTXID 0x3274 +#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 +#define mmDMCUB_EXT_INTERRUPT_ACK 0x3275 +#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 +#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x3276 +#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 +#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x3277 +#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 +#define mmDMCUB_SEC_CNTL 0x3278 +#define mmDMCUB_SEC_CNTL_BASE_IDX 2 +#define mmDMCUB_MEM_CNTL 0x3279 +#define mmDMCUB_MEM_CNTL_BASE_IDX 2 +#define mmDMCUB_INBOX0_BASE_ADDRESS 0x327a +#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_INBOX0_SIZE 0x327b +#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2 +#define mmDMCUB_INBOX0_WPTR 0x327c +#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2 +#define mmDMCUB_INBOX0_RPTR 0x327d +#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2 +#define mmDMCUB_INBOX1_BASE_ADDRESS 0x327e +#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_INBOX1_SIZE 0x327f +#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2 +#define mmDMCUB_INBOX1_WPTR 0x3280 +#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2 +#define mmDMCUB_INBOX1_RPTR 0x3281 +#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2 +#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x3282 +#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_OUTBOX0_SIZE 0x3283 +#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2 +#define mmDMCUB_OUTBOX0_WPTR 0x3284 +#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2 +#define mmDMCUB_OUTBOX0_RPTR 0x3285 +#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2 +#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x3286 +#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 +#define mmDMCUB_OUTBOX1_SIZE 0x3287 +#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2 +#define mmDMCUB_OUTBOX1_WPTR 0x3288 +#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2 +#define mmDMCUB_OUTBOX1_RPTR 0x3289 +#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2 +#define mmDMCUB_TIMER_TRIGGER0 0x328a +#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2 +#define mmDMCUB_TIMER_TRIGGER1 0x328b +#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2 +#define mmDMCUB_TIMER_WINDOW 0x328c +#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2 +#define mmDMCUB_SCRATCH0 0x328d +#define mmDMCUB_SCRATCH0_BASE_IDX 2 +#define mmDMCUB_SCRATCH1 0x328e +#define mmDMCUB_SCRATCH1_BASE_IDX 2 +#define mmDMCUB_SCRATCH2 0x328f +#define mmDMCUB_SCRATCH2_BASE_IDX 2 +#define mmDMCUB_SCRATCH3 0x3290 +#define mmDMCUB_SCRATCH3_BASE_IDX 2 +#define mmDMCUB_SCRATCH4 0x3291 +#define mmDMCUB_SCRATCH4_BASE_IDX 2 +#define mmDMCUB_SCRATCH5 0x3292 +#define mmDMCUB_SCRATCH5_BASE_IDX 2 +#define mmDMCUB_SCRATCH6 0x3293 +#define mmDMCUB_SCRATCH6_BASE_IDX 2 +#define mmDMCUB_SCRATCH7 0x3294 +#define mmDMCUB_SCRATCH7_BASE_IDX 2 +#define mmDMCUB_SCRATCH8 0x3295 +#define mmDMCUB_SCRATCH8_BASE_IDX 2 +#define mmDMCUB_SCRATCH9 0x3296 +#define mmDMCUB_SCRATCH9_BASE_IDX 2 +#define mmDMCUB_SCRATCH10 0x3297 +#define mmDMCUB_SCRATCH10_BASE_IDX 2 +#define mmDMCUB_SCRATCH11 0x3298 +#define mmDMCUB_SCRATCH11_BASE_IDX 2 +#define mmDMCUB_SCRATCH12 0x3299 +#define mmDMCUB_SCRATCH12_BASE_IDX 2 +#define mmDMCUB_SCRATCH13 0x329a +#define mmDMCUB_SCRATCH13_BASE_IDX 2 +#define mmDMCUB_SCRATCH14 0x329b +#define mmDMCUB_SCRATCH14_BASE_IDX 2 +#define mmDMCUB_SCRATCH15 0x329c +#define mmDMCUB_SCRATCH15_BASE_IDX 2 +#define mmDMCUB_CNTL 0x32a0 +#define mmDMCUB_CNTL_BASE_IDX 2 +#define mmDMCUB_GPINT_DATAIN0 0x32a1 +#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2 +#define mmDMCUB_GPINT_DATAIN1 0x32a2 +#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2 +#define mmDMCUB_GPINT_DATAOUT 0x32a3 +#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2 +#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x32a4 +#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 +#define mmDMCUB_LS_WAKE_INT_ENABLE 0x32a5 +#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 +#define mmDMCUB_MEM_PWR_CNTL 0x32a6 +#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2 +#define mmDMCUB_TIMER_CURRENT 0x32a7 +#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2 +#define mmDMCUB_PROC_ID 0x32a9 +#define mmDMCUB_PROC_ID_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec +// base address: 0xc6b8 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x3460 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x3461 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x3462 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x3463 +#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x3464 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x3465 +#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x3466 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x3467 +#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x3468 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x3469 +#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x346a +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x346b +#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x346c +#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x346d +#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x346e +#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x346f +#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x3470 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x3471 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x3472 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x3473 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x3474 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x3475 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x3476 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x3477 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x3478 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x3479 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x347a +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x347b +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x347c +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x347d +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x347e +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x347f +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x3480 +#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x3481 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x3482 +#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x3483 +#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x3484 +#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x3485 +#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x3486 +#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x3487 +#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x3489 +#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x348a +#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x348b +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH 0x348c +#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x348d +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH 0x348e +#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x348f +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH 0x3490 +#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x3491 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH 0x3492 +#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION 0x3493 +#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION 0x3494 +#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION 0x3495 +#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION 0x3496 +#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 + + +// addressBlock: dce_dc_dchvm_hvm_dispdec +// base address: 0x0 +#define mmDCHVM_CTRL0 0x016b +#define mmDCHVM_CTRL0_BASE_IDX 3 +#define mmDCHVM_CTRL1 0x016c +#define mmDCHVM_CTRL1_BASE_IDX 3 +#define mmDCHVM_CLK_CTRL 0x016d +#define mmDCHVM_CLK_CTRL_BASE_IDX 3 +#define mmDCHVM_MEM_CTRL 0x016e +#define mmDCHVM_MEM_CTRL_BASE_IDX 3 +#define mmDCHVM_RIOMMU_CTRL0 0x016f +#define mmDCHVM_RIOMMU_CTRL0_BASE_IDX 3 +#define mmDCHVM_RIOMMU_STAT0 0x0170 +#define mmDCHVM_RIOMMU_STAT0_BASE_IDX 3 + + +// addressBlock: vga_vgaseqind +// base address: 0x0 +#define ixSEQ00 0x0000 +#define ixSEQ01 0x0001 +#define ixSEQ02 0x0002 +#define ixSEQ03 0x0003 +#define ixSEQ04 0x0004 + + +// addressBlock: vga_vgacrtind +// base address: 0x0 +#define ixCRT00 0x0000 +#define ixCRT01 0x0001 +#define ixCRT02 0x0002 +#define ixCRT03 0x0003 +#define ixCRT04 0x0004 +#define ixCRT05 0x0005 +#define ixCRT06 0x0006 +#define ixCRT07 0x0007 +#define ixCRT08 0x0008 +#define ixCRT09 0x0009 +#define ixCRT0A 0x000a +#define ixCRT0B 0x000b +#define ixCRT0C 0x000c +#define ixCRT0D 0x000d +#define ixCRT0E 0x000e +#define ixCRT0F 0x000f +#define ixCRT10 0x0010 +#define ixCRT11 0x0011 +#define ixCRT12 0x0012 +#define ixCRT13 0x0013 +#define ixCRT14 0x0014 +#define ixCRT15 0x0015 +#define ixCRT16 0x0016 +#define ixCRT17 0x0017 +#define ixCRT18 0x0018 +#define ixCRT1E 0x001e +#define ixCRT1F 0x001f +#define ixCRT22 0x0022 + + +// addressBlock: vga_vgagrphind +// base address: 0x0 +#define ixGRA00 0x0000 +#define ixGRA01 0x0001 +#define ixGRA02 0x0002 +#define ixGRA03 0x0003 +#define ixGRA04 0x0004 +#define ixGRA05 0x0005 +#define ixGRA06 0x0006 +#define ixGRA07 0x0007 +#define ixGRA08 0x0008 + + +// addressBlock: vga_vgaattrind +// base address: 0x0 +#define ixATTR00 0x0000 +#define ixATTR01 0x0001 +#define ixATTR02 0x0002 +#define ixATTR03 0x0003 +#define ixATTR04 0x0004 +#define ixATTR05 0x0005 +#define ixATTR06 0x0006 +#define ixATTR07 0x0007 +#define ixATTR08 0x0008 +#define ixATTR09 0x0009 +#define ixATTR0A 0x000a +#define ixATTR0B 0x000b +#define ixATTR0C 0x000c +#define ixATTR0D 0x000d +#define ixATTR0E 0x000e +#define ixATTR0F 0x000f +#define ixATTR10 0x0010 +#define ixATTR11 0x0011 +#define ixATTR12 0x0012 +#define ixATTR13 0x0013 +#define ixATTR14 0x0014 + + +// addressBlock: azendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e + + +// addressBlock: azendpoint_descriptorind +// base address: 0x0 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000a +#define ixAUDIO_DESCRIPTOR10 0x000b +#define ixAUDIO_DESCRIPTOR11 0x000c +#define ixAUDIO_DESCRIPTOR12 0x000d +#define ixAUDIO_DESCRIPTOR13 0x000e + + +// addressBlock: azendpoint_sinkinfoind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000a +#define ixSINK_DESCRIPTION6 0x000b +#define ixSINK_DESCRIPTION7 0x000c +#define ixSINK_DESCRIPTION8 0x000d +#define ixSINK_DESCRIPTION9 0x000e +#define ixSINK_DESCRIPTION10 0x000f +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 + + +// addressBlock: azf0controller_azinputcrc0resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azinputcrc1resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc0resultind +// base address: 0x0 +#define ixAZALIA_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc1resultind +// base address: 0x0 +#define ixAZALIA_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azinputendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c + + +// addressBlock: azroot_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f + + +// addressBlock: azf0stream0_streamind +// base address: 0x0 +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream1_streamind +// base address: 0x0 +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream2_streamind +// base address: 0x0 +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream3_streamind +// base address: 0x0 +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream4_streamind +// base address: 0x0 +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream5_streamind +// base address: 0x0 +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream6_streamind +// base address: 0x0 +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream7_streamind +// base address: 0x0 +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream8_streamind +// base address: 0x0 +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream9_streamind +// base address: 0x0 +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream10_streamind +// base address: 0x0 +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream11_streamind +// base address: 0x0 +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream12_streamind +// base address: 0x0 +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream13_streamind +// base address: 0x0 +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream14_streamind +// base address: 0x0 +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0stream15_streamind +// base address: 0x0 +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 + + +// addressBlock: azf0endpoint0_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint1_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint2_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint3_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint4_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint5_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint6_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0endpoint7_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e + + +// addressBlock: azf0inputendpoint0_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint1_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint2_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint3_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint4_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint5_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint6_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint7_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h new file mode 100644 index 000000000000..faa0e76e32b4 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h @@ -0,0 +1,56638 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dcn_2_1_0_SH_MASK_HEADER +#define _dcn_2_1_0_SH_MASK_HEADER + + +// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] +//VGA_MEM_WRITE_PAGE_ADDR +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L +//VGA_MEM_READ_PAGE_ADDR +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL +#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L +// addressBlock: dce_dc_mmhubbub_vga_dispdec +//VGA_RENDER_CONTROL +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 +#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001FL +#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L +#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L +#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L +#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L +#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L +#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L +//VGA_SEQUENCER_RESET_CONTROL +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 +#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L +#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L +#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L +#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L +#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L +#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L +#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L +#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L +#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L +#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L +#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L +#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L +#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00FC0000L +//VGA_MODE_CONTROL +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT 0x18 +#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L +#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L +#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L +#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L +#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK 0x01000000L +//VGA_SURFACE_PITCH_SELECT +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L +#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L +//VGA_MEMORY_BASE_ADDRESS +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xFFFFFFFFL +//VGA_DISPBUF1_SURFACE_ADDR +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_DISPBUF2_SURFACE_ADDR +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 +#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01FFFFFFL +//VGA_MEMORY_BASE_ADDRESS_HIGH +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 +#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x0000FFFFL +//VGA_HDP_CONTROL +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 +#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 +#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L +#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L +#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L +#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L +#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L +//VGA_CACHE_CONTROL +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 +#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L +#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L +#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L +#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3F000000L +//D1VGA_CONTROL +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 +#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L +#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L +#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L +//D2VGA_CONTROL +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 +#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L +#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L +#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L +//VGA_STATUS +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 +#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 +#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L +#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L +#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L +#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L +//VGA_INTERRUPT_CONTROL +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 +#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L +#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L +#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L +#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L +//VGA_STATUS_CLEAR +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 +#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L +#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L +#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L +#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L +//VGA_INTERRUPT_STATUS +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 +#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L +#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L +#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L +#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L +//VGA_MAIN_CONTROL +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT 0xc +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f +#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L +#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L +#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000E0L +#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L +#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK 0x0000F000L +#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L +#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L +#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L +#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L +#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L +//VGA_TEST_CONTROL +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 +#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L +#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L +//VGA_QOS_CTRL +#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT 0x0 +#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT 0x4 +#define VGA_QOS_CTRL__VGA_READ_QOS_MASK 0x0000000FL +#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK 0x000000F0L +//D3VGA_CONTROL +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 +#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L +#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L +#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L +//D4VGA_CONTROL +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 +#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L +#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L +#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L +//D5VGA_CONTROL +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 +#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L +#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L +#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L +//D6VGA_CONTROL +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 +#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 +#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L +#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L +#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L +#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L +#define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L +//VGA_SOURCE_SELECT +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L +#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L + + +// addressBlock: dce_dc_dccg_dccg_dispdec +//PHYPLLA_PIXCLK_RESYNC_CNTL +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//PHYPLLB_PIXCLK_RESYNC_CNTL +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//PHYPLLC_PIXCLK_RESYNC_CNTL +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//PHYPLLD_PIXCLK_RESYNC_CNTL +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//DP_DTO_DBUF_EN +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L +//DPREFCLK_CGTT_BLK_CTRL_REG +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//REFCLK_CNTL +#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT 0x0 +#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT 0x1 +#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK 0x00000001L +#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK 0x00000002L +//REFCLK_CGTT_BLK_CTRL_REG +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//PHYPLLE_PIXCLK_RESYNC_CNTL +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L +//DCCG_PERFMON_CNTL2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_DS_DTO_INCR +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 +#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_DS_DTO_MODULO +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 +#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_DS_CNTL +#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT 0x4 +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 +#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x00000001L +#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK 0x00000030L +#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x00000100L +#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x00000200L +#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x00030000L +#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x01000000L +#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x02000000L +//DCCG_DS_HW_CAL_INTERVAL +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 +#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xFFFFFFFFL +//DPREFCLK_CNTL +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L +//DCE_VERSION +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL +#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L +//DCCG_GTC_CNTL +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 +#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L +//DCCG_GTC_DTO_INCR +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 +#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xFFFFFFFFL +//DCCG_GTC_DTO_MODULO +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 +#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xFFFFFFFFL +//DCCG_GTC_CURRENT +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 +#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xFFFFFFFFL +//DSCCLK0_DTO_PARAM +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK1_DTO_PARAM +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK2_DTO_PARAM +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT 0x0 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT 0x10 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK 0x00FF0000L +//MILLISECOND_TIME_BASE_DIV +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DISPCLK_FREQ_CHANGE_CNTL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0E000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +//DC_MEM_GLOBAL_PWR_REQ_CNTL +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//DCCG_PERFMON_CNTL +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xFFFFF800L +//DCCG_GATE_DISABLE_CNTL +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L +//DISPCLK_CGTT_BLK_CTRL_REG +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SOCCLK_CGTT_BLK_CTRL_REG +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CAC_STATUS +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL +//MICROSECOND_TIME_BASE_DIV +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DCCG_GATE_DISABLE_CNTL2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L +//SYMCLK_CGTT_BLK_CTRL_REG +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_DISP_CNTL_REG +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L +//OTG0_PIXEL_RATE_CNTL +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT 0x8 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT 0x9 +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L +#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK 0x00000100L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK 0x00000200L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO0_PHASE +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL +//DP_DTO0_MODULO +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL +//OTG0_PHYPLL_PIXEL_RATE_CNTL +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG1_PIXEL_RATE_CNTL +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT 0x8 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L +#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK 0x00000100L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO1_PHASE +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL +//DP_DTO1_MODULO +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL +//OTG1_PHYPLL_PIXEL_RATE_CNTL +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG2_PIXEL_RATE_CNTL +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT 0x8 +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT 0x9 +#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L +#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK 0x00000100L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK 0x00000200L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO2_PHASE +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL +//DP_DTO2_MODULO +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL +//OTG2_PHYPLL_PIXEL_RATE_CNTL +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG3_PIXEL_RATE_CNTL +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT 0x8 +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT 0x9 +#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT 0xb +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L +#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK 0x00000100L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK 0x00000200L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK 0x00000800L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO3_PHASE +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL +//DP_DTO3_MODULO +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL +//OTG3_PHYPLL_PIXEL_RATE_CNTL +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//DPPCLK_CGTT_BLK_CTRL_REG +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DPPCLK0_DTO_PARAM +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK1_DTO_PARAM +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK2_DTO_PARAM +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT 0x0 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK3_DTO_PARAM +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT 0x0 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK 0x00FF0000L +//DCCG_CAC_STATUS2 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x0000007FL +//SYMCLKA_CLOCK_ENABLE +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKB_CLOCK_ENABLE +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKC_CLOCK_ENABLE +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKD_CLOCK_ENABLE +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L +//SYMCLKE_CLOCK_ENABLE +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L +//DCCG_SOFT_RESET +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT 0x1 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK 0x00000002L +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L +//DSCCLK_DTO_CTRL +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT 0x0 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT 0x1 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT 0x2 +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT 0x3 +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT 0x4 +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT 0x5 +#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE__SHIFT 0x6 +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd +#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN__SHIFT 0xe +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK 0x00000001L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK 0x00000002L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK 0x00000004L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK 0x00000008L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK 0x00000010L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK 0x00000020L +#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE_MASK 0x00000040L +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L +#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN_MASK 0x00004000L +//DCCG_AUDIO_DTO_SOURCE +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x00003000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x00010000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L +//DCCG_AUDIO_DTO0_PHASE +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO0_MODULE +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_PHASE +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_MODULE +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG0_LATCH_VALUE +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG1_LATCH_VALUE +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG2_LATCH_VALUE +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG3_LATCH_VALUE +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG4_LATCH_VALUE +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG5_LATCH_VALUE +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL +//DPPCLK_DTO_CTRL +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT 0x0 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT 0x4 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT 0x8 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9 +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT 0xc +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT 0x10 +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT 0x14 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK 0x00000001L +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK 0x00000010L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK 0x00000100L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK 0x00001000L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK 0x00010000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK 0x00100000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L +//DCCG_VSYNC_CNT_CTRL +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT 0x1 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK 0x00000002L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L +//DCCG_VSYNC_CNT_INT_CTRL +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x8 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x9 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0xb +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0xc +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0xd +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00000100L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00000200L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00000400L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00000800L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00001000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00002000L +//FORCE_SYMCLK_DISABLE +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L +//DCCG_TEST_CLK_SEL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT 0xe +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK 0x0000C000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x01FF0000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000L + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +//DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +//DC_PERFMON0_PERFCOUNTER_CNTL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_CNTL2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_STATE +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON0_PERFMON_CNTL +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON0_PERFMON_CNTL2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON0_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON0_PERFMON_CVALUE_LOW +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON0_PERFMON_HI +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFMON_LOW +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +//DC_PERFMON1_PERFCOUNTER_CNTL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_CNTL2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_STATE +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON1_PERFMON_CNTL +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON1_PERFMON_CNTL2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON1_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON1_PERFMON_CVALUE_LOW +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON1_PERFMON_HI +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFMON_LOW +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_pll_dispdec +//PLL_MACRO_CNTL_RESERVED0 +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED1 +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED2 +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED3 +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED4 +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED5 +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED6 +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED7 +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED8 +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED9 +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED10 +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED11 +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED12 +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED13 +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED14 +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED15 +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED16 +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED17 +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED18 +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED19 +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED20 +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED21 +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED22 +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED23 +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED24 +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED25 +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED26 +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED27 +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED28 +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED29 +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED30 +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED31 +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED32 +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED33 +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED34 +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED35 +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED36 +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED37 +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED38 +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED39 +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED40 +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL +//PLL_MACRO_CNTL_RESERVED41 +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT 0x0 +#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +//RBBMIF_TIMEOUT +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L +//RBBMIF_STATUS +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xFFFFFFFFL +//RBBMIF_STATUS_2 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT 0x0 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK 0x0000003FL +//RBBMIF_INT_STATUS +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK 0x0003FFFCL +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT 0x1e +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK 0x40000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS_2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK 0x00000020L +//RBBMIF_STATUS_FLAG +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +//DOMAIN0_PG_CONFIG +#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT 0x8 +#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK 0x00000100L +//DOMAIN0_PG_STATUS +#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN1_PG_CONFIG +#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT 0x8 +#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK 0x00000100L +//DOMAIN1_PG_STATUS +#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN2_PG_CONFIG +#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT 0x8 +#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK 0x00000100L +//DOMAIN2_PG_STATUS +#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN3_PG_CONFIG +#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT 0x8 +#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK 0x00000100L +//DOMAIN3_PG_STATUS +#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN4_PG_CONFIG +#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT 0x8 +#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK 0x00000100L +//DOMAIN4_PG_STATUS +#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN5_PG_CONFIG +#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT 0x8 +#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK 0x00000100L +//DOMAIN5_PG_STATUS +#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN6_PG_CONFIG +#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT 0x8 +#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK 0x00000100L +//DOMAIN6_PG_STATUS +#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN7_PG_CONFIG +#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT 0x8 +#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK 0x00000100L +//DOMAIN7_PG_STATUS +#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN16_PG_CONFIG +#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE__SHIFT 0x8 +#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE_MASK 0x00000100L +//DOMAIN16_PG_STATUS +#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN17_PG_CONFIG +#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE__SHIFT 0x8 +#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE_MASK 0x00000100L +//DOMAIN17_PG_STATUS +#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN18_PG_CONFIG +#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE__SHIFT 0x8 +#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE_MASK 0x00000100L +//DOMAIN18_PG_STATUS +#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DCPG_INTERRUPT_STATUS +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0xa +#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xd +#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xf +#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 +#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x12 +#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x14 +#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x16 +#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x18 +#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x19 +#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x1a +#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x1b +#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x1c +#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x1d +#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x1e +#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x1f +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00000100L +#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L +#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00000400L +#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L +#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00001000L +#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L +#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00004000L +#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L +#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00010000L +#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L +#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00040000L +#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00100000L +#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L +#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00400000L +#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L +#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x01000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x02000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x04000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x08000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x10000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x20000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x40000000L +#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x80000000L +//DCPG_INTERRUPT_STATUS_2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT 0xa +#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED_MASK 0x00000100L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED_MASK 0x00000400L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L +//DCPG_INTERRUPT_CONTROL_1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT 0x14 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x15 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT 0x18 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x19 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT 0x1a +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0x1b +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT 0x1c +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1d +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT 0x1e +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0x1f +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK 0x00010000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK 0x00100000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00200000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK 0x00400000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK 0x01000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x02000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK 0x04000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x08000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK 0x10000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x20000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK 0x40000000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x80000000L +//DCPG_INTERRUPT_CONTROL_2 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT 0x14 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x15 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT 0x18 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x19 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT 0x1a +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x1b +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT 0x1c +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x1d +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT 0x1e +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x1f +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK 0x00010000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK 0x00100000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00200000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK 0x00400000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK 0x01000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x02000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK 0x04000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x08000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK 0x10000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x20000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK 0x40000000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x80000000L +//DCPG_INTERRUPT_CONTROL_3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK__SHIFT 0x14 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR__SHIFT 0x15 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK__SHIFT 0x16 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK_MASK 0x00010000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK_MASK 0x00100000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR_MASK 0x00200000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK_MASK 0x00400000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +//DC_IP_REQUEST_CNTL +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON2_PERFCOUNTER_CNTL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_CNTL2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_STATE +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON2_PERFMON_CNTL +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON2_PERFMON_CNTL2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON2_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON2_PERFMON_CVALUE_LOW +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON2_PERFMON_HI +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFMON_LOW +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +//CC_DC_PIPE_DIS +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L +//DMU_CLK_CNTL +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4 +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x5 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x6 +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x8 +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT 0x9 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0xa +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00000020L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000040L +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000100L +#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK 0x00000200L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000400L +//DMU_MEM_PWR_CNTL +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT 0x0 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT 0x1 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT 0x3 +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT 0x4 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT 0x8 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT 0x9 +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT 0xa +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK 0x00000001L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK 0x00000006L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK 0x00000008L +#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK 0x00000030L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK 0x00000100L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK 0x00000200L +#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L +//DMCU_SMU_INTERRUPT_CNTL +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x00000001L +#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xFFFF0000L +//SMU_INTERRUPT_CONTROL +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L +//DMU_MISC_ALLOW_DS_FORCE +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L + + +// addressBlock: dce_dc_dmu_dmcu_dispdec +//DMCU_CTRL +#define DMCU_CTRL__RESET_UC__SHIFT 0x0 +#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 +#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 +#define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT 0x8 +#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x10 +#define DMCU_CTRL__RESET_UC_MASK 0x00000001L +#define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L +#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L +#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L +#define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L +#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK 0x00000100L +#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xFFFF0000L +//DMCU_STATUS +#define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 +#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 +#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 +#define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L +#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L +#define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L +//DMCU_PC_START_ADDR +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_START_ADDR +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_END_ADDR +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_ISR_START_ADDR +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000FFL +#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000FF00L +//DMCU_FW_CS_HI +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 +#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xFFFFFFFFL +//DMCU_FW_CS_LO +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 +#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xFFFFFFFFL +//DMCU_RAM_ACCESS_CTRL +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 +#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L +#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L +#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L +#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L +#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L +#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L +//DMCU_ERAM_WR_CTRL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000FFFFL +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000F0000L +#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L +//DMCU_ERAM_WR_DATA +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 +#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xFFFFFFFFL +//DMCU_ERAM_RD_CTRL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 +#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000FFFFL +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000F0000L +#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L +//DMCU_ERAM_RD_DATA +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 +#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xFFFFFFFFL +//DMCU_IRAM_WR_CTRL +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 +#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003FFL +//DMCU_IRAM_WR_DATA +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 +#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000FFL +//DMCU_IRAM_RD_CTRL +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 +#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003FFL +//DMCU_IRAM_RD_DATA +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 +#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000FFL +//DMCU_EVENT_TRIGGER +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 +#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L +#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007F0000L +#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L +//DMCU_UC_INTERNAL_INT_STATUS +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L +#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L +//DMCU_SS_INTERRUPT_CNTL_STATUS +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x00002000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x00004000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x00004000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x00008000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x00010000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x00010000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x00020000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x00040000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x00040000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x00080000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x00100000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x00100000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x00200000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x00400000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x00400000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x00800000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x01000000L +#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x01000000L +//DMCU_INTERRUPT_STATUS +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L +#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L +//DMCU_INTERRUPT_STATUS_1 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK 0x00002000L +//DMCU_INTERRUPT_TO_HOST_EN_MASK +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L +//DMCU_INTERRUPT_TO_UC_EN_MASK +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x40000000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK 0x00002000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0x1e +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x40000000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +//DC_DMCU_SCRATCH +#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 +#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xFFFFFFFFL +//DMCU_INT_CNT +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00FF0000L +//DMCU_FW_CHECKSUM_SMPL_BYTE_POS +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L +#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000CL +//DMCU_UC_CLK_GATING_CNTL +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 +#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L +#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L +#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L +//MASTER_COMM_DATA_REG1 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L +//MASTER_COMM_DATA_REG2 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L +//MASTER_COMM_DATA_REG3 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L +//MASTER_COMM_CMD_REG +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000FFL +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L +#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xFF000000L +//MASTER_COMM_CNTL_REG +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 +#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +//SLAVE_COMM_DATA_REG1 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_DATA_REG2 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_DATA_REG3 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_CMD_REG +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000FFL +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000FF00L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00FF0000L +#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xFF000000L +//SLAVE_COMM_CNTL_REG +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 +#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L +#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_STATUS1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_STATUS2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_STATUS3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_STATUS4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_STATUS5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK 0x00000200L +#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK 0x00000200L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK 0x00000200L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +//DMCU_DPRX_INTERRUPT_STATUS1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK 0x10000000L +#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK 0x10000000L +//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK 0x10000000L +//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +//DMCU_INTERRUPT_STATUS_CONTINUE +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT 0xc +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT 0xd +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT 0xe +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT 0x17 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT 0x18 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT 0x19 +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT 0x1a +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT 0x1b +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT 0x1c +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK 0x00001000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK 0x00002000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK 0x00004000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK 0x00800000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK 0x01000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK 0x02000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK 0x04000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK 0x08000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK 0x10000000L +#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK 0x10000000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK 0x10000000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xc +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xd +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xe +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xf +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT 0x17 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT 0x18 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT 0x19 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1a +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1b +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x1c +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00001000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00002000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00004000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00008000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK 0x00400000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK 0x00800000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK 0x01000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK 0x02000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x04000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x08000000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x10000000L +//DMCU_INT_CNT_CONTINUE +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT 0x0 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT 0x8 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT 0x10 +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK 0x000000FFL +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK 0x0000FF00L +#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK 0x00FF0000L +//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK 0x00400000L +//DMCU_INTERRUPT_STATUS_2 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x0 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x2 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0x3 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT 0x4 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x6 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0x8 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0x9 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT 0xa +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT 0x10 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT 0x11 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT 0x12 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT 0x13 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT 0x14 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT 0x15 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT 0x16 +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000001L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000004L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00000008L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK 0x00000010L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000040L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000100L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00000200L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK 0x00000400L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK 0x00010000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK 0x00020000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK 0x00040000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK 0x00080000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK 0x00100000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK 0x00200000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK 0x00400000L +#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK 0x00400000L +//DMCU_INTERRUPT_TO_UC_EN_MASK_2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT 0x0 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT 0x1 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT 0x2 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT 0x3 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT 0x4 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT 0x5 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x6 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x7 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x8 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x9 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xa +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT 0xb +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT 0x10 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT 0x11 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT 0x12 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT 0x13 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT 0x14 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT 0x15 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT 0x16 +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK 0x00000001L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK 0x00000002L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK 0x00000004L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK 0x00000008L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK 0x00000010L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK 0x00000020L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000040L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000080L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000100L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000200L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000400L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK 0x00000800L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK 0x00010000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK 0x00020000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK 0x00040000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK 0x00080000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK 0x00100000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK 0x00200000L +#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK 0x00400000L + + +// addressBlock: dce_dc_dmu_ihc_dispdec +//DC_GPU_TIMER_START_POSITION_V_UPDATE +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_VSTARTUP +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L +//DC_GPU_TIMER_READ +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL +//DC_GPU_TIMER_READ_CNTL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +//DISP_INTERRUPT_STATUS +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE14 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE15 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE19 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE20 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE21 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE22 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L +//DC_GPU_TIMER_START_POSITION_VREADY +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L +//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP_AWAY +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L +//DISP_INTERRUPT_STATUS_CONTINUE23 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE24 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x02000000L +//DCCG_INTERRUPT_DEST +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +//DMU_INTERRUPT_DEST +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT 0xe +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT 0xf +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x10 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT 0x11 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT 0x12 +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT 0x13 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x18 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x19 +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1a +#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT 0x1b +#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT 0x1c +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00000800L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK 0x00004000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK 0x00008000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK 0x00010000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK 0x00020000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK 0x00040000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK 0x00080000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x01000000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x02000000L +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x04000000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK 0x08000000L +#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK 0x10000000L +//DCPG_INTERRUPT_DEST +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT 0xb +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT 0xc +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT 0xd +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT 0xe +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT 0xf +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x18 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x19 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1a +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1b +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1c +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1d +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1e +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1f +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK 0x00000800L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK 0x00001000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK 0x00002000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK 0x00004000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK 0x00008000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK 0x01000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK 0x02000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK 0x04000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK 0x08000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK 0x10000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK 0x20000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK 0x40000000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK 0x80000000L +//DCPG_INTERRUPT_DEST2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0xb +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00000800L +//MMHUBBUB_INTERRUPT_DEST +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT 0x0 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK 0x00000001L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//WB_INTERRUPT_DEST +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0x0 +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1 +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0x8 +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9 +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT 0xa +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000001L +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000100L +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK 0x00000400L +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +//DCHUB_INTERRUPT_DEST +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1f +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x80000000L +//DCHUB_PERFCOUNTER_INTERRUPT_DEST +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x20000000L +//DCHUB_INTERRUPT_DEST2 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x02000000L +//DPP_PERFCOUNTER_INTERRUPT_DEST +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +//MPC_INTERRUPT_DEST +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0 +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1 +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2 +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3 +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4 +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5 +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6 +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7 +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPP_INTERRUPT_DEST +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPTC_INTERRUPT_DEST +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18 +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19 +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L +//OTG0_INTERRUPT_DEST +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +//OTG1_INTERRUPT_DEST +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +//OTG2_INTERRUPT_DEST +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +//OTG3_INTERRUPT_DEST +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +//OTG4_INTERRUPT_DEST +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +//OTG5_INTERRUPT_DEST +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT 0xc +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT 0xd +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT 0xe +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK 0x00001000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK 0x00002000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK 0x00004000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +//DIG_INTERRUPT_DEST +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L +//I2C_DDC_HPD_INTERRUPT_DEST +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16 +#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x17 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L +#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK 0x00800000L +//DIO_INTERRUPT_DEST +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//DCIO_INTERRUPT_DEST +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10 +#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST__SHIFT 0x18 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L +#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST_MASK 0x01000000L +//HPD_INTERRUPT_DEST +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd +#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST__SHIFT 0xe +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L +#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST_MASK 0x00004000L +//AZ_INTERRUPT_DEST +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17 +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1e +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1f +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x40000000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x80000000L +//AUX_INTERRUPT_DEST +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x10 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x12 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x13 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x14 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x16 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x17 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x18 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x19 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT 0x1a +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT 0x1b +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00010000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00040000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00080000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00100000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x00400000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x00800000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x01000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x02000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK 0x04000000L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK 0x08000000L +//DSC_INTERRUPT_DEST +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x0 +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x4 +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x6 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x7 +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x8 +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9 +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xa +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xb +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0xc +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x10 +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x14 +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000001L +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L +#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000010L +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000040L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000080L +#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00000100L +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000400L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000800L +#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00001000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00010000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK 0x00100000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L + + +// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec +//WB_ENABLE +#define WB_ENABLE__WB_ENABLE__SHIFT 0x0 +#define WB_ENABLE__WB_ENABLE_MASK 0x00000001L +//WB_EC_CONFIG +#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT 0x0 +#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT 0x1 +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT 0x2 +#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT 0x3 +#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT 0x7 +#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT 0x8 +#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT 0x9 +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT 0xc +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT 0xe +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT 0xf +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT 0x15 +#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT 0x17 +#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE__SHIFT 0x18 +#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK 0x00000001L +#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK 0x00000002L +#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK 0x00000004L +#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK 0x00000078L +#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK 0x00000080L +#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK 0x00000100L +#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK 0x00000200L +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x00003000L +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK 0x00004000L +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK 0x00018000L +#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK 0x00600000L +#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK 0x00800000L +#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE_MASK 0x03000000L +//CNV_MODE +#define CNV_MODE__CNV_OUT_BPC__SHIFT 0x4 +#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT 0x8 +#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT 0xc +#define CNV_MODE__CNV_STEREO_TYPE__SHIFT 0xd +#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT 0xf +#define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 +#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT 0x12 +#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT 0x13 +#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT 0x14 +#define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 +#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1e +#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT 0x1f +#define CNV_MODE__CNV_OUT_BPC_MASK 0x00000010L +#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK 0x00000300L +#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK 0x00001000L +#define CNV_MODE__CNV_STEREO_TYPE_MASK 0x00006000L +#define CNV_MODE__CNV_INTERLACED_MODE_MASK 0x00008000L +#define CNV_MODE__CNV_EYE_SELECTION_MASK 0x00030000L +#define CNV_MODE__CNV_STEREO_POLARITY_MASK 0x00040000L +#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK 0x00080000L +#define CNV_MODE__CNV_STEREO_SPLIT_MASK 0x00100000L +#define CNV_MODE__CNV_NEW_CONTENT_MASK 0x01000000L +#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT_MASK 0x40000000L +#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK 0x80000000L +//CNV_WINDOW_START +#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 +#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 +#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0x00000FFFL +#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0x0FFF0000L +//CNV_WINDOW_SIZE +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 +#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0x00000FFFL +#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0x0FFF0000L +//CNV_UPDATE +#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 +#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 +#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 +#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x00000001L +#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x00000100L +#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x00010000L +//CNV_SOURCE_SIZE +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 +#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x00007FFFL +#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7FFF0000L +//CNV_TEST_CNTL +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 +#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x00000010L +#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x00000100L +//CNV_TEST_CRC_RED +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0x0000FFF0L +#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xFFFF0000L +//CNV_TEST_CRC_GREEN +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0x0000FFF0L +#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L +//CNV_TEST_CRC_BLUE +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x4 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0x0000FFF0L +#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L +//WB_DEBUG_CTRL +#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT 0x0 +#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6 +#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x00000001L +#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0x000000C0L +//WB_DBG_MODE +#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0 +#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1 +#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2 +#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3 +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8 +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10 +#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x00000001L +#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x00000002L +#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x00000004L +#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x00000008L +#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x00000100L +#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7FFF0000L +//WB_HW_DEBUG +#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0 +#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xFFFFFFFFL +//WB_SOFT_RESET +#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT 0x0 +#define WB_SOFT_RESET__WB_SOFT_RESET_MASK 0x00000001L +//WB_WARM_UP_MODE_CTL1 +#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT 0x0 +#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT 0x10 +#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT 0x1f +#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK 0x00007FFFL +#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK 0x7FFF0000L +#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK 0x80000000L +//WB_WARM_UP_MODE_CTL2 +#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT 0x0 +#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT 0x10 +#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP__SHIFT 0x14 +#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK 0x000003FFL +#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK 0x00010000L +#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP_MASK 0x00100000L +//CNV_TEST_DEBUG_INDEX +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CNV_TEST_DEBUG_DATA +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 +#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec +//WBSCL_COEF_RAM_SELECT +#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT 0x8 +#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000007L +#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK 0x00000F00L +#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK 0x00030000L +//WBSCL_COEF_RAM_TAP_DATA +#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//WBSCL_MODE +#define WBSCL_MODE__WBSCL_MODE__SHIFT 0x0 +#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH__SHIFT 0x4 +#define WBSCL_MODE__WBSCL_MODE_MASK 0x00000003L +#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH_MASK 0x00000010L +//WBSCL_TAP_CONTROL +#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 +#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 +#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 +#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc +#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK 0x0000000FL +#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK 0x000000F0L +#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK 0x00000F00L +#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK 0x0000F000L +//WBSCL_DEST_SIZE +#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT 0x0 +#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT 0x10 +#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK 0x00007FFFL +#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK 0x7FFF0000L +//WBSCL_HORZ_FILTER_SCALE_RATIO +#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT 0x0 +#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//WBSCL_HORZ_FILTER_INIT_Y_RGB +#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 +#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT 0x18 +#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL +#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK 0x1F000000L +//WBSCL_HORZ_FILTER_INIT_CBCR +#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT 0x0 +#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT 0x18 +#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK 0x00FFFFFFL +#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK 0x1F000000L +//WBSCL_VERT_FILTER_SCALE_RATIO +#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT 0x0 +#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//WBSCL_VERT_FILTER_INIT_Y_RGB +#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 +#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT 0x18 +#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK 0x00FFFFFFL +#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK 0x1F000000L +//WBSCL_VERT_FILTER_INIT_CBCR +#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT 0x0 +#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT 0x18 +#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK 0x00FFFFFFL +#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK 0x1F000000L +//WBSCL_ROUND_OFFSET +#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 +#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT 0x10 +#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK 0x000003FFL +#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK 0x03FF0000L +//WBSCL_OVERFLOW_STATUS +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT 0xc +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//WBSCL_COEF_RAM_CONFLICT_STATUS +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT 0x0 +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT 0x8 +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT 0xc +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK 0x00000001L +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK 0x00000100L +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK 0x00001000L +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L +#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK 0x00100000L +//WBSCL_TEST_CNTL +#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT 0x4 +#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT 0x8 +#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK 0x00000010L +#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK 0x00000100L +//WBSCL_TEST_CRC_RED +#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT 0x0 +#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT 0x10 +#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK 0x000003FFL +#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK 0xFFFF0000L +//WBSCL_TEST_CRC_GREEN +#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 +#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 +#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK 0x0000FFFFL +#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK 0xFFFF0000L +//WBSCL_TEST_CRC_BLUE +#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT 0x0 +#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 +#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK 0x000003FFL +#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK 0xFFFF0000L +//WBSCL_BACKPRESSURE_CNT_EN +#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//WB_MCIF_BACKPRESSURE_CNT +#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 +#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 +#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK 0x0000FFFFL +#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK 0xFFFF0000L +//WBSCL_CLAMP_Y_RGB +#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 +#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT 0x10 +#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB_MASK 0x000003FFL +#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB_MASK 0x03FF0000L +//WBSCL_CLAMP_CBCR +#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR__SHIFT 0x0 +#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR__SHIFT 0x10 +#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR_MASK 0x000003FFL +#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR_MASK 0x03FF0000L +//WBSCL_OUTSIDE_PIX_STRATEGY +#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 +#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT 0x10 +#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK 0x00000001L +#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK 0x03FF0000L +//WBSCL_OUTSIDE_PIX_STRATEGY_CBCR +#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB__SHIFT 0x0 +#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR__SHIFT 0x10 +#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR_MASK 0x03FF0000L +//WBSCL_DEBUG +#define WBSCL_DEBUG__WBSCL_DEBUG__SHIFT 0x0 +#define WBSCL_DEBUG__WBSCL_DEBUG_MASK 0xFFFFFFFFL +//WBSCL_TEST_DEBUG_INDEX +#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX__SHIFT 0x0 +#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//WBSCL_TEST_DEBUG_DATA +#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA__SHIFT 0x0 +#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON3_PERFCOUNTER_CNTL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_CNTL2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_STATE +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON3_PERFMON_CNTL +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON3_PERFMON_CNTL2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON3_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON3_PERFMON_CVALUE_LOW +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON3_PERFMON_HI +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFMON_LOW +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L +#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R +#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL +//MCIF_WB0_MCIF_WB_BUFMGR_STATUS +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB0_MCIF_WB_BUF_PITCH +#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB0_MCIF_WB_BUF_1_STATUS +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB0_MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L +//MCIF_WB0_MCIF_WB_BUF_2_STATUS +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB0_MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L +//MCIF_WB0_MCIF_WB_BUF_3_STATUS +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB0_MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L +//MCIF_WB0_MCIF_WB_BUF_4_STATUS +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB0_MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L +//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 +#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L +//MCIF_WB0_MCIF_WB_SCLK_CHANGE +#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL +//MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX +#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA +#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL +//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L +#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L +//MCIF_WB0_MCIF_WB_WATERMARK +#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL +//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB0_MCIF_WB_WARM_UP_CNTL +#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 +#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L +//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L +#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MCIF_WB0_MULTI_LEVEL_QOS_CTRL +#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB0_MCIF_WB_SECURITY_LEVEL +#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L +//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L + + +// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec +//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L +#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R +#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL +//MCIF_WB1_MCIF_WB_BUFMGR_STATUS +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB1_MCIF_WB_BUF_PITCH +#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB1_MCIF_WB_BUF_1_STATUS +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB1_MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L +//MCIF_WB1_MCIF_WB_BUF_2_STATUS +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB1_MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L +//MCIF_WB1_MCIF_WB_BUF_3_STATUS +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB1_MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L +//MCIF_WB1_MCIF_WB_BUF_4_STATUS +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB1_MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L +//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 +#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L +//MCIF_WB1_MCIF_WB_SCLK_CHANGE +#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL +//MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX +#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA +#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL +//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L +#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L +//MCIF_WB1_MCIF_WB_WATERMARK +#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL +//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB1_MCIF_WB_WARM_UP_CNTL +#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 +#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L +//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L +#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MCIF_WB1_MULTI_LEVEL_QOS_CTRL +#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +//WBIF0_MISC_CTRL +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L +//WBIF0_SMU_WM_CONTROL +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL__SHIFT 0x14 +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ__SHIFT 0x16 +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL_MASK 0x00300000L +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ_MASK 0x00400000L +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF0_PHASE0_OUTSTANDING_COUNTER +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF0_PHASE1_OUTSTANDING_COUNTER +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//VGA_SRC_SPLIT_CNTL +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT 0x0 +#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK 0x00000003L +//MMHUBBUB_MEM_PWR_STATUS +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT 0x1f +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L +#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK 0x80000000L +//MMHUBBUB_MEM_PWR_CNTL +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT 0x1 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK 0x00000001L +#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK 0x00000002L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L +//MMHUBBUB_CLOCK_CNTL +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT 0x6 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT 0x7 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x8 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK 0x00000040L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK 0x00000080L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000100L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L +//MMHUBBUB_SOFT_RESET +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT 0x1 +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8 +#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L +#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK 0x00000002L +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L +//DMU_IF_ERR_STATUS +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L +//MMHUBBUB_CLIENT_UNIT_ID +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT 0x0 +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8 +#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK 0x0000003FL +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L + + +// addressBlock: dce_dc_mmhubbub_vgaif_dispdec +//MCIF_CONTROL +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L +#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L +//MCIF_WRITE_COMBINE_CONTROL +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 +#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000003FFL +//MCIF_PHASE0_OUTSTANDING_COUNTER +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE1_OUTSTANDING_COUNTER +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MCIF_PHASE2_OUTSTANDING_COUNTER +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT 0x0 +#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON4_PERFCOUNTER_CNTL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_CNTL2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_STATE +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON4_PERFMON_CNTL +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON4_PERFMON_CNTL2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON4_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON4_PERFMON_CVALUE_LOW +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON4_PERFMON_HI +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFMON_LOW +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +//AZF0STREAM0_AZALIA_STREAM_INDEX +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM0_AZALIA_STREAM_DATA +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +//AZF0STREAM1_AZALIA_STREAM_INDEX +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM1_AZALIA_STREAM_DATA +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +//AZF0STREAM2_AZALIA_STREAM_INDEX +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM2_AZALIA_STREAM_DATA +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +//AZF0STREAM3_AZALIA_STREAM_INDEX +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM3_AZALIA_STREAM_DATA +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +//AZF0STREAM4_AZALIA_STREAM_INDEX +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM4_AZALIA_STREAM_DATA +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +//AZF0STREAM5_AZALIA_STREAM_INDEX +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM5_AZALIA_STREAM_DATA +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +//AZF0STREAM6_AZALIA_STREAM_INDEX +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM6_AZALIA_STREAM_DATA +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +//AZF0STREAM7_AZALIA_STREAM_INDEX +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM7_AZALIA_STREAM_DATA +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_az_misc_dispdec +//AZ_CLOCK_CNTL +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x10 +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0x18 +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00010000L +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x1F000000L + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON5_PERFCOUNTER_CNTL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_CNTL2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_STATE +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON5_PERFMON_CNTL +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON5_PERFMON_CNTL2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON5_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON5_PERFMON_CVALUE_LOW +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON5_PERFMON_HI +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFMON_LOW +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +//AZALIA_CONTROLLER_CLOCK_GATING +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L +//AZALIA_AUDIO_DTO +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L +//AZALIA_AUDIO_DTO_CONTROL +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +//AZALIA_SOCCLK_CONTROL +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L +//AZALIA_UNDERFLOW_FILLER_SAMPLE +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL +//AZALIA_DATA_DMA_CONTROL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +//AZALIA_BDL_DMA_CONTROL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L +//AZALIA_RIRB_AND_DP_CONTROL +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L +//AZALIA_CORB_DMA_CONTROL +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 +#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xFFFFFFFFL +//AZALIA_CYCLIC_BUFFER_SYNC +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 +#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L +//AZALIA_GLOBAL_CAPABILITIES +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +//AZALIA_OUTPUT_PAYLOAD_CAPABILITY +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L +//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L +//AZALIA_INPUT_PAYLOAD_CAPABILITY +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L +//AZALIA_INPUT_CRC0_CONTROL0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_CONTROL1 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CONTROL2 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC0_CONTROL3 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_RESULT +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_CONTROL1 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL2 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC1_CONTROL3 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_RESULT +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL0 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC0_CONTROL1 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL2 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC0_CONTROL3 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC0_RESULT +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL0 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC1_CONTROL1 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL2 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC1_CONTROL3 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC1_RESULT +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_MEM_PWR_CTRL +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L +//AZALIA_MEM_PWR_STATUS +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hda_azf0root_dispdec +//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//AZALIA_F0_GTC_GROUP_OFFSET0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET1 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET2 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET3 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET4 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET5 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xFFFFFFFFL +//AZALIA_F0_GTC_GROUP_OFFSET6 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 +#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xFFFFFFFFL +//REG_DC_AUDIO_PORT_CONNECTIVITY +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +//AZF0STREAM8_AZALIA_STREAM_INDEX +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM8_AZALIA_STREAM_DATA +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +//AZF0STREAM9_AZALIA_STREAM_INDEX +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM9_AZALIA_STREAM_DATA +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +//AZF0STREAM10_AZALIA_STREAM_INDEX +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM10_AZALIA_STREAM_DATA +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +//AZF0STREAM11_AZALIA_STREAM_INDEX +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM11_AZALIA_STREAM_DATA +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +//AZF0STREAM12_AZALIA_STREAM_INDEX +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM12_AZALIA_STREAM_DATA +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +//AZF0STREAM13_AZALIA_STREAM_INDEX +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM13_AZALIA_STREAM_DATA +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +//AZF0STREAM14_AZALIA_STREAM_INDEX +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM14_AZALIA_STREAM_DATA +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +//AZF0STREAM15_AZALIA_STREAM_INDEX +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM15_AZALIA_STREAM_DATA +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec +//DCHUBBUB_SDPIF_CFG0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L +//VM_REQUEST_PHYSICAL +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0 +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3 +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L +//DCHUBBUB_FORCE_IO_STATUS_0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L +//DCHUBBUB_FORCE_IO_STATUS_1 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL +//DCN_VM_FB_LOCATION_BASE +#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//DCN_VM_FB_LOCATION_TOP +#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//DCN_VM_FB_OFFSET +#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//DCN_VM_AGP_BOT +#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//DCN_VM_AGP_TOP +#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//DCN_VM_AGP_BASE +#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_START +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_END +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//DCHUBBUB_SDPIF_PIPE_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT 0x6 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT 0x9 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK 0x00000007L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK 0x00000038L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK 0x000001C0L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK 0x00000E00L +//DCHUBBUB_SDPIF_MEM_PWR_CTRL +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_SDPIF_MEM_PWR_STATUS +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_SDPIF_CFG1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L +//DCHUBBUB_SDPIF_CFG2 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK 0x00000700L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L + + +// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec +//DCHUBBUB_RET_PATH_DCC_CFG +#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK 0x00000001L +//DCHUBBUB_RET_PATH_DCC_CFG0_0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG0_1 +#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG1_0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG1_1 +#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG2_0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG2_1 +#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG3_0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG3_1 +#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG4_0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG4_1 +#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG5_0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG5_1 +#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG6_0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG6_1 +#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG7_0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_DCC_CFG7_1 +#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK 0xFFFFFFFFL +//DCHUBBUB_RET_PATH_MEM_PWR_CTRL +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_RET_PATH_MEM_PWR_STATUS +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_CRC_CTRL +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB__SHIFT 0xf +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00007000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB_MASK 0x00008000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L +//DCHUBBUB_CRC0_VAL_R_G +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC0_VAL_B_A +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_R_G +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFF0000L +//DCHUBBUB_CRC1_VAL_B_A +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x10 +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK 0x0000FFFFL +#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dchubbub_hubbub_dispdec +//DCHUBBUB_ARB_DF_REQ_OUTSTAND +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0xc +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT 0x17 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x001FF000L +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK 0xFF800000L +//DCHUBBUB_ARB_SAT_LEVEL +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_QOS_FORCE +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L +//DCHUBBUB_ARB_DRAM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT 0x9 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK 0x00000100L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK 0x00000200L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A__SHIFT 0x10 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x00003FFFL +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A_MASK 0x3FFF0000L +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK 0xFFFF0000L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B__SHIFT 0x10 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x00003FFFL +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B_MASK 0x3FFF0000L +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK 0xFFFF0000L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C__SHIFT 0x10 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x00003FFFL +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C_MASK 0x3FFF0000L +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK 0xFFFF0000L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D__SHIFT 0x10 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x00003FFFL +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D_MASK 0x3FFF0000L +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D_MASK 0xFFFF0000L +//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT 0x10 +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK 0xFFFF0000L +//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L +//DCHUBBUB_ARB_TIMEOUT_ENABLE +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L +//DCHUBBUB_GLOBAL_TIMER_CNTL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L +//SURFACE_CHECK0_ADDRESS_LSB +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK0_ADDRESS_MSB +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK1_ADDRESS_LSB +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK1_ADDRESS_MSB +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK2_ADDRESS_LSB +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK2_ADDRESS_MSB +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK3_ADDRESS_LSB +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK3_ADDRESS_MSB +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L +//VTG0_CONTROL +#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 +#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10 +#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f +#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL +#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L +//VTG1_CONTROL +#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 +#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10 +#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f +#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL +#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L +//VTG2_CONTROL +#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 +#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0x10 +#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f +#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL +#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L +//VTG3_CONTROL +#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 +#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10 +#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f +#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL +#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L +//DCHUBBUB_SOFT_RESET +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L +//DCHUBBUB_CLOCK_CNTL +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L +//DCFCLK_CNTL +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x007FF800L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x13 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x7FF80000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L +//DCHUBBUB_VLINE_SNAPSHOT +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L +//DCHUBBUB_CTRL_STATUS +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0 +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL1 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL2 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L +//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L +//DCHUBBUB_TEST_DEBUG_INDEX +#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK 0x000000FFL +//DCHUBBUB_TEST_DEBUG_DATA +#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK 0x000003FFL +//DCHUBBUB_ARB_HOSTVM_CNTL +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT 0x0 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT 0x1 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT 0x2 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT 0x3 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT 0x4 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT 0x6 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT 0x8 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT 0x10 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT 0x18 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT 0x1c +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK 0x00000001L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK 0x00000002L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK 0x00000004L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK 0x00000008L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK 0x00000010L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK 0x00000040L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK 0x00003F00L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK 0x00FF0000L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK 0x0F000000L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK 0xF0000000L +//FMON_CTRL +#define FMON_CTRL__FMON_START__SHIFT 0x0 +#define FMON_CTRL__FMON_MODE__SHIFT 0x1 +#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4 +#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5 +#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6 +#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7 +#define FMON_CTRL__FMON_STATE__SHIFT 0x9 +#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc +#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd +#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11 +#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16 +#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b +#define FMON_CTRL__FMON_START_MASK 0x00000001L +#define FMON_CTRL__FMON_MODE_MASK 0x00000006L +#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L +#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L +#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L +#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L +#define FMON_CTRL__FMON_STATE_MASK 0x00000600L +#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L +#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L +#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L +#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L +#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L + + +// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON6_PERFCOUNTER_CNTL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_CNTL2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_STATE +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON6_PERFMON_CNTL +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON6_PERFMON_CNTL2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON6_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON6_PERFMON_CVALUE_LOW +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON6_PERFMON_HI +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFMON_LOW +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec +//DCN_VM_CONTEXT0_CNTL +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_CNTL +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_CNTL +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_CNTL +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_CNTL +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_CNTL +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_CNTL +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_CNTL +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_CNTL +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_CNTL +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_CNTL +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_CNTL +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_CNTL +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_CNTL +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_CNTL +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_CNTL +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_DEFAULT_ADDR_MSB +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT 0x1c +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT 0x1d +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK 0x10000000L +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK 0x20000000L +//DCN_VM_DEFAULT_ADDR_LSB +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//DCN_VM_FAULT_CNTL +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2 +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8 +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L +//DCN_VM_FAULT_STATUS +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x14 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x18 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x00300000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x0F000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L +//DCN_VM_FAULT_ADDR_MSB +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL +//DCN_VM_FAULT_ADDR_LSB +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +//HUBP0_DCSURF_SURFACE_CONFIG +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +//HUBP0_DCSURF_ADDR_CONFIG +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +//HUBP0_DCSURF_TILING_CONFIG +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP0_DCSURF_PRI_VIEWPORT_START +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_START_C +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START_C +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP0_DCHUBP_CNTL +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP0_HUBP_CLK_CNTL +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP0_DCHUBP_VMPG_CONFIG +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP0_HUBPREQ_DEBUG_DB +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +//HUBPREQ0_DCSURF_SURFACE_PITCH +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_SURFACE_PITCH_C +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ0_VMID_SETTINGS_0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ0_DCSURF_FLIP_CONTROL +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ0_DCSURF_FLIP_CONTROL2 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ0_DCSURF_SURFACE_INUSE +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCN_EXPANSION_MODE +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ0_DCN_TTU_QOS_WM +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ0_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ0_BLANK_OFFSET_0 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ0_BLANK_OFFSET_1 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ0_DST_DIMENSIONS +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ0_DST_AFTER_SCALER +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ0_PREFETCH_SETTINGS +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ0_PREFETCH_SETTINGS_C +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ0_VBLANK_PARAMETERS_1 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_2 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_3 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_4 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ0_FLIP_PARAMETERS_1 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_2 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_1 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_2 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_3 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_4 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_5 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_6 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_7 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_PER_LINE_DELIVERY_PRE +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ0_PER_LINE_DELIVERY +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ0_CURSOR_SETTINGS +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ0_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ0_VBLANK_PARAMETERS_5 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_6 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_3 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_4 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_5 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_6 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +//HUBPRET0_HUBPRET_CONTROL +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET0_HUBPRET_MEM_PWR_CTRL +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET0_HUBPRET_MEM_PWR_STATUS +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET0_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET0_HUBPRET_READ_LINE0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE1 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_INTERRUPT +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET0_HUBPRET_READ_LINE_VALUE +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_STATUS +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +//CURSOR0_0_CURSOR_CONTROL +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_0_CURSOR_SURFACE_ADDRESS +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_CURSOR_SIZE +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_0_CURSOR_POSITION +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_0_CURSOR_HOT_SPOT +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_0_CURSOR_STEREO_CONTROL +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_0_CURSOR_DST_OFFSET +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_0_CURSOR_MEM_PWR_CTRL +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_0_CURSOR_MEM_PWR_STATUS +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_0_DMDATA_ADDRESS_HIGH +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_0_DMDATA_ADDRESS_LOW +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_DMDATA_CNTL +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_QOS_CNTL +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_0_DMDATA_STATUS +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_0_DMDATA_SW_CNTL +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_SW_DATA +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON7_PERFCOUNTER_CNTL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_CNTL2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_STATE +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON7_PERFMON_CNTL +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON7_PERFMON_CNTL2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON7_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON7_PERFMON_CVALUE_LOW +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON7_PERFMON_HI +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFMON_LOW +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +//HUBP1_DCSURF_SURFACE_CONFIG +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +//HUBP1_DCSURF_ADDR_CONFIG +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +//HUBP1_DCSURF_TILING_CONFIG +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP1_DCSURF_PRI_VIEWPORT_START +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_START_C +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START_C +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP1_DCHUBP_CNTL +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP1_HUBP_CLK_CNTL +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP1_DCHUBP_VMPG_CONFIG +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP1_HUBPREQ_DEBUG_DB +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +//HUBPREQ1_DCSURF_SURFACE_PITCH +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_SURFACE_PITCH_C +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ1_VMID_SETTINGS_0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_CONTROL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ1_DCSURF_FLIP_CONTROL +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ1_DCSURF_FLIP_CONTROL2 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ1_DCSURF_SURFACE_INUSE +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCN_EXPANSION_MODE +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ1_DCN_TTU_QOS_WM +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ1_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ1_BLANK_OFFSET_0 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ1_BLANK_OFFSET_1 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ1_DST_DIMENSIONS +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ1_DST_AFTER_SCALER +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ1_PREFETCH_SETTINGS +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ1_PREFETCH_SETTINGS_C +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ1_VBLANK_PARAMETERS_1 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_2 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_3 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_4 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ1_FLIP_PARAMETERS_1 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_2 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_1 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_2 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_3 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_4 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_5 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_6 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_7 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_PER_LINE_DELIVERY_PRE +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ1_PER_LINE_DELIVERY +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ1_CURSOR_SETTINGS +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ1_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ1_VBLANK_PARAMETERS_5 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_6 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_3 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_4 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_5 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_6 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +//HUBPRET1_HUBPRET_CONTROL +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET1_HUBPRET_MEM_PWR_CTRL +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET1_HUBPRET_MEM_PWR_STATUS +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET1_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET1_HUBPRET_READ_LINE0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE1 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_INTERRUPT +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET1_HUBPRET_READ_LINE_VALUE +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_STATUS +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +//CURSOR0_1_CURSOR_CONTROL +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_1_CURSOR_SURFACE_ADDRESS +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_CURSOR_SIZE +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_1_CURSOR_POSITION +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_1_CURSOR_HOT_SPOT +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_1_CURSOR_STEREO_CONTROL +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_1_CURSOR_DST_OFFSET +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_1_CURSOR_MEM_PWR_CTRL +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_1_CURSOR_MEM_PWR_STATUS +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_1_DMDATA_ADDRESS_HIGH +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_1_DMDATA_ADDRESS_LOW +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_DMDATA_CNTL +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_QOS_CNTL +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_1_DMDATA_STATUS +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_1_DMDATA_SW_CNTL +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_SW_DATA +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON8_PERFCOUNTER_CNTL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_CNTL2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_STATE +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON8_PERFMON_CNTL +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON8_PERFMON_CNTL2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON8_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON8_PERFMON_CVALUE_LOW +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON8_PERFMON_HI +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFMON_LOW +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +//HUBP2_DCSURF_SURFACE_CONFIG +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +//HUBP2_DCSURF_ADDR_CONFIG +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +//HUBP2_DCSURF_TILING_CONFIG +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP2_DCSURF_PRI_VIEWPORT_START +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_START_C +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START_C +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP2_DCHUBP_CNTL +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP2_HUBP_CLK_CNTL +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP2_DCHUBP_VMPG_CONFIG +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP2_HUBPREQ_DEBUG_DB +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +//HUBPREQ2_DCSURF_SURFACE_PITCH +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ2_DCSURF_SURFACE_PITCH_C +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ2_VMID_SETTINGS_0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_CONTROL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ2_DCSURF_FLIP_CONTROL +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ2_DCSURF_FLIP_CONTROL2 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ2_DCSURF_SURFACE_INUSE +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCN_EXPANSION_MODE +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ2_DCN_TTU_QOS_WM +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ2_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ2_BLANK_OFFSET_0 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ2_BLANK_OFFSET_1 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ2_DST_DIMENSIONS +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ2_DST_AFTER_SCALER +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ2_PREFETCH_SETTINGS +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ2_PREFETCH_SETTINGS_C +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ2_VBLANK_PARAMETERS_1 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_2 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_3 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_4 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ2_FLIP_PARAMETERS_1 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_2 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_1 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_2 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_3 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_4 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_5 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_6 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_7 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_PER_LINE_DELIVERY_PRE +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ2_PER_LINE_DELIVERY +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ2_CURSOR_SETTINGS +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ2_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ2_VBLANK_PARAMETERS_5 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_6 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_3 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_4 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_5 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_6 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +//HUBPRET2_HUBPRET_CONTROL +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET2_HUBPRET_MEM_PWR_CTRL +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET2_HUBPRET_MEM_PWR_STATUS +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET2_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET2_HUBPRET_READ_LINE0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE1 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_INTERRUPT +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET2_HUBPRET_READ_LINE_VALUE +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_STATUS +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +//CURSOR0_2_CURSOR_CONTROL +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_2_CURSOR_SURFACE_ADDRESS +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_2_CURSOR_SIZE +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_2_CURSOR_POSITION +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_2_CURSOR_HOT_SPOT +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_2_CURSOR_STEREO_CONTROL +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_2_CURSOR_DST_OFFSET +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_2_CURSOR_MEM_PWR_CTRL +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_2_CURSOR_MEM_PWR_STATUS +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_2_DMDATA_ADDRESS_HIGH +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_2_DMDATA_ADDRESS_LOW +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_2_DMDATA_CNTL +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_QOS_CNTL +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_2_DMDATA_STATUS +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_2_DMDATA_SW_CNTL +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_SW_DATA +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON9_PERFCOUNTER_CNTL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_CNTL2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_STATE +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON9_PERFMON_CNTL +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON9_PERFMON_CNTL2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON9_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON9_PERFMON_CVALUE_LOW +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON9_PERFMON_HI +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFMON_LOW +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +//HUBP3_DCSURF_SURFACE_CONFIG +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +//HUBP3_DCSURF_ADDR_CONFIG +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT 0x3 +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT 0x8 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0xa +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK 0x00000038L +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE_MASK 0x00000300L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x00000C00L +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +//HUBP3_DCSURF_TILING_CONFIG +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT 0xa +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK 0x00000400L +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP3_DCSURF_PRI_VIEWPORT_START +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_START_C +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START_C +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP3_DCHUBP_CNTL +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT 0x2 +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK 0x00000004L +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP3_HUBP_CLK_CNTL +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP3_DCHUBP_VMPG_CONFIG +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +//HUBP3_HUBPREQ_DEBUG_DB +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +//HUBPREQ3_DCSURF_SURFACE_PITCH +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ3_DCSURF_SURFACE_PITCH_C +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ3_VMID_SETTINGS_0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_CONTROL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x4 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0x5 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT 0xa +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0xc +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT 0xd +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000010L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00000020L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK 0x00000400L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00001000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK 0x00002000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x00080000L +//HUBPREQ3_DCSURF_FLIP_CONTROL +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ3_DCSURF_FLIP_CONTROL2 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ3_DCSURF_SURFACE_INUSE +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCN_EXPANSION_MODE +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ3_DCN_TTU_QOS_WM +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ3_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ3_BLANK_OFFSET_0 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ3_BLANK_OFFSET_1 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ3_DST_DIMENSIONS +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ3_DST_AFTER_SCALER +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ3_PREFETCH_SETTINGS +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ3_PREFETCH_SETTINGS_C +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ3_VBLANK_PARAMETERS_1 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_2 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_3 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_4 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ3_FLIP_PARAMETERS_1 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_2 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_1 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_2 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_3 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_4 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_5 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_6 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_7 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_PER_LINE_DELIVERY_PRE +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ3_PER_LINE_DELIVERY +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ3_CURSOR_SETTINGS +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ3_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +//HUBPREQ3_VBLANK_PARAMETERS_5 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_6 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_3 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_4 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_5 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_6 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +//HUBPRET3_HUBPRET_CONTROL +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x0 +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xc +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00000FFFL +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00001000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET3_HUBPRET_MEM_PWR_CTRL +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00000030L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET3_HUBPRET_MEM_PWR_STATUS +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET3_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET3_HUBPRET_READ_LINE0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE1 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_INTERRUPT +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET3_HUBPRET_READ_LINE_VALUE +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_STATUS +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +//CURSOR0_3_CURSOR_CONTROL +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT 0xd +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT 0xe +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP_MASK 0x00002000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM_MASK 0x00004000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_3_CURSOR_SURFACE_ADDRESS +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_3_CURSOR_SIZE +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_3_CURSOR_POSITION +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_3_CURSOR_HOT_SPOT +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_3_CURSOR_STEREO_CONTROL +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_3_CURSOR_DST_OFFSET +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_3_CURSOR_MEM_PWR_CTRL +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_3_CURSOR_MEM_PWR_STATUS +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_3_DMDATA_ADDRESS_HIGH +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT 0x1c +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT 0x1d +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK 0x10000000L +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK 0x20000000L +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_3_DMDATA_ADDRESS_LOW +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_3_DMDATA_CNTL +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_QOS_CNTL +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_3_DMDATA_STATUS +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_3_DMDATA_SW_CNTL +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_SW_DATA +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON10_PERFCOUNTER_CNTL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_CNTL2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_STATE +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON10_PERFMON_CNTL +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON10_PERFMON_CNTL2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON10_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON10_PERFMON_CVALUE_LOW +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON10_PERFMON_HI +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFMON_LOW +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +//DPP_TOP0_DPP_CONTROL +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L +//DPP_TOP0_DPP_SOFT_RESET +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP0_DPP_CRC_VAL_R_G +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_VAL_B_A +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP0_DPP_CRC_CTRL +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP0_HOST_READ_CONTROL +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//CNVC_CFG0_FORMAT_CONTROL +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +//CNVC_CFG0_FCNV_FP_BIAS_R +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_G +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_B +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_R +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_G +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_B +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG0_COLOR_KEYER_CONTROL +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG0_COLOR_KEYER_ALPHA +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_RED +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_GREEN +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_BLUE +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec +//CNVC_CUR0_CURSOR0_CONTROL +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR0_CURSOR0_COLOR0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_COLOR1 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +//DSCL0_SCL_COEF_RAM_TAP_SELECT +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL0_SCL_COEF_RAM_TAP_DATA +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL0_SCL_MODE +#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL0_SCL_TAP_CONTROL +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL0_DSCL_CONTROL +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL0_DSCL_2TAP_CONTROL +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL0_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT_C +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT_C +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL0_SCL_BLACK_OFFSET +#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 +#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 +#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL +#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L +//DSCL0_DSCL_UPDATE +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL0_DSCL_AUTOCAL +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL0_OTG_H_BLANK +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL0_OTG_V_BLANK +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL0_RECOUT_START +#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL0_RECOUT_SIZE +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL0_MPC_SIZE +#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL0_LB_DATA_FORMAT +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL0_LB_MEMORY_CTRL +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL0_LB_V_COUNTER +#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL0_DSCL_MEM_PWR_CTRL +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL0_DSCL_MEM_PWR_STATUS +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL0_OBUF_CONTROL +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L +//DSCL0_OBUF_MEM_PWR_CTRL +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +//CM0_CM_CONTROL +#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM0_CM_ICSC_CONTROL +#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 +#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L +//CM0_CM_ICSC_C11_C12 +#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 +#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 +#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L +//CM0_CM_ICSC_C13_C14 +#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 +#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 +#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L +//CM0_CM_ICSC_C21_C22 +#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 +#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 +#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L +//CM0_CM_ICSC_C23_C24 +#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 +#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 +#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L +//CM0_CM_ICSC_C31_C32 +#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 +#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 +#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L +//CM0_CM_ICSC_C33_C34 +#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 +#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 +#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL +#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L +//CM0_CM_ICSC_B_C11_C12 +#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0 +#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10 +#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL +#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L +//CM0_CM_ICSC_B_C13_C14 +#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0 +#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10 +#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL +#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L +//CM0_CM_ICSC_B_C21_C22 +#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0 +#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10 +#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL +#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L +//CM0_CM_ICSC_B_C23_C24 +#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0 +#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10 +#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL +#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L +//CM0_CM_ICSC_B_C31_C32 +#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0 +#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10 +#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL +#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L +//CM0_CM_ICSC_B_C33_C34 +#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0 +#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10 +#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL +#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_CONTROL +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +//CM0_CM_GAMUT_REMAP_C11_C12 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C13_C14 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C21_C22 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C23_C24 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C31_C32 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_C33_C34 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C11_C12 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C13_C14 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C21_C22 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C23_C24 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C31_C32 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM0_CM_GAMUT_REMAP_B_C33_C34 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM0_CM_BIAS_CR_R +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM0_CM_BIAS_Y_G_CB_B +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM0_CM_DGAM_CONTROL +#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 +#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L +//CM0_CM_DGAM_LUT_INDEX +#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_DGAM_LUT_DATA +#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 +#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL +//CM0_CM_DGAM_LUT_WRITE_EN_MASK +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L +#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L +//CM0_CM_DGAM_RAMA_START_CNTL_B +#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_DGAM_RAMA_START_CNTL_G +#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_DGAM_RAMA_START_CNTL_R +#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_DGAM_RAMA_SLOPE_CNTL_B +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMA_SLOPE_CNTL_G +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMA_SLOPE_CNTL_R +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMA_END_CNTL1_B +#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMA_END_CNTL2_B +#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMA_END_CNTL1_G +#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMA_END_CNTL2_G +#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMA_END_CNTL1_R +#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMA_END_CNTL2_R +#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMA_REGION_0_1 +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_2_3 +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_4_5 +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_6_7 +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_8_9 +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_10_11 +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_12_13 +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMA_REGION_14_15 +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_START_CNTL_B +#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_DGAM_RAMB_START_CNTL_G +#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_DGAM_RAMB_START_CNTL_R +#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_DGAM_RAMB_SLOPE_CNTL_B +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMB_SLOPE_CNTL_G +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMB_SLOPE_CNTL_R +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_DGAM_RAMB_END_CNTL1_B +#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMB_END_CNTL2_B +#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMB_END_CNTL1_G +#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMB_END_CNTL2_G +#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMB_END_CNTL1_R +#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM0_CM_DGAM_RAMB_END_CNTL2_R +#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM0_CM_DGAM_RAMB_REGION_0_1 +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_2_3 +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_4_5 +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_6_7 +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_8_9 +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_10_11 +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_12_13 +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_DGAM_RAMB_REGION_14_15 +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_CONTROL +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0 +#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L +//CM0_CM_BLNDGAM_LUT_INDEX +#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_BLNDGAM_LUT_DATA +#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL +//CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK +#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B +#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G +#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R +#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B +#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G +#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R +#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM0_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_HDR_MULT_COEF +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM0_CM_MEM_PWR_CTRL +#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM0_CM_MEM_PWR_STATUS +#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM0_CM_DEALPHA +#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +//CM0_CM_COEF_FORMAT +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4 +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L +#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM0_CM_SHAPER_CONTROL +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +//CM0_CM_SHAPER_OFFSET_R +#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_SHAPER_OFFSET_G +#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_SHAPER_OFFSET_B +#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_SHAPER_SCALE_R +#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM0_CM_SHAPER_SCALE_G_B +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM0_CM_SHAPER_LUT_INDEX +#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM0_CM_SHAPER_LUT_DATA +#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM0_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8 +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L +//CM0_CM_SHAPER_RAMA_START_CNTL_B +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_START_CNTL_G +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_START_CNTL_R +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMA_END_CNTL_B +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_END_CNTL_G +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_END_CNTL_R +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMA_REGION_0_1 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_2_3 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_4_5 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_6_7 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_8_9 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_10_11 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_12_13 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_14_15 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_16_17 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_18_19 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_20_21 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_22_23 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_24_25 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_26_27 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_28_29 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_30_31 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMA_REGION_32_33 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_START_CNTL_B +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_START_CNTL_G +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_START_CNTL_R +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_SHAPER_RAMB_END_CNTL_B +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_END_CNTL_G +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_END_CNTL_R +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM0_CM_SHAPER_RAMB_REGION_0_1 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_2_3 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_4_5 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_6_7 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_8_9 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_10_11 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_12_13 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_14_15 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_16_17 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_18_19 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_20_21 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_22_23 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_24_25 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_26_27 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_28_29 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_30_31 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_SHAPER_RAMB_REGION_32_33 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_MEM_PWR_CTRL2 +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM0_CM_MEM_PWR_STATUS2 +#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM0_CM_3DLUT_MODE +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +//CM0_CM_3DLUT_INDEX +#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM0_CM_3DLUT_DATA +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM0_CM_3DLUT_DATA_30BIT +#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM0_CM_3DLUT_READ_WRITE_CONTROL +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L +#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM0_CM_3DLUT_OUT_NORM_FACTOR +#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM0_CM_3DLUT_OUT_OFFSET_R +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM0_CM_3DLUT_OUT_OFFSET_G +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM0_CM_3DLUT_OUT_OFFSET_B +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//CM0_CM_TEST_DEBUG_INDEX +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM0_CM_TEST_DEBUG_DATA +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON11_PERFCOUNTER_CNTL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_CNTL2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_STATE +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON11_PERFMON_CNTL +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON11_PERFMON_CNTL2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON11_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON11_PERFMON_CVALUE_LOW +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON11_PERFMON_HI +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFMON_LOW +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +//DPP_TOP1_DPP_CONTROL +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L +//DPP_TOP1_DPP_SOFT_RESET +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP1_DPP_CRC_VAL_R_G +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_VAL_B_A +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP1_DPP_CRC_CTRL +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP1_HOST_READ_CONTROL +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//CNVC_CFG1_FORMAT_CONTROL +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +//CNVC_CFG1_FCNV_FP_BIAS_R +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_G +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_B +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_R +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_G +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_B +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG1_COLOR_KEYER_CONTROL +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG1_COLOR_KEYER_ALPHA +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_RED +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_GREEN +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_BLUE +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec +//CNVC_CUR1_CURSOR0_CONTROL +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR1_CURSOR0_COLOR0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_COLOR1 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +//DSCL1_SCL_COEF_RAM_TAP_SELECT +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL1_SCL_COEF_RAM_TAP_DATA +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL1_SCL_MODE +#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL1_SCL_TAP_CONTROL +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL1_DSCL_CONTROL +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL1_DSCL_2TAP_CONTROL +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL1_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT_C +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT_C +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL1_SCL_BLACK_OFFSET +#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 +#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 +#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL +#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L +//DSCL1_DSCL_UPDATE +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL1_DSCL_AUTOCAL +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL1_OTG_H_BLANK +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL1_OTG_V_BLANK +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL1_RECOUT_START +#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL1_RECOUT_SIZE +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL1_MPC_SIZE +#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL1_LB_DATA_FORMAT +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL1_LB_MEMORY_CTRL +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL1_LB_V_COUNTER +#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL1_DSCL_MEM_PWR_CTRL +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL1_DSCL_MEM_PWR_STATUS +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL1_OBUF_CONTROL +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L +//DSCL1_OBUF_MEM_PWR_CTRL +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +//CM1_CM_CONTROL +#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM1_CM_ICSC_CONTROL +#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 +#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L +//CM1_CM_ICSC_C11_C12 +#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 +#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 +#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L +//CM1_CM_ICSC_C13_C14 +#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 +#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 +#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L +//CM1_CM_ICSC_C21_C22 +#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 +#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 +#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L +//CM1_CM_ICSC_C23_C24 +#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 +#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 +#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L +//CM1_CM_ICSC_C31_C32 +#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 +#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 +#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L +//CM1_CM_ICSC_C33_C34 +#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 +#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 +#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL +#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L +//CM1_CM_ICSC_B_C11_C12 +#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0 +#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10 +#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL +#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L +//CM1_CM_ICSC_B_C13_C14 +#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0 +#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10 +#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL +#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L +//CM1_CM_ICSC_B_C21_C22 +#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0 +#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10 +#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL +#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L +//CM1_CM_ICSC_B_C23_C24 +#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0 +#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10 +#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL +#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L +//CM1_CM_ICSC_B_C31_C32 +#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0 +#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10 +#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL +#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L +//CM1_CM_ICSC_B_C33_C34 +#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0 +#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10 +#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL +#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_CONTROL +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +//CM1_CM_GAMUT_REMAP_C11_C12 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C13_C14 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C21_C22 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C23_C24 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C31_C32 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_C33_C34 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C11_C12 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C13_C14 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C21_C22 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C23_C24 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C31_C32 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM1_CM_GAMUT_REMAP_B_C33_C34 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM1_CM_BIAS_CR_R +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM1_CM_BIAS_Y_G_CB_B +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM1_CM_DGAM_CONTROL +#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 +#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L +//CM1_CM_DGAM_LUT_INDEX +#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_DGAM_LUT_DATA +#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 +#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL +//CM1_CM_DGAM_LUT_WRITE_EN_MASK +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L +#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L +//CM1_CM_DGAM_RAMA_START_CNTL_B +#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_DGAM_RAMA_START_CNTL_G +#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_DGAM_RAMA_START_CNTL_R +#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_DGAM_RAMA_SLOPE_CNTL_B +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMA_SLOPE_CNTL_G +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMA_SLOPE_CNTL_R +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMA_END_CNTL1_B +#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMA_END_CNTL2_B +#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMA_END_CNTL1_G +#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMA_END_CNTL2_G +#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMA_END_CNTL1_R +#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMA_END_CNTL2_R +#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMA_REGION_0_1 +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_2_3 +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_4_5 +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_6_7 +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_8_9 +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_10_11 +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_12_13 +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMA_REGION_14_15 +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_START_CNTL_B +#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_DGAM_RAMB_START_CNTL_G +#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_DGAM_RAMB_START_CNTL_R +#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_DGAM_RAMB_SLOPE_CNTL_B +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMB_SLOPE_CNTL_G +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMB_SLOPE_CNTL_R +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_DGAM_RAMB_END_CNTL1_B +#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMB_END_CNTL2_B +#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMB_END_CNTL1_G +#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMB_END_CNTL2_G +#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMB_END_CNTL1_R +#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM1_CM_DGAM_RAMB_END_CNTL2_R +#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM1_CM_DGAM_RAMB_REGION_0_1 +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_2_3 +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_4_5 +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_6_7 +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_8_9 +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_10_11 +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_12_13 +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_DGAM_RAMB_REGION_14_15 +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_CONTROL +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0 +#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L +//CM1_CM_BLNDGAM_LUT_INDEX +#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_BLNDGAM_LUT_DATA +#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL +//CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK +#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B +#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G +#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R +#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B +#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G +#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R +#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM1_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_HDR_MULT_COEF +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM1_CM_MEM_PWR_CTRL +#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM1_CM_MEM_PWR_STATUS +#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM1_CM_DEALPHA +#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +//CM1_CM_COEF_FORMAT +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4 +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L +#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM1_CM_SHAPER_CONTROL +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +//CM1_CM_SHAPER_OFFSET_R +#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_SHAPER_OFFSET_G +#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_SHAPER_OFFSET_B +#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_SHAPER_SCALE_R +#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM1_CM_SHAPER_SCALE_G_B +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM1_CM_SHAPER_LUT_INDEX +#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM1_CM_SHAPER_LUT_DATA +#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM1_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8 +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L +//CM1_CM_SHAPER_RAMA_START_CNTL_B +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_START_CNTL_G +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_START_CNTL_R +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMA_END_CNTL_B +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_END_CNTL_G +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_END_CNTL_R +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMA_REGION_0_1 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_2_3 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_4_5 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_6_7 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_8_9 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_10_11 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_12_13 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_14_15 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_16_17 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_18_19 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_20_21 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_22_23 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_24_25 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_26_27 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_28_29 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_30_31 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMA_REGION_32_33 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_START_CNTL_B +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_START_CNTL_G +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_START_CNTL_R +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_SHAPER_RAMB_END_CNTL_B +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_END_CNTL_G +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_END_CNTL_R +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM1_CM_SHAPER_RAMB_REGION_0_1 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_2_3 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_4_5 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_6_7 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_8_9 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_10_11 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_12_13 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_14_15 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_16_17 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_18_19 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_20_21 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_22_23 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_24_25 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_26_27 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_28_29 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_30_31 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_SHAPER_RAMB_REGION_32_33 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_MEM_PWR_CTRL2 +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM1_CM_MEM_PWR_STATUS2 +#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM1_CM_3DLUT_MODE +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +//CM1_CM_3DLUT_INDEX +#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM1_CM_3DLUT_DATA +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM1_CM_3DLUT_DATA_30BIT +#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM1_CM_3DLUT_READ_WRITE_CONTROL +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L +#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM1_CM_3DLUT_OUT_NORM_FACTOR +#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM1_CM_3DLUT_OUT_OFFSET_R +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM1_CM_3DLUT_OUT_OFFSET_G +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM1_CM_3DLUT_OUT_OFFSET_B +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//CM1_CM_TEST_DEBUG_INDEX +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM1_CM_TEST_DEBUG_DATA +#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON12_PERFCOUNTER_CNTL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_CNTL2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_STATE +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON12_PERFMON_CNTL +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON12_PERFMON_CNTL2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON12_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON12_PERFMON_CVALUE_LOW +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON12_PERFMON_HI +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFMON_LOW +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +//DPP_TOP2_DPP_CONTROL +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L +//DPP_TOP2_DPP_SOFT_RESET +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP2_DPP_CRC_VAL_R_G +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_VAL_B_A +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP2_DPP_CRC_CTRL +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP2_HOST_READ_CONTROL +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//CNVC_CFG2_FORMAT_CONTROL +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +//CNVC_CFG2_FCNV_FP_BIAS_R +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_G +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_B +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_R +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_G +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_B +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG2_COLOR_KEYER_CONTROL +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG2_COLOR_KEYER_ALPHA +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_RED +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_GREEN +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_BLUE +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_ALPHA_2BIT_LUT +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec +//CNVC_CUR2_CURSOR0_CONTROL +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR2_CURSOR0_COLOR0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_COLOR1 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +//DSCL2_SCL_COEF_RAM_TAP_SELECT +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL2_SCL_COEF_RAM_TAP_DATA +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL2_SCL_MODE +#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL2_SCL_TAP_CONTROL +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL2_DSCL_CONTROL +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL2_DSCL_2TAP_CONTROL +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL2_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT_C +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT_C +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL2_SCL_BLACK_OFFSET +#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 +#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 +#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL +#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L +//DSCL2_DSCL_UPDATE +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL2_DSCL_AUTOCAL +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL2_OTG_H_BLANK +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL2_OTG_V_BLANK +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL2_RECOUT_START +#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL2_RECOUT_SIZE +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL2_MPC_SIZE +#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL2_LB_DATA_FORMAT +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL2_LB_MEMORY_CTRL +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL2_LB_V_COUNTER +#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL2_DSCL_MEM_PWR_CTRL +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL2_DSCL_MEM_PWR_STATUS +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL2_OBUF_CONTROL +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L +//DSCL2_OBUF_MEM_PWR_CTRL +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +//CM2_CM_CONTROL +#define CM2_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM2_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM2_CM_ICSC_CONTROL +#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 +#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L +//CM2_CM_ICSC_C11_C12 +#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 +#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 +#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L +//CM2_CM_ICSC_C13_C14 +#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 +#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 +#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L +//CM2_CM_ICSC_C21_C22 +#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 +#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 +#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L +//CM2_CM_ICSC_C23_C24 +#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 +#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 +#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L +//CM2_CM_ICSC_C31_C32 +#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 +#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 +#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L +//CM2_CM_ICSC_C33_C34 +#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 +#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 +#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL +#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L +//CM2_CM_ICSC_B_C11_C12 +#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0 +#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10 +#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL +#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L +//CM2_CM_ICSC_B_C13_C14 +#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0 +#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10 +#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL +#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L +//CM2_CM_ICSC_B_C21_C22 +#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0 +#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10 +#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL +#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L +//CM2_CM_ICSC_B_C23_C24 +#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0 +#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10 +#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL +#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L +//CM2_CM_ICSC_B_C31_C32 +#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0 +#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10 +#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL +#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L +//CM2_CM_ICSC_B_C33_C34 +#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0 +#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10 +#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL +#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_CONTROL +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +//CM2_CM_GAMUT_REMAP_C11_C12 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C13_C14 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C21_C22 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C23_C24 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C31_C32 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_C33_C34 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C11_C12 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C13_C14 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C21_C22 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C23_C24 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C31_C32 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM2_CM_GAMUT_REMAP_B_C33_C34 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM2_CM_BIAS_CR_R +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM2_CM_BIAS_Y_G_CB_B +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM2_CM_DGAM_CONTROL +#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 +#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L +//CM2_CM_DGAM_LUT_INDEX +#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_DGAM_LUT_DATA +#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 +#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL +//CM2_CM_DGAM_LUT_WRITE_EN_MASK +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L +#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L +//CM2_CM_DGAM_RAMA_START_CNTL_B +#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_DGAM_RAMA_START_CNTL_G +#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_DGAM_RAMA_START_CNTL_R +#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_DGAM_RAMA_SLOPE_CNTL_B +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMA_SLOPE_CNTL_G +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMA_SLOPE_CNTL_R +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMA_END_CNTL1_B +#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMA_END_CNTL2_B +#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMA_END_CNTL1_G +#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMA_END_CNTL2_G +#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMA_END_CNTL1_R +#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMA_END_CNTL2_R +#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMA_REGION_0_1 +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_2_3 +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_4_5 +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_6_7 +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_8_9 +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_10_11 +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_12_13 +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMA_REGION_14_15 +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_START_CNTL_B +#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_DGAM_RAMB_START_CNTL_G +#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_DGAM_RAMB_START_CNTL_R +#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_DGAM_RAMB_SLOPE_CNTL_B +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMB_SLOPE_CNTL_G +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMB_SLOPE_CNTL_R +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_DGAM_RAMB_END_CNTL1_B +#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMB_END_CNTL2_B +#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMB_END_CNTL1_G +#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMB_END_CNTL2_G +#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMB_END_CNTL1_R +#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM2_CM_DGAM_RAMB_END_CNTL2_R +#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM2_CM_DGAM_RAMB_REGION_0_1 +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_2_3 +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_4_5 +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_6_7 +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_8_9 +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_10_11 +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_12_13 +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_DGAM_RAMB_REGION_14_15 +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_CONTROL +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0 +#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L +//CM2_CM_BLNDGAM_LUT_INDEX +#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_BLNDGAM_LUT_DATA +#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL +//CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK +#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L +//CM2_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B +#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G +#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R +#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B +#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G +#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R +#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM2_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_HDR_MULT_COEF +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM2_CM_MEM_PWR_CTRL +#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 +#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L +#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM2_CM_MEM_PWR_STATUS +#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM2_CM_DEALPHA +#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +//CM2_CM_COEF_FORMAT +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4 +#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L +#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM2_CM_SHAPER_CONTROL +#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +//CM2_CM_SHAPER_OFFSET_R +#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_SHAPER_OFFSET_G +#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_SHAPER_OFFSET_B +#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_SHAPER_SCALE_R +#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM2_CM_SHAPER_SCALE_G_B +#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM2_CM_SHAPER_LUT_INDEX +#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM2_CM_SHAPER_LUT_DATA +#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM2_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8 +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L +//CM2_CM_SHAPER_RAMA_START_CNTL_B +#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMA_START_CNTL_G +#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMA_START_CNTL_R +#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMA_END_CNTL_B +#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMA_END_CNTL_G +#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMA_END_CNTL_R +#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMA_REGION_0_1 +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_2_3 +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_4_5 +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_6_7 +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_8_9 +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_10_11 +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_12_13 +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_14_15 +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_16_17 +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_18_19 +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_20_21 +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_22_23 +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_24_25 +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_26_27 +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_28_29 +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_30_31 +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMA_REGION_32_33 +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_START_CNTL_B +#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMB_START_CNTL_G +#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMB_START_CNTL_R +#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_SHAPER_RAMB_END_CNTL_B +#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMB_END_CNTL_G +#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMB_END_CNTL_R +#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM2_CM_SHAPER_RAMB_REGION_0_1 +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_2_3 +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_4_5 +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_6_7 +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_8_9 +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_10_11 +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_12_13 +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_14_15 +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_16_17 +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_18_19 +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_20_21 +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_22_23 +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_24_25 +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_26_27 +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_28_29 +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_30_31 +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_SHAPER_RAMB_REGION_32_33 +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_MEM_PWR_CTRL2 +#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM2_CM_MEM_PWR_STATUS2 +#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM2_CM_3DLUT_MODE +#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +//CM2_CM_3DLUT_INDEX +#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM2_CM_3DLUT_DATA +#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM2_CM_3DLUT_DATA_30BIT +#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM2_CM_3DLUT_READ_WRITE_CONTROL +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L +#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM2_CM_3DLUT_OUT_NORM_FACTOR +#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM2_CM_3DLUT_OUT_OFFSET_R +#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM2_CM_3DLUT_OUT_OFFSET_G +#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM2_CM_3DLUT_OUT_OFFSET_B +#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//CM2_CM_TEST_DEBUG_INDEX +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM2_CM_TEST_DEBUG_DATA +#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON13_PERFCOUNTER_CNTL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_CNTL2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_STATE +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON13_PERFMON_CNTL +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON13_PERFMON_CNTL2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON13_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON13_PERFMON_CVALUE_LOW +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON13_PERFMON_HI +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFMON_LOW +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +//DPP_TOP3_DPP_CONTROL +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x14 +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00100000L +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0xF0000000L +//DPP_TOP3_DPP_SOFT_RESET +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +//DPP_TOP3_DPP_CRC_VAL_R_G +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_VAL_B_A +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK 0x0000FFFFL +#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK 0xFFFF0000L +//DPP_TOP3_DPP_CRC_CTRL +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT 0x6 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x7 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x8 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0xa +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xc +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT 0xf +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK 0x00000040L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000080L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000300L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000C00L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00007000L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK 0x00008000L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP3_HOST_READ_CONTROL +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +//CNVC_CFG3_FORMAT_CONTROL +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +//CNVC_CFG3_FCNV_FP_BIAS_R +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_G +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_B +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_R +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_G +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_B +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG3_COLOR_KEYER_CONTROL +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG3_COLOR_KEYER_ALPHA +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_RED +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_GREEN +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_BLUE +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_ALPHA_2BIT_LUT +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT 0x8 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT 0x10 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT 0x18 +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK 0x000000FFL +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK 0x0000FF00L +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK 0x00FF0000L +#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec +//CNVC_CUR3_CURSOR0_CONTROL +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CNVC_CUR3_CURSOR0_COLOR0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_COLOR1 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT 0x0 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT 0x10 +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK 0x0000FFFFL +#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +//DSCL3_SCL_COEF_RAM_TAP_SELECT +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL3_SCL_COEF_RAM_TAP_DATA +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL3_SCL_MODE +#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL3_SCL_TAP_CONTROL +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL3_DSCL_CONTROL +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL3_DSCL_2TAP_CONTROL +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL3_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT_C +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x03FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT_C +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL3_SCL_BLACK_OFFSET +#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT 0x0 +#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT 0x10 +#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK 0x0000FFFFL +#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK 0xFFFF0000L +//DSCL3_DSCL_UPDATE +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL3_DSCL_AUTOCAL +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1FFF0000L +//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1FFF0000L +//DSCL3_OTG_H_BLANK +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL3_OTG_V_BLANK +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL3_RECOUT_START +#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00001FFFL +#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x1FFF0000L +//DSCL3_RECOUT_SIZE +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL3_MPC_SIZE +#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL3_LB_DATA_FORMAT +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL3_LB_MEMORY_CTRL +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL3_LB_V_COUNTER +#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL3_DSCL_MEM_PWR_CTRL +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL3_DSCL_MEM_PWR_STATUS +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL3_OBUF_CONTROL +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x4 +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0xc +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x1c +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000010L +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00001000L +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0xF0000000L +//DSCL3_OBUF_MEM_PWR_CTRL +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +//CM3_CM_CONTROL +#define CM3_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM3_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM3_CM_ICSC_CONTROL +#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT 0x0 +#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK 0x00000003L +//CM3_CM_ICSC_C11_C12 +#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT 0x0 +#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT 0x10 +#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12_MASK 0xFFFF0000L +//CM3_CM_ICSC_C13_C14 +#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT 0x0 +#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT 0x10 +#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14_MASK 0xFFFF0000L +//CM3_CM_ICSC_C21_C22 +#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT 0x0 +#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT 0x10 +#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22_MASK 0xFFFF0000L +//CM3_CM_ICSC_C23_C24 +#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT 0x0 +#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT 0x10 +#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24_MASK 0xFFFF0000L +//CM3_CM_ICSC_C31_C32 +#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT 0x0 +#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT 0x10 +#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32_MASK 0xFFFF0000L +//CM3_CM_ICSC_C33_C34 +#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT 0x0 +#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT 0x10 +#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33_MASK 0x0000FFFFL +#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34_MASK 0xFFFF0000L +//CM3_CM_ICSC_B_C11_C12 +#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT 0x0 +#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT 0x10 +#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK 0x0000FFFFL +#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK 0xFFFF0000L +//CM3_CM_ICSC_B_C13_C14 +#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT 0x0 +#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT 0x10 +#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK 0x0000FFFFL +#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK 0xFFFF0000L +//CM3_CM_ICSC_B_C21_C22 +#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT 0x0 +#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT 0x10 +#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK 0x0000FFFFL +#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK 0xFFFF0000L +//CM3_CM_ICSC_B_C23_C24 +#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT 0x0 +#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT 0x10 +#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK 0x0000FFFFL +#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK 0xFFFF0000L +//CM3_CM_ICSC_B_C31_C32 +#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT 0x0 +#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT 0x10 +#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK 0x0000FFFFL +#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK 0xFFFF0000L +//CM3_CM_ICSC_B_C33_C34 +#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT 0x0 +#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT 0x10 +#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK 0x0000FFFFL +#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_CONTROL +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK 0x00000003L +//CM3_CM_GAMUT_REMAP_C11_C12 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C13_C14 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C21_C22 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C23_C24 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C31_C32 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_C33_C34 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C11_C12 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C13_C14 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C21_C22 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C23_C24 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C31_C32 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK 0xFFFF0000L +//CM3_CM_GAMUT_REMAP_B_C33_C34 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT 0x0 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT 0x10 +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK 0x0000FFFFL +#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK 0xFFFF0000L +//CM3_CM_BIAS_CR_R +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM3_CM_BIAS_Y_G_CB_B +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM3_CM_DGAM_CONTROL +#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT 0x0 +#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK 0x00000007L +//CM3_CM_DGAM_LUT_INDEX +#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_DGAM_LUT_DATA +#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT 0x0 +#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK 0x0007FFFFL +//CM3_CM_DGAM_LUT_WRITE_EN_MASK +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT 0xc +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK 0x00000700L +#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK 0x00001000L +//CM3_CM_DGAM_RAMA_START_CNTL_B +#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_DGAM_RAMA_START_CNTL_G +#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_DGAM_RAMA_START_CNTL_R +#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_DGAM_RAMA_SLOPE_CNTL_B +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMA_SLOPE_CNTL_G +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMA_SLOPE_CNTL_R +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMA_END_CNTL1_B +#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMA_END_CNTL2_B +#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMA_END_CNTL1_G +#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMA_END_CNTL2_G +#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMA_END_CNTL1_R +#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMA_END_CNTL2_R +#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMA_REGION_0_1 +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_2_3 +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_4_5 +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_6_7 +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_8_9 +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_10_11 +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_12_13 +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMA_REGION_14_15 +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_START_CNTL_B +#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_DGAM_RAMB_START_CNTL_G +#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_DGAM_RAMB_START_CNTL_R +#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_DGAM_RAMB_SLOPE_CNTL_B +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMB_SLOPE_CNTL_G +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMB_SLOPE_CNTL_R +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_DGAM_RAMB_END_CNTL1_B +#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMB_END_CNTL2_B +#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMB_END_CNTL1_G +#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMB_END_CNTL2_G +#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMB_END_CNTL1_R +#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM3_CM_DGAM_RAMB_END_CNTL2_R +#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM3_CM_DGAM_RAMB_REGION_0_1 +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_2_3 +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_4_5 +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_6_7 +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_8_9 +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_10_11 +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_12_13 +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_DGAM_RAMB_REGION_14_15 +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_CONTROL +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT 0x0 +#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK 0x00000003L +//CM3_CM_BLNDGAM_LUT_INDEX +#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_BLNDGAM_LUT_DATA +#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT 0x0 +#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK 0x0007FFFFL +//CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK +#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT 0x4 +#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT 0x8 +#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK 0x00000010L +#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK 0x00000300L +//CM3_CM_BLNDGAM_RAMA_START_CNTL_B +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMA_START_CNTL_G +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMA_START_CNTL_R +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B +#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G +#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R +#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMA_REGION_0_1 +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_2_3 +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_4_5 +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_6_7 +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_8_9 +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_10_11 +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_12_13 +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_14_15 +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_16_17 +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_18_19 +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_20_21 +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_22_23 +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_24_25 +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_26_27 +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_28_29 +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_30_31 +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMA_REGION_32_33 +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_START_CNTL_B +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMB_START_CNTL_G +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMB_START_CNTL_R +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B +#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G +#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R +#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//CM3_CM_BLNDGAM_RAMB_REGION_0_1 +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_2_3 +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_4_5 +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_6_7 +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_8_9 +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_10_11 +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_12_13 +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_14_15 +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_16_17 +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_18_19 +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_20_21 +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_22_23 +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_24_25 +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_26_27 +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_28_29 +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_30_31 +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_BLNDGAM_RAMB_REGION_32_33 +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_HDR_MULT_COEF +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM3_CM_MEM_PWR_CTRL +#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT 0x2 +#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT 0x4 +#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT 0x6 +#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK 0x00000004L +#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK 0x00000030L +#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK 0x00000040L +//CM3_CM_MEM_PWR_STATUS +#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT 0x2 +#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK 0x0000000CL +//CM3_CM_DEALPHA +#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +//CM3_CM_COEF_FORMAT +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT 0x4 +#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x8 +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK 0x00000010L +#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000100L +//CM3_CM_SHAPER_CONTROL +#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT 0x0 +#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK 0x00000003L +//CM3_CM_SHAPER_OFFSET_R +#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT 0x0 +#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_SHAPER_OFFSET_G +#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT 0x0 +#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_SHAPER_OFFSET_B +#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT 0x0 +#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_SHAPER_SCALE_R +#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT 0x0 +#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//CM3_CM_SHAPER_SCALE_G_B +#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT 0x0 +#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT 0x10 +#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//CM3_CM_SHAPER_LUT_INDEX +#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//CM3_CM_SHAPER_LUT_DATA +#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT 0x0 +#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//CM3_CM_SHAPER_LUT_WRITE_EN_MASK +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT 0x8 +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK 0x00000300L +//CM3_CM_SHAPER_RAMA_START_CNTL_B +#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMA_START_CNTL_G +#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMA_START_CNTL_R +#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMA_END_CNTL_B +#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMA_END_CNTL_G +#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMA_END_CNTL_R +#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMA_REGION_0_1 +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_2_3 +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_4_5 +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_6_7 +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_8_9 +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_10_11 +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_12_13 +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_14_15 +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_16_17 +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_18_19 +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_20_21 +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_22_23 +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_24_25 +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_26_27 +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_28_29 +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_30_31 +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMA_REGION_32_33 +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_START_CNTL_B +#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMB_START_CNTL_G +#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMB_START_CNTL_R +#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_SHAPER_RAMB_END_CNTL_B +#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMB_END_CNTL_G +#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMB_END_CNTL_R +#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//CM3_CM_SHAPER_RAMB_REGION_0_1 +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_2_3 +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_4_5 +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_6_7 +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_8_9 +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_10_11 +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_12_13 +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_14_15 +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_16_17 +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_18_19 +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_20_21 +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_22_23 +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_24_25 +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_26_27 +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_28_29 +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_30_31 +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_SHAPER_RAMB_REGION_32_33 +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_MEM_PWR_CTRL2 +#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT 0x8 +#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT 0xa +#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT 0xc +#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT 0xe +#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK 0x00000300L +#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK 0x00000400L +#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK 0x00003000L +#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK 0x00004000L +//CM3_CM_MEM_PWR_STATUS2 +#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT 0x4 +#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT 0x6 +#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK 0x00000030L +#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK 0x000000C0L +//CM3_CM_3DLUT_MODE +#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT 0x0 +#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT 0x4 +#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK 0x00000003L +#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK 0x00000010L +//CM3_CM_3DLUT_INDEX +#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT 0x0 +#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK 0x000007FFL +//CM3_CM_3DLUT_DATA +#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT 0x0 +#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT 0x10 +#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK 0x0000FFFFL +#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK 0xFFFF0000L +//CM3_CM_3DLUT_DATA_30BIT +#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//CM3_CM_3DLUT_READ_WRITE_CONTROL +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT 0x4 +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT 0x8 +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT 0xc +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT 0x10 +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK 0x00000010L +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK 0x00000100L +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK 0x00003000L +#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK 0x00030000L +//CM3_CM_3DLUT_OUT_NORM_FACTOR +#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//CM3_CM_3DLUT_OUT_OFFSET_R +#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//CM3_CM_3DLUT_OUT_OFFSET_G +#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//CM3_CM_3DLUT_OUT_OFFSET_B +#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//CM3_CM_TEST_DEBUG_INDEX +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM3_CM_TEST_DEBUG_DATA +#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON14_PERFCOUNTER_CNTL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_CNTL2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_STATE +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON14_PERFMON_CNTL +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON14_PERFMON_CNTL2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON14_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON14_PERFMON_CVALUE_LOW +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON14_PERFMON_HI +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFMON_LOW +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +//MPCC0_MPCC_TOP_SEL +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC0_MPCC_BOT_SEL +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC0_MPCC_OPP_ID +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC0_MPCC_CONTROL +#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC0_MPCC_SM_CONTROL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC0_MPCC_UPDATE_LOCK_SEL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC0_MPCC_TOP_GAIN +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_INSIDE +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_OUTSIDE +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BG_R_CR +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC0_MPCC_BG_G_Y +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC0_MPCC_BG_B_CB +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC0_MPCC_MEM_PWR_CTRL +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L +//MPCC0_MPCC_STALL_STATUS +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +//MPCC0_MPCC_STATUS +#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d +#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L +#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +//MPCC1_MPCC_TOP_SEL +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC1_MPCC_BOT_SEL +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC1_MPCC_OPP_ID +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC1_MPCC_CONTROL +#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC1_MPCC_SM_CONTROL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC1_MPCC_UPDATE_LOCK_SEL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC1_MPCC_TOP_GAIN +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_INSIDE +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_OUTSIDE +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BG_R_CR +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC1_MPCC_BG_G_Y +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC1_MPCC_BG_B_CB +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC1_MPCC_MEM_PWR_CTRL +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L +//MPCC1_MPCC_STALL_STATUS +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +//MPCC1_MPCC_STATUS +#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d +#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L +#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +//MPCC2_MPCC_TOP_SEL +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC2_MPCC_BOT_SEL +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC2_MPCC_OPP_ID +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC2_MPCC_CONTROL +#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC2_MPCC_SM_CONTROL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC2_MPCC_UPDATE_LOCK_SEL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC2_MPCC_TOP_GAIN +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_INSIDE +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_OUTSIDE +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_BG_R_CR +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC2_MPCC_BG_G_Y +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC2_MPCC_BG_B_CB +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC2_MPCC_MEM_PWR_CTRL +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L +//MPCC2_MPCC_STALL_STATUS +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +//MPCC2_MPCC_STATUS +#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d +#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L +#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +//MPCC3_MPCC_TOP_SEL +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC3_MPCC_BOT_SEL +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC3_MPCC_OPP_ID +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC3_MPCC_CONTROL +#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC3_MPCC_SM_CONTROL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC3_MPCC_UPDATE_LOCK_SEL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC3_MPCC_TOP_GAIN +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_INSIDE +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_OUTSIDE +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_BG_R_CR +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC3_MPCC_BG_G_Y +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC3_MPCC_BG_B_CB +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC3_MPCC_MEM_PWR_CTRL +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L +//MPCC3_MPCC_STALL_STATUS +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +//MPCC3_MPCC_STATUS +#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d +#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L +#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc4_dispdec +//MPCC4_MPCC_TOP_SEL +#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC4_MPCC_BOT_SEL +#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC4_MPCC_OPP_ID +#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC4_MPCC_CONTROL +#define MPCC4_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC4_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC4_MPCC_SM_CONTROL +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC4_MPCC_UPDATE_LOCK_SEL +#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC4_MPCC_TOP_GAIN +#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC4_MPCC_BOT_GAIN_INSIDE +#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC4_MPCC_BOT_GAIN_OUTSIDE +#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC4_MPCC_BG_R_CR +#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC4_MPCC_BG_G_Y +#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC4_MPCC_BG_B_CB +#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC4_MPCC_MEM_PWR_CTRL +#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 +#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L +//MPCC4_MPCC_STALL_STATUS +#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 +#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L +#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +//MPCC4_MPCC_STATUS +#define MPCC4_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC4_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC4_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d +#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC4_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC4_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC4_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L +#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L +#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc5_dispdec +//MPCC5_MPCC_TOP_SEL +#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC5_MPCC_BOT_SEL +#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC5_MPCC_OPP_ID +#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC5_MPCC_CONTROL +#define MPCC5_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC5_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC5_MPCC_SM_CONTROL +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC5_MPCC_UPDATE_LOCK_SEL +#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC5_MPCC_TOP_GAIN +#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC5_MPCC_BOT_GAIN_INSIDE +#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC5_MPCC_BOT_GAIN_OUTSIDE +#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC5_MPCC_BG_R_CR +#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC5_MPCC_BG_G_Y +#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC5_MPCC_BG_B_CB +#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC5_MPCC_MEM_PWR_CTRL +#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 +#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L +//MPCC5_MPCC_STALL_STATUS +#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 +#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L +#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +//MPCC5_MPCC_STATUS +#define MPCC5_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC5_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC5_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d +#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC5_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC5_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC5_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L +#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L +#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc6_dispdec +//MPCC6_MPCC_TOP_SEL +#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC6_MPCC_BOT_SEL +#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC6_MPCC_OPP_ID +#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC6_MPCC_CONTROL +#define MPCC6_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC6_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC6_MPCC_SM_CONTROL +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC6_MPCC_UPDATE_LOCK_SEL +#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC6_MPCC_TOP_GAIN +#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC6_MPCC_BOT_GAIN_INSIDE +#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC6_MPCC_BOT_GAIN_OUTSIDE +#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC6_MPCC_BG_R_CR +#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC6_MPCC_BG_G_Y +#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC6_MPCC_BG_B_CB +#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC6_MPCC_MEM_PWR_CTRL +#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 +#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L +//MPCC6_MPCC_STALL_STATUS +#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 +#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L +#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +//MPCC6_MPCC_STATUS +#define MPCC6_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC6_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC6_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d +#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC6_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC6_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC6_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L +#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L +#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpcc7_dispdec +//MPCC7_MPCC_TOP_SEL +#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC7_MPCC_BOT_SEL +#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC7_MPCC_OPP_ID +#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC7_MPCC_CONTROL +#define MPCC7_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT 0x10 +#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT 0x18 +#define MPCC7_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK 0x00FF0000L +#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK 0xFF000000L +//MPCC7_MPCC_SM_CONTROL +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC7_MPCC_UPDATE_LOCK_SEL +#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC7_MPCC_TOP_GAIN +#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC7_MPCC_BOT_GAIN_INSIDE +#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC7_MPCC_BOT_GAIN_OUTSIDE +#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC7_MPCC_BG_R_CR +#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC7_MPCC_BG_G_Y +#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC7_MPCC_BG_B_CB +#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC7_MPCC_MEM_PWR_CTRL +#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x4 +#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000030L +//MPCC7_MPCC_STALL_STATUS +#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT 0x0 +#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT 0x4 +#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT 0x8 +#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT 0xc +#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK 0x00000001L +#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK 0x00000010L +#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK 0x00000100L +#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK 0x00001000L +//MPCC7_MPCC_STATUS +#define MPCC7_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC7_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC7_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT 0x1d +#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT 0x1e +#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT 0x1f +#define MPCC7_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC7_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC7_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L +#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK 0x20000000L +#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK 0x40000000L +#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK 0x80000000L + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +//MPC_CLOCK_CONTROL +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x1 +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0x4 +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000002L +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x00000030L +//MPC_SOFT_RESET +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 +#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L +#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L +//MPC_CRC_CTRL +#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//MPC_CRC_SEL_CONTROL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L +//MPC_CRC_RESULT_AR +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT 0x0 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT 0x10 +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK 0xFFFF0000L +//MPC_CRC_RESULT_GB +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT 0x0 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT 0x10 +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK 0x0000FFFFL +#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK 0xFFFF0000L +//MPC_CRC_RESULT_C +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT 0x0 +#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK 0x0000FFFFL +//MPC_PERFMON_EVENT_CTRL +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0 +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L +//MPC_BYPASS_BG_AR +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//MPC_BYPASS_BG_GB +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//MPC_STALL_GRACE_WINDOW +#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD__SHIFT 0x0 +#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD_MASK 0x000000FFL +//MPC_HOST_READ_CONTROL +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//MPC_PENDING_TAKEN_STATUS_REG1 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN__SHIFT 0x1 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x2 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN__SHIFT 0x3 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x4 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN__SHIFT 0x5 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x6 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN__SHIFT 0x7 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x8 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN__SHIFT 0x9 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0xa +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN__SHIFT 0xb +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT 0xc +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN__SHIFT 0xd +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT 0xe +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN__SHIFT 0xf +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT 0x10 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN__SHIFT 0x11 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT 0x12 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN__SHIFT 0x13 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT 0x14 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN__SHIFT 0x15 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT 0x16 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN__SHIFT 0x17 +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN_MASK 0x00000002L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000004L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN_MASK 0x00000008L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000010L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN_MASK 0x00000020L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000040L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN_MASK 0x00000080L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000100L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN_MASK 0x00000200L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000400L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN_MASK 0x00000800L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING_MASK 0x00001000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN_MASK 0x00002000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING_MASK 0x00004000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN_MASK 0x00008000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING_MASK 0x00010000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN_MASK 0x00020000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING_MASK 0x00040000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN_MASK 0x00080000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING_MASK 0x00100000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN_MASK 0x00200000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING_MASK 0x00400000L +#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN_MASK 0x00800000L +//MPC_PENDING_TAKEN_STATUS_REG3 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN__SHIFT 0x1 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x2 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN__SHIFT 0x3 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT 0x4 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN__SHIFT 0x5 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT 0x6 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN__SHIFT 0x7 +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0xc +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN__SHIFT 0xd +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0xe +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN__SHIFT 0xf +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING__SHIFT 0x10 +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN__SHIFT 0x11 +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING__SHIFT 0x12 +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN__SHIFT 0x13 +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN_MASK 0x00000002L +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000004L +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN_MASK 0x00000008L +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK 0x00000010L +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN_MASK 0x00000020L +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK 0x00000040L +#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN_MASK 0x00000080L +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00001000L +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN_MASK 0x00002000L +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00004000L +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN_MASK 0x00008000L +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING_MASK 0x00010000L +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN_MASK 0x00020000L +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING_MASK 0x00040000L +#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN_MASK 0x00080000L +//MPC_UPDATE_ACK_REG5 +#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK__SHIFT 0x0 +#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK__SHIFT 0x1 +#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK__SHIFT 0x2 +#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK__SHIFT 0x3 +#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK__SHIFT 0x4 +#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK__SHIFT 0x5 +#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK__SHIFT 0x6 +#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK__SHIFT 0x7 +#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK__SHIFT 0x8 +#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK__SHIFT 0x9 +#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK__SHIFT 0xa +#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK__SHIFT 0xb +#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK__SHIFT 0xf +#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK__SHIFT 0x10 +#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK__SHIFT 0x11 +#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK__SHIFT 0x12 +#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK__SHIFT 0x14 +#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK__SHIFT 0x15 +#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK__SHIFT 0x16 +#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK__SHIFT 0x17 +#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK_MASK 0x00000001L +#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK_MASK 0x00000002L +#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK_MASK 0x00000004L +#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK_MASK 0x00000008L +#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK_MASK 0x00000010L +#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK_MASK 0x00000020L +#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK_MASK 0x00000040L +#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK_MASK 0x00000080L +#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK_MASK 0x00000100L +#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK_MASK 0x00000200L +#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK_MASK 0x00000400L +#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK_MASK 0x00000800L +#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK_MASK 0x00008000L +#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK_MASK 0x00010000L +#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK_MASK 0x00020000L +#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK_MASK 0x00040000L +#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK_MASK 0x00100000L +#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK_MASK 0x00200000L +#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK_MASK 0x00400000L +#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK_MASK 0x00800000L +//ADR_CFG_CUR_VUPDATE_LOCK_SET0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET1 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET1 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET1 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET1 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET1 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET2 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET2 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET2 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET2 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET2 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET3 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET3 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET3 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET3 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET3 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//MPC_OUT0_MUX +#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL +//MPC_OUT0_DENORM_CONTROL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT0_DENORM_CLAMP_G_Y +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT0_DENORM_CLAMP_B_CB +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT1_MUX +#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL +//MPC_OUT1_DENORM_CONTROL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT1_DENORM_CLAMP_G_Y +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT1_DENORM_CLAMP_B_CB +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT2_MUX +#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL +//MPC_OUT2_DENORM_CONTROL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT2_DENORM_CLAMP_G_Y +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT2_DENORM_CLAMP_B_CB +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT3_MUX +#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL +//MPC_OUT3_DENORM_CONTROL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT3_DENORM_CLAMP_G_Y +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT3_DENORM_CLAMP_B_CB +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +//MPCC_OGAM0_MPCC_OGAM_MODE +#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L +//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM0_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 +#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L +#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +//MPCC_OGAM1_MPCC_OGAM_MODE +#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L +//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM1_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 +#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L +#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +//MPCC_OGAM2_MPCC_OGAM_MODE +#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L +//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM2_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 +#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L +#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +//MPCC_OGAM3_MPCC_OGAM_MODE +#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L +//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM3_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 +#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L +#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec +//MPCC_OGAM4_MPCC_OGAM_MODE +#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L +//MPCC_OGAM4_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM4_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL +//MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL +#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 +#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 +#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L +#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L +//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B +#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G +#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R +#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B +#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G +#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R +#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec +//MPCC_OGAM5_MPCC_OGAM_MODE +#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L +//MPCC_OGAM5_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM5_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL +//MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL +#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 +#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 +#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L +#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L +//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B +#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G +#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R +#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B +#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G +#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R +#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec +//MPCC_OGAM6_MPCC_OGAM_MODE +#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L +//MPCC_OGAM6_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM6_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL +//MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL +#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 +#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 +#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L +#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L +//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B +#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G +#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R +#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B +#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G +#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R +#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec +//MPCC_OGAM7_MPCC_OGAM_MODE +#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK 0x00000003L +//MPCC_OGAM7_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM7_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0007FFFFL +//MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL +#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT 0x3 +#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT 0x4 +#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK 0x00000008L +#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK 0x00000030L +//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B +#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G +#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R +#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B +#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G +#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R +#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0x0000FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0xFFFF0000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0x0000FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0xFFFF0000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0x0000FFFFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0xFFFF0000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +//MPC_OUT_CSC_COEF_FORMAT +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT 0x2 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT 0x3 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK 0x00000004L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK 0x00000008L +//MPC_OUT0_CSC_MODE +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +//MPC_OUT0_CSC_C11_C12_A +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_A +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_A +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_A +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_A +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_A +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C11_C12_B +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_B +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_B +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_B +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_B +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_B +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_MODE +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +//MPC_OUT1_CSC_C11_C12_A +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_A +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_A +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_A +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_A +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_A +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C11_C12_B +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_B +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_B +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_B +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_B +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_B +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_MODE +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +//MPC_OUT2_CSC_C11_C12_A +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_A +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_A +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_A +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_A +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_A +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C11_C12_B +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_B +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_B +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_B +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_B +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_B +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_MODE +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +//MPC_OUT3_CSC_C11_C12_A +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_A +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_A +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_A +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_A +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_A +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C11_C12_B +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_B +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_B +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_B +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_B +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_B +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON15_PERFCOUNTER_CNTL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_CNTL2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_STATE +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON15_PERFMON_CNTL +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON15_PERFMON_CNTL2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON15_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON15_PERFMON_CVALUE_LOW +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON15_PERFMON_HI +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFMON_LOW +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_abm0_dispdec +//BL1_PWM_AMBIENT_LIGHT_LEVEL +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//BL1_PWM_USER_LEVEL +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//BL1_PWM_TARGET_ABM_LEVEL +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//BL1_PWM_CURRENT_ABM_LEVEL +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//BL1_PWM_FINAL_DUTY_CYCLE +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//BL1_PWM_MINIMUM_DUTY_CYCLE +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//BL1_PWM_ABM_CNTL +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//BL1_PWM_GRP2_REG_LOCK +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//DC_ABM1_CNTL +#define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 +#define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L +//DC_ABM1_IPCSC_COEFF_SEL +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000FL +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000F00L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000F0000L +#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//DC_ABM1_ACE_OFFSET_SLOPE_0 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007FFFL +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07FF0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L +//DC_ABM1_ACE_OFFSET_SLOPE_1 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007FFFL +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07FF0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L +//DC_ABM1_ACE_OFFSET_SLOPE_2 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007FFFL +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07FF0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L +//DC_ABM1_ACE_OFFSET_SLOPE_3 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007FFFL +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07FF0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L +//DC_ABM1_ACE_OFFSET_SLOPE_4 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007FFFL +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07FF0000L +#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L +//DC_ABM1_ACE_THRES_12 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003FFL +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03FF0000L +#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L +//DC_ABM1_ACE_THRES_34 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003FFL +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03FF0000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L +//DC_ABM1_ACE_CNTL_MISC +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//DC_ABM1_HGLS_REG_READ_PROGRESS +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//DC_ABM1_HG_MISC_CTRL +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L +#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//DC_ABM1_LS_SUM_OF_LUMA +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//DC_ABM1_LS_MIN_MAX_LUMA +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003FFL +#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03FF0000L +//DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003FFL +#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03FF0000L +//DC_ABM1_LS_PIXEL_COUNT +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x18 +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0xFF000000L +//DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003FFL +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03FF0000L +#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//DC_ABM1_HG_SAMPLE_RATE +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//DC_ABM1_LS_SAMPLE_RATE +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00FF0000L +#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L +//DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_1 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_2 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_3 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_4 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_5 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_6 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_7 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_8 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_9 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_10 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_11 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_12 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_13 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_14 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_15 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_16 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_17 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_18 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_19 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_20 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_21 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_22 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_23 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xFFFFFFFFL +//DC_ABM1_HG_RESULT_24 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 +#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xFFFFFFFFL +//DC_ABM1_BL_MASTER_LOCK +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_fmt0_dispdec +//FMT0_FMT_CLAMP_COMPONENT_R +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_G +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_B +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT0_FMT_DYNAMIC_EXP_CNTL +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT0_FMT_CONTROL +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L +//FMT0_FMT_BIT_DEPTH_CONTROL +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT0_FMT_DITHER_RAND_R_SEED +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_G_SEED +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_B_SEED +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_CNTL +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT0_FMT_MAP420_MEMORY_CONTROL +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT0_FMT_422_CONTROL +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg0_dispdec +//DPG0_DPG_CONTROL +#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG0_DPG_RAMP_CONTROL +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG0_DPG_DIMENSIONS +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_COLOUR_R_CR +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_G_Y +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_B_CB +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG0_DPG_OFFSET_SEGMENT +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_STATUS +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +//OPPBUF0_OPPBUF_CONTROL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF0_OPPBUF_CONTROL1 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +//OPP_PIPE0_OPP_PIPE_CONTROL +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt1_dispdec +//FMT1_FMT_CLAMP_COMPONENT_R +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_G +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_B +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT1_FMT_DYNAMIC_EXP_CNTL +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT1_FMT_CONTROL +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L +//FMT1_FMT_BIT_DEPTH_CONTROL +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT1_FMT_DITHER_RAND_R_SEED +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_G_SEED +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_B_SEED +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_CNTL +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT1_FMT_MAP420_MEMORY_CONTROL +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT1_FMT_422_CONTROL +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg1_dispdec +//DPG1_DPG_CONTROL +#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG1_DPG_RAMP_CONTROL +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG1_DPG_DIMENSIONS +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_COLOUR_R_CR +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_G_Y +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_B_CB +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG1_DPG_OFFSET_SEGMENT +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_STATUS +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +//OPPBUF1_OPPBUF_CONTROL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF1_OPPBUF_CONTROL1 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +//OPP_PIPE1_OPP_PIPE_CONTROL +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt2_dispdec +//FMT2_FMT_CLAMP_COMPONENT_R +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_G +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_B +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT2_FMT_DYNAMIC_EXP_CNTL +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT2_FMT_CONTROL +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L +//FMT2_FMT_BIT_DEPTH_CONTROL +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT2_FMT_DITHER_RAND_R_SEED +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_G_SEED +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_B_SEED +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_CNTL +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT2_FMT_MAP420_MEMORY_CONTROL +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT2_FMT_422_CONTROL +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg2_dispdec +//DPG2_DPG_CONTROL +#define DPG2_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG2_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG2_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG2_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG2_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG2_DPG_RAMP_CONTROL +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG2_DPG_DIMENSIONS +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_COLOUR_R_CR +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_G_Y +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_B_CB +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG2_DPG_OFFSET_SEGMENT +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_STATUS +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +//OPPBUF2_OPPBUF_CONTROL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF2_OPPBUF_CONTROL1 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +//OPP_PIPE2_OPP_PIPE_CONTROL +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt3_dispdec +//FMT3_FMT_CLAMP_COMPONENT_R +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_G +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_B +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT3_FMT_DYNAMIC_EXP_CNTL +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT3_FMT_CONTROL +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L +//FMT3_FMT_BIT_DEPTH_CONTROL +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT3_FMT_DITHER_RAND_R_SEED +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_G_SEED +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_B_SEED +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_CNTL +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT3_FMT_MAP420_MEMORY_CONTROL +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT3_FMT_422_CONTROL +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg3_dispdec +//DPG3_DPG_CONTROL +#define DPG3_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG3_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG3_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG3_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG3_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG3_DPG_RAMP_CONTROL +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG3_DPG_DIMENSIONS +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_COLOUR_R_CR +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_G_Y +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_B_CB +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG3_DPG_OFFSET_SEGMENT +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_STATUS +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +//OPPBUF3_OPPBUF_CONTROL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF3_OPPBUF_CONTROL1 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +//OPP_PIPE3_OPP_PIPE_CONTROL +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt4_dispdec +//FMT4_FMT_CLAMP_COMPONENT_R +#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT4_FMT_CLAMP_COMPONENT_G +#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT4_FMT_CLAMP_COMPONENT_B +#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT4_FMT_DYNAMIC_EXP_CNTL +#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT4_FMT_CONTROL +#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 +#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c +#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L +#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L +//FMT4_FMT_BIT_DEPTH_CONTROL +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT4_FMT_DITHER_RAND_R_SEED +#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT4_FMT_DITHER_RAND_G_SEED +#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT4_FMT_DITHER_RAND_B_SEED +#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT4_FMT_CLAMP_CNTL +#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT4_FMT_MAP420_MEMORY_CONTROL +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT4_FMT_422_CONTROL +#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg4_dispdec +//DPG4_DPG_CONTROL +#define DPG4_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG4_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG4_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG4_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG4_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG4_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG4_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG4_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG4_DPG_RAMP_CONTROL +#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG4_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG4_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG4_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG4_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG4_DPG_DIMENSIONS +#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG4_DPG_COLOUR_R_CR +#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG4_DPG_COLOUR_G_Y +#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG4_DPG_COLOUR_B_CB +#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG4_DPG_OFFSET_SEGMENT +#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG4_DPG_STATUS +#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf4_dispdec +//OPPBUF4_OPPBUF_CONTROL +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF4_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF4_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF4_OPPBUF_CONTROL1 +#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe4_dispdec +//OPP_PIPE4_OPP_PIPE_CONTROL +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec +//OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_fmt5_dispdec +//FMT5_FMT_CLAMP_COMPONENT_R +#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT5_FMT_CLAMP_COMPONENT_G +#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT5_FMT_CLAMP_COMPONENT_B +#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT5_FMT_DYNAMIC_EXP_CNTL +#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT5_FMT_CONTROL +#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT 0x4 +#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT 0x1c +#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK 0x00000010L +#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE_MASK 0x10000000L +//FMT5_FMT_BIT_DEPTH_CONTROL +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT5_FMT_DITHER_RAND_R_SEED +#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT5_FMT_DITHER_RAND_G_SEED +#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT5_FMT_DITHER_RAND_B_SEED +#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT5_FMT_CLAMP_CNTL +#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT5_FMT_MAP420_MEMORY_CONTROL +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT5_FMT_422_CONTROL +#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg5_dispdec +//DPG5_DPG_CONTROL +#define DPG5_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG5_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG5_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG5_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG5_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG5_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG5_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG5_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG5_DPG_RAMP_CONTROL +#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG5_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG5_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG5_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG5_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG5_DPG_DIMENSIONS +#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG5_DPG_COLOUR_R_CR +#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG5_DPG_COLOUR_G_Y +#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG5_DPG_COLOUR_B_CB +#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG5_DPG_OFFSET_SEGMENT +#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG5_DPG_STATUS +#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf5_dispdec +//OPPBUF5_OPPBUF_CONTROL +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF5_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF5_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF5_OPPBUF_CONTROL1 +#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe5_dispdec +//OPP_PIPE5_OPP_PIPE_CONTROL +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec +//OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT 0x10 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK 0x0000FFFFL +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFF0000L +//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT 0x10 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK 0x0000FFFFL +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFF0000L +//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_opp_opp_top_dispdec +//OPP_TOP_CLK_CONTROL +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +//DSCRM0_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +//DSCRM1_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +//DSCRM2_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm3_dispdec +//DSCRM3_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm4_dispdec +//DSCRM4_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm5_dispdec +//DSCRM5_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON16_PERFCOUNTER_CNTL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_CNTL2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_STATE +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON16_PERFMON_CNTL +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON16_PERFMON_CNTL2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON16_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON16_PERFMON_CVALUE_LOW +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON16_PERFMON_HI +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFMON_LOW +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm0_dispdec +//ODM0_OPTC_INPUT_GLOBAL_CONTROL +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM0_OPTC_DATA_SOURCE_SELECT +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L +//ODM0_OPTC_DATA_FORMAT_CONTROL +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM0_OPTC_BYTES_PER_PIXEL +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM0_OPTC_WIDTH_CONTROL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM0_OPTC_INPUT_CLOCK_CONTROL +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM0_OPTC_MEMORY_CONFIG +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +//ODM0_OPTC_INPUT_SPARE_REGISTER +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm1_dispdec +//ODM1_OPTC_INPUT_GLOBAL_CONTROL +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM1_OPTC_DATA_SOURCE_SELECT +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L +//ODM1_OPTC_DATA_FORMAT_CONTROL +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM1_OPTC_BYTES_PER_PIXEL +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM1_OPTC_WIDTH_CONTROL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM1_OPTC_INPUT_CLOCK_CONTROL +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM1_OPTC_MEMORY_CONFIG +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +//ODM1_OPTC_INPUT_SPARE_REGISTER +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm2_dispdec +//ODM2_OPTC_INPUT_GLOBAL_CONTROL +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM2_OPTC_DATA_SOURCE_SELECT +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L +//ODM2_OPTC_DATA_FORMAT_CONTROL +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM2_OPTC_BYTES_PER_PIXEL +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM2_OPTC_WIDTH_CONTROL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM2_OPTC_INPUT_CLOCK_CONTROL +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM2_OPTC_MEMORY_CONFIG +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +//ODM2_OPTC_INPUT_SPARE_REGISTER +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm3_dispdec +//ODM3_OPTC_INPUT_GLOBAL_CONTROL +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM3_OPTC_DATA_SOURCE_SELECT +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L +//ODM3_OPTC_DATA_FORMAT_CONTROL +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM3_OPTC_BYTES_PER_PIXEL +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM3_OPTC_WIDTH_CONTROL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM3_OPTC_INPUT_CLOCK_CONTROL +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM3_OPTC_MEMORY_CONFIG +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +//ODM3_OPTC_INPUT_SPARE_REGISTER +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm4_dispdec +//ODM4_OPTC_INPUT_GLOBAL_CONTROL +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM4_OPTC_DATA_SOURCE_SELECT +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L +#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L +//ODM4_OPTC_DATA_FORMAT_CONTROL +#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM4_OPTC_BYTES_PER_PIXEL +#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM4_OPTC_WIDTH_CONTROL +#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM4_OPTC_INPUT_CLOCK_CONTROL +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM4_OPTC_MEMORY_CONFIG +#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +//ODM4_OPTC_INPUT_SPARE_REGISTER +#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm5_dispdec +//ODM5_OPTC_INPUT_GLOBAL_CONTROL +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT 0x9 +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK 0x00000200L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM5_OPTC_DATA_SOURCE_SELECT +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x2 +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x8 +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0xc +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000001L +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x0000000CL +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x00000F00L +#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x0000F000L +//ODM5_OPTC_DATA_FORMAT_CONTROL +#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM5_OPTC_BYTES_PER_PIXEL +#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM5_OPTC_WIDTH_CONTROL +#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM5_OPTC_INPUT_CLOCK_CONTROL +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM5_OPTC_MEMORY_CONFIG +#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +//ODM5_OPTC_INPUT_SPARE_REGISTER +#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg0_dispdec +//OTG0_OTG_H_TOTAL +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_H_BLANK_START_END +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A_CNTL +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG0_OTG_H_TIMING_CNTL +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG0_OTG_V_TOTAL +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MIN +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MAX +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MID +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_CONTROL +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_V_TOTAL_INT_STATUS +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG0_OTG_VSYNC_NOM_INT_STATUS +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG0_OTG_V_BLANK_START_END +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A_CNTL +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG0_OTG_TRIGA_CNTL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGA_MANUAL_TRIG +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_TRIGB_CNTL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGB_MANUAL_TRIG +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_FORCE_COUNT_NOW_CNTL +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG0_OTG_FLOW_CONTROL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG0_OTG_STEREO_FORCE_NEXT_EYE +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG0_OTG_CONTROL +#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L +#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L +//OTG0_OTG_BLANK_CONTROL +#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG0_OTG_PIPE_ABORT_CONTROL +#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG0_OTG_INTERLACE_CONTROL +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG0_OTG_INTERLACE_STATUS +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG0_OTG_PIXEL_DATA_READBACK0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG0_OTG_PIXEL_DATA_READBACK1 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG0_OTG_STATUS +#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG0_OTG_STATUS_POSITION +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_NOM_VERT_POSITION +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG0_OTG_STATUS_FRAME_COUNT +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_STATUS_VF_COUNT +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_STATUS_HV_COUNT +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_COUNT_CONTROL +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG0_OTG_COUNT_RESET +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG0_OTG_VERT_SYNC_CONTROL +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG0_OTG_STEREO_STATUS +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG0_OTG_STEREO_CONTROL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG0_OTG_SNAPSHOT_STATUS +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG0_OTG_SNAPSHOT_CONTROL +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG0_OTG_SNAPSHOT_POSITION +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_SNAPSHOT_FRAME +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_INTERRUPT_CONTROL +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG0_OTG_UPDATE_LOCK +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG0_OTG_DOUBLE_BUFFER_CONTROL +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG0_OTG_MASTER_EN +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG0_OTG_BLANK_DATA_COLOR +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG0_OTG_BLANK_DATA_COLOR_EXT +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG0_OTG_BLACK_COLOR +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG0_OTG_BLACK_COLOR_EXT +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_CRC_CNTL +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG0_OTG_CRC_CNTL2 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_DATA_RG +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC0_DATA_B +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_DATA_RG +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC1_DATA_B +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_RG +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC2_DATA_B +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_RG +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG0_OTG_CRC3_DATA_B +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG0_OTG_STATIC_SCREEN_CONTROL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG0_OTG_3D_STRUCTURE_CONTROL +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG0_OTG_GSL_VSYNC_GAP +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG0_OTG_MASTER_UPDATE_MODE +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG0_OTG_CLOCK_CONTROL +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG0_OTG_VSTARTUP_PARAM +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG0_OTG_VUPDATE_PARAM +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG0_OTG_VREADY_PARAM +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG0_OTG_GLOBAL_SYNC_STATUS +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG0_OTG_MASTER_UPDATE_LOCK +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG0_OTG_GSL_CONTROL +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG0_OTG_GSL_WINDOW_X +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_GSL_WINDOW_Y +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG0_OTG_VUPDATE_KEEPOUT +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL0 +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG0_OTG_GLOBAL_CONTROL1 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL2 +#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL3 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG0_OTG_TRIG_MANUAL_CONTROL +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG0_OTG_MANUAL_FLOW_CONTROL +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG0_OTG_RANGE_TIMING_INT_STATUS +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG0_OTG_DRR_CONTROL +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG0_OTG_REQUEST_CONTROL +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG0_OTG_DSC_START_POSITION +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG0_OTG_PIPE_UPDATE_STATUS +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG0_OTG_SPARE_REGISTER +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg1_dispdec +//OTG1_OTG_H_TOTAL +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_H_BLANK_START_END +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A_CNTL +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG1_OTG_H_TIMING_CNTL +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG1_OTG_V_TOTAL +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MIN +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MAX +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MID +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_CONTROL +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_V_TOTAL_INT_STATUS +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG1_OTG_VSYNC_NOM_INT_STATUS +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG1_OTG_V_BLANK_START_END +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A_CNTL +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG1_OTG_TRIGA_CNTL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGA_MANUAL_TRIG +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_TRIGB_CNTL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGB_MANUAL_TRIG +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_FORCE_COUNT_NOW_CNTL +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG1_OTG_FLOW_CONTROL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG1_OTG_STEREO_FORCE_NEXT_EYE +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG1_OTG_CONTROL +#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L +#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L +//OTG1_OTG_BLANK_CONTROL +#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG1_OTG_PIPE_ABORT_CONTROL +#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG1_OTG_INTERLACE_CONTROL +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG1_OTG_INTERLACE_STATUS +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG1_OTG_PIXEL_DATA_READBACK0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG1_OTG_PIXEL_DATA_READBACK1 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG1_OTG_STATUS +#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG1_OTG_STATUS_POSITION +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_NOM_VERT_POSITION +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG1_OTG_STATUS_FRAME_COUNT +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_STATUS_VF_COUNT +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_STATUS_HV_COUNT +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_COUNT_CONTROL +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG1_OTG_COUNT_RESET +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG1_OTG_VERT_SYNC_CONTROL +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG1_OTG_STEREO_STATUS +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG1_OTG_STEREO_CONTROL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG1_OTG_SNAPSHOT_STATUS +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG1_OTG_SNAPSHOT_CONTROL +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG1_OTG_SNAPSHOT_POSITION +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_SNAPSHOT_FRAME +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_INTERRUPT_CONTROL +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG1_OTG_UPDATE_LOCK +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG1_OTG_DOUBLE_BUFFER_CONTROL +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG1_OTG_MASTER_EN +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG1_OTG_BLANK_DATA_COLOR +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG1_OTG_BLANK_DATA_COLOR_EXT +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG1_OTG_BLACK_COLOR +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG1_OTG_BLACK_COLOR_EXT +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_CRC_CNTL +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG1_OTG_CRC_CNTL2 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_DATA_RG +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC0_DATA_B +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_DATA_RG +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC1_DATA_B +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_RG +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC2_DATA_B +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_RG +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG1_OTG_CRC3_DATA_B +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG1_OTG_STATIC_SCREEN_CONTROL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG1_OTG_3D_STRUCTURE_CONTROL +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG1_OTG_GSL_VSYNC_GAP +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG1_OTG_MASTER_UPDATE_MODE +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG1_OTG_CLOCK_CONTROL +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG1_OTG_VSTARTUP_PARAM +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG1_OTG_VUPDATE_PARAM +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG1_OTG_VREADY_PARAM +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG1_OTG_GLOBAL_SYNC_STATUS +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG1_OTG_MASTER_UPDATE_LOCK +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG1_OTG_GSL_CONTROL +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG1_OTG_GSL_WINDOW_X +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_GSL_WINDOW_Y +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG1_OTG_VUPDATE_KEEPOUT +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL0 +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG1_OTG_GLOBAL_CONTROL1 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL2 +#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL3 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG1_OTG_TRIG_MANUAL_CONTROL +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG1_OTG_MANUAL_FLOW_CONTROL +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG1_OTG_RANGE_TIMING_INT_STATUS +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG1_OTG_DRR_CONTROL +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG1_OTG_REQUEST_CONTROL +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG1_OTG_DSC_START_POSITION +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG1_OTG_PIPE_UPDATE_STATUS +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG1_OTG_SPARE_REGISTER +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg2_dispdec +//OTG2_OTG_H_TOTAL +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_H_BLANK_START_END +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A_CNTL +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG2_OTG_H_TIMING_CNTL +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG2_OTG_V_TOTAL +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MIN +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MAX +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MID +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_CONTROL +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_V_TOTAL_INT_STATUS +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG2_OTG_VSYNC_NOM_INT_STATUS +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG2_OTG_V_BLANK_START_END +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A_CNTL +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG2_OTG_TRIGA_CNTL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGA_MANUAL_TRIG +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_TRIGB_CNTL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGB_MANUAL_TRIG +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_FORCE_COUNT_NOW_CNTL +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG2_OTG_FLOW_CONTROL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG2_OTG_STEREO_FORCE_NEXT_EYE +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG2_OTG_CONTROL +#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L +#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L +//OTG2_OTG_BLANK_CONTROL +#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG2_OTG_PIPE_ABORT_CONTROL +#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG2_OTG_INTERLACE_CONTROL +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG2_OTG_INTERLACE_STATUS +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG2_OTG_PIXEL_DATA_READBACK0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG2_OTG_PIXEL_DATA_READBACK1 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG2_OTG_STATUS +#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG2_OTG_STATUS_POSITION +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_NOM_VERT_POSITION +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG2_OTG_STATUS_FRAME_COUNT +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_STATUS_VF_COUNT +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_STATUS_HV_COUNT +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_COUNT_CONTROL +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG2_OTG_COUNT_RESET +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG2_OTG_VERT_SYNC_CONTROL +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG2_OTG_STEREO_STATUS +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG2_OTG_STEREO_CONTROL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG2_OTG_SNAPSHOT_STATUS +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG2_OTG_SNAPSHOT_CONTROL +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG2_OTG_SNAPSHOT_POSITION +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_SNAPSHOT_FRAME +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_INTERRUPT_CONTROL +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG2_OTG_UPDATE_LOCK +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG2_OTG_DOUBLE_BUFFER_CONTROL +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG2_OTG_MASTER_EN +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG2_OTG_BLANK_DATA_COLOR +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG2_OTG_BLANK_DATA_COLOR_EXT +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG2_OTG_BLACK_COLOR +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG2_OTG_BLACK_COLOR_EXT +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_CRC_CNTL +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG2_OTG_CRC_CNTL2 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_DATA_RG +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC0_DATA_B +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_DATA_RG +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC1_DATA_B +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_RG +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC2_DATA_B +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_RG +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG2_OTG_CRC3_DATA_B +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG2_OTG_STATIC_SCREEN_CONTROL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG2_OTG_3D_STRUCTURE_CONTROL +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG2_OTG_GSL_VSYNC_GAP +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG2_OTG_MASTER_UPDATE_MODE +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG2_OTG_CLOCK_CONTROL +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG2_OTG_VSTARTUP_PARAM +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG2_OTG_VUPDATE_PARAM +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG2_OTG_VREADY_PARAM +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG2_OTG_GLOBAL_SYNC_STATUS +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG2_OTG_MASTER_UPDATE_LOCK +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG2_OTG_GSL_CONTROL +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG2_OTG_GSL_WINDOW_X +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_GSL_WINDOW_Y +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG2_OTG_VUPDATE_KEEPOUT +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL0 +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG2_OTG_GLOBAL_CONTROL1 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL2 +#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL3 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG2_OTG_TRIG_MANUAL_CONTROL +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG2_OTG_MANUAL_FLOW_CONTROL +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG2_OTG_RANGE_TIMING_INT_STATUS +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG2_OTG_DRR_CONTROL +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG2_OTG_REQUEST_CONTROL +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG2_OTG_DSC_START_POSITION +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG2_OTG_PIPE_UPDATE_STATUS +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG2_OTG_SPARE_REGISTER +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg3_dispdec +//OTG3_OTG_H_TOTAL +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_H_BLANK_START_END +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A_CNTL +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG3_OTG_H_TIMING_CNTL +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG3_OTG_V_TOTAL +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MIN +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MAX +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MID +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_CONTROL +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_V_TOTAL_INT_STATUS +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG3_OTG_VSYNC_NOM_INT_STATUS +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG3_OTG_V_BLANK_START_END +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A_CNTL +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG3_OTG_TRIGA_CNTL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGA_MANUAL_TRIG +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_TRIGB_CNTL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGB_MANUAL_TRIG +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_FORCE_COUNT_NOW_CNTL +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG3_OTG_FLOW_CONTROL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG3_OTG_STEREO_FORCE_NEXT_EYE +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG3_OTG_CONTROL +#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L +#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L +//OTG3_OTG_BLANK_CONTROL +#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG3_OTG_PIPE_ABORT_CONTROL +#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG3_OTG_INTERLACE_CONTROL +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG3_OTG_INTERLACE_STATUS +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG3_OTG_PIXEL_DATA_READBACK0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG3_OTG_PIXEL_DATA_READBACK1 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG3_OTG_STATUS +#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG3_OTG_STATUS_POSITION +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_NOM_VERT_POSITION +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG3_OTG_STATUS_FRAME_COUNT +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_STATUS_VF_COUNT +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_STATUS_HV_COUNT +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_COUNT_CONTROL +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG3_OTG_COUNT_RESET +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG3_OTG_VERT_SYNC_CONTROL +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG3_OTG_STEREO_STATUS +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG3_OTG_STEREO_CONTROL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG3_OTG_SNAPSHOT_STATUS +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG3_OTG_SNAPSHOT_CONTROL +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG3_OTG_SNAPSHOT_POSITION +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_SNAPSHOT_FRAME +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_INTERRUPT_CONTROL +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG3_OTG_UPDATE_LOCK +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG3_OTG_DOUBLE_BUFFER_CONTROL +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG3_OTG_MASTER_EN +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG3_OTG_BLANK_DATA_COLOR +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG3_OTG_BLANK_DATA_COLOR_EXT +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG3_OTG_BLACK_COLOR +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG3_OTG_BLACK_COLOR_EXT +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_CRC_CNTL +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG3_OTG_CRC_CNTL2 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_DATA_RG +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC0_DATA_B +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_DATA_RG +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC1_DATA_B +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_RG +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC2_DATA_B +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_RG +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG3_OTG_CRC3_DATA_B +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG3_OTG_STATIC_SCREEN_CONTROL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG3_OTG_3D_STRUCTURE_CONTROL +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG3_OTG_GSL_VSYNC_GAP +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG3_OTG_MASTER_UPDATE_MODE +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG3_OTG_CLOCK_CONTROL +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG3_OTG_VSTARTUP_PARAM +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG3_OTG_VUPDATE_PARAM +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG3_OTG_VREADY_PARAM +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG3_OTG_GLOBAL_SYNC_STATUS +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG3_OTG_MASTER_UPDATE_LOCK +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG3_OTG_GSL_CONTROL +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG3_OTG_GSL_WINDOW_X +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_GSL_WINDOW_Y +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG3_OTG_VUPDATE_KEEPOUT +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL0 +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG3_OTG_GLOBAL_CONTROL1 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL2 +#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL3 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG3_OTG_TRIG_MANUAL_CONTROL +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG3_OTG_MANUAL_FLOW_CONTROL +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG3_OTG_RANGE_TIMING_INT_STATUS +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG3_OTG_DRR_CONTROL +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG3_OTG_REQUEST_CONTROL +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG3_OTG_DSC_START_POSITION +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG3_OTG_PIPE_UPDATE_STATUS +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG3_OTG_SPARE_REGISTER +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg4_dispdec +//OTG4_OTG_H_TOTAL +#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG4_OTG_H_BLANK_START_END +#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG4_OTG_H_SYNC_A +#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG4_OTG_H_SYNC_A_CNTL +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG4_OTG_H_TIMING_CNTL +#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG4_OTG_V_TOTAL +#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG4_OTG_V_TOTAL_MIN +#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG4_OTG_V_TOTAL_MAX +#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG4_OTG_V_TOTAL_MID +#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG4_OTG_V_TOTAL_CONTROL +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG4_OTG_V_TOTAL_INT_STATUS +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG4_OTG_VSYNC_NOM_INT_STATUS +#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG4_OTG_V_BLANK_START_END +#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG4_OTG_V_SYNC_A +#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG4_OTG_V_SYNC_A_CNTL +#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG4_OTG_TRIGA_CNTL +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG4_OTG_TRIGA_MANUAL_TRIG +#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG4_OTG_TRIGB_CNTL +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG4_OTG_TRIGB_MANUAL_TRIG +#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG4_OTG_FORCE_COUNT_NOW_CNTL +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG4_OTG_FLOW_CONTROL +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG4_OTG_STEREO_FORCE_NEXT_EYE +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG4_OTG_CONTROL +#define OTG4_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define OTG4_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L +#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L +//OTG4_OTG_BLANK_CONTROL +#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG4_OTG_PIPE_ABORT_CONTROL +#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG4_OTG_INTERLACE_CONTROL +#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG4_OTG_INTERLACE_STATUS +#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG4_OTG_PIXEL_DATA_READBACK0 +#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG4_OTG_PIXEL_DATA_READBACK1 +#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG4_OTG_STATUS +#define OTG4_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG4_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG4_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG4_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG4_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG4_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG4_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG4_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG4_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG4_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG4_OTG_STATUS_POSITION +#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG4_OTG_NOM_VERT_POSITION +#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG4_OTG_STATUS_FRAME_COUNT +#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG4_OTG_STATUS_VF_COUNT +#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG4_OTG_STATUS_HV_COUNT +#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG4_OTG_COUNT_CONTROL +#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG4_OTG_COUNT_RESET +#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG4_OTG_VERT_SYNC_CONTROL +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG4_OTG_STEREO_STATUS +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG4_OTG_STEREO_CONTROL +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG4_OTG_SNAPSHOT_STATUS +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG4_OTG_SNAPSHOT_CONTROL +#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG4_OTG_SNAPSHOT_POSITION +#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG4_OTG_SNAPSHOT_FRAME +#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG4_OTG_INTERRUPT_CONTROL +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG4_OTG_UPDATE_LOCK +#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG4_OTG_DOUBLE_BUFFER_CONTROL +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG4_OTG_MASTER_EN +#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG4_OTG_BLANK_DATA_COLOR +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG4_OTG_BLANK_DATA_COLOR_EXT +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG4_OTG_BLACK_COLOR +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG4_OTG_BLACK_COLOR_EXT +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG4_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG4_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG4_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG4_OTG_CRC_CNTL +#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG4_OTG_CRC_CNTL2 +#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG4_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC0_DATA_RG +#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG4_OTG_CRC0_DATA_B +#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG4_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG4_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG4_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG4_OTG_CRC1_DATA_RG +#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG4_OTG_CRC1_DATA_B +#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG4_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG4_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG4_OTG_CRC2_DATA_RG +#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG4_OTG_CRC2_DATA_B +#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG4_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG4_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG4_OTG_CRC3_DATA_RG +#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG4_OTG_CRC3_DATA_B +#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG4_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG4_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG4_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG4_OTG_STATIC_SCREEN_CONTROL +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG4_OTG_3D_STRUCTURE_CONTROL +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG4_OTG_GSL_VSYNC_GAP +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG4_OTG_MASTER_UPDATE_MODE +#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG4_OTG_CLOCK_CONTROL +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG4_OTG_VSTARTUP_PARAM +#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG4_OTG_VUPDATE_PARAM +#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG4_OTG_VREADY_PARAM +#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG4_OTG_GLOBAL_SYNC_STATUS +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG4_OTG_MASTER_UPDATE_LOCK +#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG4_OTG_GSL_CONTROL +#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG4_OTG_GSL_WINDOW_X +#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG4_OTG_GSL_WINDOW_Y +#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG4_OTG_VUPDATE_KEEPOUT +#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG4_OTG_GLOBAL_CONTROL0 +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG4_OTG_GLOBAL_CONTROL1 +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG4_OTG_GLOBAL_CONTROL2 +#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d +#define OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L +#define OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG4_OTG_GLOBAL_CONTROL3 +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG4_OTG_TRIG_MANUAL_CONTROL +#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG4_OTG_MANUAL_FLOW_CONTROL +#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG4_OTG_RANGE_TIMING_INT_STATUS +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG4_OTG_DRR_CONTROL +#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG4_OTG_REQUEST_CONTROL +#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG4_OTG_DSC_START_POSITION +#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG4_OTG_PIPE_UPDATE_STATUS +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L +#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG4_OTG_SPARE_REGISTER +#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg5_dispdec +//OTG5_OTG_H_TOTAL +#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG5_OTG_H_BLANK_START_END +#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG5_OTG_H_SYNC_A +#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG5_OTG_H_SYNC_A_CNTL +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG5_OTG_H_TIMING_CNTL +#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT 0x0 +#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT 0x8 +#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK 0x00000001L +#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK 0x00000100L +//OTG5_OTG_V_TOTAL +#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG5_OTG_V_TOTAL_MIN +#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG5_OTG_V_TOTAL_MAX +#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG5_OTG_V_TOTAL_MID +#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG5_OTG_V_TOTAL_CONTROL +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0x7 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK 0x00000080L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG5_OTG_V_TOTAL_INT_STATUS +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG5_OTG_VSYNC_NOM_INT_STATUS +#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG5_OTG_V_BLANK_START_END +#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG5_OTG_V_SYNC_A +#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG5_OTG_V_SYNC_A_CNTL +#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +//OTG5_OTG_TRIGA_CNTL +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG5_OTG_TRIGA_MANUAL_TRIG +#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG5_OTG_TRIGB_CNTL +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG5_OTG_TRIGB_MANUAL_TRIG +#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG5_OTG_FORCE_COUNT_NOW_CNTL +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG5_OTG_FLOW_CONTROL +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT 0x8 +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001FL +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK 0x00000100L +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L +#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L +//OTG5_OTG_STEREO_FORCE_NEXT_EYE +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT 0x8 +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT 0x10 +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK 0x0000FF00L +#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK 0x1FFF0000L +//OTG5_OTG_CONTROL +#define OTG5_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 +#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT 0x1e +#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT 0x1f +#define OTG5_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L +#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK 0x40000000L +#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK 0x80000000L +//OTG5_OTG_BLANK_CONTROL +#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT 0x0 +#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT 0x8 +#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT 0x10 +#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK 0x00000001L +#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK 0x00000100L +#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK 0x00010000L +//OTG5_OTG_PIPE_ABORT_CONTROL +#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT 0x0 +#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT 0x8 +#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK 0x00000001L +#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK 0x00000100L +//OTG5_OTG_INTERLACE_CONTROL +#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG5_OTG_INTERLACE_STATUS +#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG5_OTG_PIXEL_DATA_READBACK0 +#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG5_OTG_PIXEL_DATA_READBACK1 +#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG5_OTG_STATUS +#define OTG5_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG5_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG5_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG5_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG5_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG5_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG5_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG5_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG5_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG5_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG5_OTG_STATUS_POSITION +#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG5_OTG_NOM_VERT_POSITION +#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG5_OTG_STATUS_FRAME_COUNT +#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG5_OTG_STATUS_VF_COUNT +#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG5_OTG_STATUS_HV_COUNT +#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG5_OTG_COUNT_CONTROL +#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG5_OTG_COUNT_RESET +#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG5_OTG_VERT_SYNC_CONTROL +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG5_OTG_STEREO_STATUS +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG5_OTG_STEREO_CONTROL +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG5_OTG_SNAPSHOT_STATUS +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG5_OTG_SNAPSHOT_CONTROL +#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG5_OTG_SNAPSHOT_POSITION +#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG5_OTG_SNAPSHOT_FRAME +#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG5_OTG_INTERRUPT_CONTROL +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG5_OTG_UPDATE_LOCK +#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG5_OTG_DOUBLE_BUFFER_CONTROL +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT 0x2 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT 0x3 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT 0xa +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK 0x00000004L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK 0x00000008L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK 0x00000400L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L +#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG5_OTG_MASTER_EN +#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG5_OTG_BLANK_DATA_COLOR +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003FFL +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000FFC00L +#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK 0x3FF00000L +//OTG5_OTG_BLANK_DATA_COLOR_EXT +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x0000003FL +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x00003F00L +#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x003F0000L +//OTG5_OTG_BLACK_COLOR +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT 0x0 +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT 0xa +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT 0x14 +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK 0x000003FFL +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK 0x000FFC00L +#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK 0x3FF00000L +//OTG5_OTG_BLACK_COLOR_EXT +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK 0x0000003FL +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK 0x00003F00L +#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK 0x003F0000L +//OTG5_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +//OTG5_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG5_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG5_OTG_CRC_CNTL +#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT 0x1 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT 0x2 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK 0x00000002L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK 0x00000004L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG5_OTG_CRC_CNTL2 +#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT 0x0 +#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT 0x1 +#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT 0x4 +#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT 0x8 +#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK 0x00000001L +#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK 0x00000002L +#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK 0x00000030L +#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK 0x00000300L +//OTG5_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC0_DATA_RG +#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 +#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 +#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK 0x0000FFFFL +#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK 0xFFFF0000L +//OTG5_OTG_CRC0_DATA_B +#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG5_OTG_CRC0_DATA_B__CRC0_C__SHIFT 0x10 +#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0x0000FFFFL +#define OTG5_OTG_CRC0_DATA_B__CRC0_C_MASK 0xFFFF0000L +//OTG5_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG5_OTG_CRC1_DATA_RG +#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 +#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 +#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK 0x0000FFFFL +#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK 0xFFFF0000L +//OTG5_OTG_CRC1_DATA_B +#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG5_OTG_CRC1_DATA_B__CRC1_C__SHIFT 0x10 +#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0x0000FFFFL +#define OTG5_OTG_CRC1_DATA_B__CRC1_C_MASK 0xFFFF0000L +//OTG5_OTG_CRC2_DATA_RG +#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT 0x0 +#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT 0x10 +#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK 0x0000FFFFL +#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK 0xFFFF0000L +//OTG5_OTG_CRC2_DATA_B +#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG5_OTG_CRC2_DATA_B__CRC2_C__SHIFT 0x10 +#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0x0000FFFFL +#define OTG5_OTG_CRC2_DATA_B__CRC2_C_MASK 0xFFFF0000L +//OTG5_OTG_CRC3_DATA_RG +#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT 0x0 +#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT 0x10 +#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK 0x0000FFFFL +#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK 0xFFFF0000L +//OTG5_OTG_CRC3_DATA_B +#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG5_OTG_CRC3_DATA_B__CRC3_C__SHIFT 0x10 +#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0x0000FFFFL +#define OTG5_OTG_CRC3_DATA_B__CRC3_C_MASK 0xFFFF0000L +//OTG5_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG5_OTG_STATIC_SCREEN_CONTROL +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG5_OTG_3D_STRUCTURE_CONTROL +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG5_OTG_GSL_VSYNC_GAP +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG5_OTG_MASTER_UPDATE_MODE +#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG5_OTG_CLOCK_CONTROL +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG5_OTG_VSTARTUP_PARAM +#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG5_OTG_VUPDATE_PARAM +#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG5_OTG_VREADY_PARAM +#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG5_OTG_GLOBAL_SYNC_STATUS +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG5_OTG_MASTER_UPDATE_LOCK +#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG5_OTG_GSL_CONTROL +#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG5_OTG_GSL_WINDOW_X +#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG5_OTG_GSL_WINDOW_Y +#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG5_OTG_VUPDATE_KEEPOUT +#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG5_OTG_GLOBAL_CONTROL0 +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT 0x8 +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK 0x000000FFL +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK 0x00000100L +#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +//OTG5_OTG_GLOBAL_CONTROL1 +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT 0x10 +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK 0x00007FFFL +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK 0x7FFF0000L +#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG5_OTG_GLOBAL_CONTROL2 +#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT 0x1d +#define OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK 0x000003FFL +#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK 0x20000000L +#define OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG5_OTG_GLOBAL_CONTROL3 +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT 0x8 +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK 0x00000100L +//OTG5_OTG_TRIG_MANUAL_CONTROL +#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG5_OTG_MANUAL_FLOW_CONTROL +#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT 0x0 +#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK 0x00000001L +//OTG5_OTG_RANGE_TIMING_INT_STATUS +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0x10 +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00010000L +//OTG5_OTG_DRR_CONTROL +#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000007L +#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG5_OTG_REQUEST_CONTROL +#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG5_OTG_DSC_START_POSITION +#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT 0x0 +#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT 0x10 +#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK 0x00007FFFL +#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK 0x03FF0000L +//OTG5_OTG_PIPE_UPDATE_STATUS +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT 0x1 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT 0x2 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT 0x5 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT 0x6 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT 0x9 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT 0xa +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK 0x00000002L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK 0x00000004L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK 0x00000020L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK 0x00000040L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK 0x00000200L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK 0x00000400L +#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG5_OTG_SPARE_REGISTER +#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +//DWB_SOURCE_SELECT +#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT 0x0 +#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT 0x3 +#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT 0x6 +#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK 0x00000007L +#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK 0x00000038L +#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK 0x000001C0L +//GSL_SOURCE_SELECT +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L +//OPTC_CLOCK_CONTROL +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L +//ODM_MEM_PWR_CTRL +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT 0x10 +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT 0x12 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT 0x14 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT 0x16 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT 0x18 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT 0x1a +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT 0x1c +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT 0x1e +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK 0x00030000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK 0x00040000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK 0x00300000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK 0x00400000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK 0x03000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK 0x04000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK 0x30000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK 0x40000000L +//ODM_MEM_PWR_CTRL2 +#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE__SHIFT 0x4 +#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS__SHIFT 0x6 +#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE__SHIFT 0x8 +#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS__SHIFT 0xa +#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE__SHIFT 0xc +#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS__SHIFT 0xe +#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS_MASK 0x00000004L +#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE_MASK 0x00000030L +#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS_MASK 0x00000040L +#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE_MASK 0x00000300L +#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS_MASK 0x00000400L +#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE_MASK 0x00003000L +#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS_MASK 0x00004000L +//ODM_MEM_PWR_CTRL3 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL +//ODM_MEM_PWR_STATUS +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0 +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2 +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4 +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6 +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT 0x8 +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT 0xa +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT 0xc +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT 0xe +#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE__SHIFT 0x10 +#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE__SHIFT 0x12 +#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE__SHIFT 0x14 +#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE__SHIFT 0x16 +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK 0x00000300L +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK 0x00000C00L +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK 0x00003000L +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK 0x0000C000L +#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE_MASK 0x00030000L +#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE_MASK 0x000C0000L +#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE_MASK 0x00300000L +#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE_MASK 0x00C00000L +//OPTC_MISC_SPARE_REGISTER +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON17_PERFCOUNTER_CNTL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_CNTL2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_STATE +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON17_PERFMON_CNTL +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON17_PERFMON_CNTL2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON17_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON17_PERFMON_CVALUE_LOW +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON17_PERFMON_HI +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFMON_LOW +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +//DC_I2C_CONTROL +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +//DC_I2C_ARBITRATION +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +//DC_I2C_INTERRUPT_CONTROL +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +//DC_I2C_SW_STATUS +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +//DC_I2C_DDC1_HW_STATUS +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC2_HW_STATUS +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC3_HW_STATUS +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC4_HW_STATUS +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC5_HW_STATUS +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC1_SPEED +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC1_SETUP +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC2_SPEED +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC2_SETUP +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC3_SPEED +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC3_SETUP +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC4_SPEED +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC4_SETUP +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC5_SPEED +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC5_SETUP +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_TRANSACTION0 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L +//DC_I2C_TRANSACTION1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L +//DC_I2C_TRANSACTION2 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L +//DC_I2C_TRANSACTION3 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L +//DC_I2C_DATA +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +//DC_I2C_EDID_DETECT_CTRL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +//DC_I2C_READ_REQUEST_INTERRUPT +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L + + +//DIG_SOFT_RESET +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 +#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L +#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L +#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L +#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L +#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L +#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L +#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L +#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L +#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L +#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L +#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L +#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L +#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x01000000L +#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x02000000L +//DIO_MEM_PWR_STATUS1 +#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE__SHIFT 0x2 +#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE__SHIFT 0xa +#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE__SHIFT 0x10 +#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE__SHIFT 0x12 +#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE__SHIFT 0x14 +#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE__SHIFT 0x16 +#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE__SHIFT 0x18 +#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE__SHIFT 0x1a +#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE_MASK 0x00000004L +#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE_MASK 0x00000400L +#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE_MASK 0x00030000L +#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE_MASK 0x000C0000L +#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE_MASK 0x00300000L +#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE_MASK 0x00C00000L +#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE_MASK 0x03000000L +#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE_MASK 0x0C000000L +//DIO_CLK_CNTL2 +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT 0x0 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT 0x7 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT 0x8 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT 0x9 +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT 0x11 +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT 0x12 +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT 0x13 +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT 0x14 +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT 0x15 +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT 0x16 +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT 0x17 +#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK 0x0000007FL +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK 0x00000080L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK 0x00000100L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK 0x00000200L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK 0x00020000L +#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK 0x00040000L +#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK 0x00080000L +#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK 0x00100000L +#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK 0x00200000L +#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK 0x00400000L +#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK 0x00800000L +//DIO_CLK_CNTL3 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT 0x0 +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT 0x1 +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT 0x2 +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT 0x3 +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT 0x4 +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT 0x5 +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT 0x6 +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT 0xe +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT 0xf +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT 0x10 +#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK 0x00000001L +#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK 0x00000002L +#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK 0x00000004L +#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK 0x00000008L +#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK 0x00000010L +#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK 0x00000020L +#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK 0x00000040L +#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK 0x00004000L +#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK 0x00008000L +#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK 0x00010000L +//DIO_HDMI_RXSTATUS_TIMER_CONTROL +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L +//DIO_PSP_INTERRUPT_STATUS +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL +//DIO_PSP_INTERRUPT_CLEAR +#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT 0x0 +#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L +//DIO_GENERIC_INTERRUPT_MESSAGE +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL +//DIO_GENERIC_INTERRUPT_CLEAR +#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT 0x0 +#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_hpd0_dispdec +//HPD0_DC_HPD_INT_STATUS +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD0_DC_HPD_INT_CONTROL +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD0_DC_HPD_CONTROL +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD0_DC_HPD_FAST_TRAIN_CNTL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD0_DC_HPD_TOGGLE_FILT_CNTL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd1_dispdec +//HPD1_DC_HPD_INT_STATUS +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD1_DC_HPD_INT_CONTROL +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD1_DC_HPD_CONTROL +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD1_DC_HPD_FAST_TRAIN_CNTL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD1_DC_HPD_TOGGLE_FILT_CNTL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd2_dispdec +//HPD2_DC_HPD_INT_STATUS +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD2_DC_HPD_INT_CONTROL +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD2_DC_HPD_CONTROL +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD2_DC_HPD_FAST_TRAIN_CNTL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD2_DC_HPD_TOGGLE_FILT_CNTL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd3_dispdec +//HPD3_DC_HPD_INT_STATUS +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD3_DC_HPD_INT_CONTROL +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD3_DC_HPD_CONTROL +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD3_DC_HPD_FAST_TRAIN_CNTL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD3_DC_HPD_TOGGLE_FILT_CNTL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_hpd4_dispdec +//HPD4_DC_HPD_INT_STATUS +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD4_DC_HPD_INT_CONTROL +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD4_DC_HPD_CONTROL +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD4_DC_HPD_FAST_TRAIN_CNTL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD4_DC_HPD_TOGGLE_FILT_CNTL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON18_PERFCOUNTER_CNTL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_CNTL2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_STATE +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON18_PERFMON_CNTL +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON18_PERFMON_CNTL2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON18_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON18_PERFMON_CVALUE_LOW +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON18_PERFMON_HI +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFMON_LOW +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dp_aux0_dispdec +//DP_AUX0_AUX_CONTROL +#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX0_AUX_SW_CONTROL +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX0_AUX_ARB_CONTROL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX0_AUX_INTERRUPT_CONTROL +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX0_AUX_SW_STATUS +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX0_AUX_LS_STATUS +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX0_AUX_SW_DATA +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX0_AUX_LS_DATA +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX0_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_TX_CONTROL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX0_AUX_DPHY_RX_CONTROL0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX0_AUX_DPHY_RX_CONTROL1 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX0_AUX_DPHY_TX_STATUS +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_RX_STATUS +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX0_AUX_GTC_SYNC_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX0_AUX_GTC_SYNC_STATUS +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX0_AUX_PHY_WAKE_CNTL +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux1_dispdec +//DP_AUX1_AUX_CONTROL +#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX1_AUX_SW_CONTROL +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX1_AUX_ARB_CONTROL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX1_AUX_INTERRUPT_CONTROL +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX1_AUX_SW_STATUS +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX1_AUX_LS_STATUS +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX1_AUX_SW_DATA +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX1_AUX_LS_DATA +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX1_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_TX_CONTROL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX1_AUX_DPHY_RX_CONTROL0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX1_AUX_DPHY_RX_CONTROL1 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX1_AUX_DPHY_TX_STATUS +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_RX_STATUS +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX1_AUX_GTC_SYNC_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX1_AUX_GTC_SYNC_STATUS +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX1_AUX_PHY_WAKE_CNTL +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux2_dispdec +//DP_AUX2_AUX_CONTROL +#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX2_AUX_SW_CONTROL +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX2_AUX_ARB_CONTROL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX2_AUX_INTERRUPT_CONTROL +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX2_AUX_SW_STATUS +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX2_AUX_LS_STATUS +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX2_AUX_SW_DATA +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX2_AUX_LS_DATA +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX2_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_TX_CONTROL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX2_AUX_DPHY_RX_CONTROL0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX2_AUX_DPHY_RX_CONTROL1 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX2_AUX_DPHY_TX_STATUS +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_RX_STATUS +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX2_AUX_GTC_SYNC_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX2_AUX_GTC_SYNC_STATUS +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX2_AUX_PHY_WAKE_CNTL +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux3_dispdec +//DP_AUX3_AUX_CONTROL +#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX3_AUX_SW_CONTROL +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX3_AUX_ARB_CONTROL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX3_AUX_INTERRUPT_CONTROL +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX3_AUX_SW_STATUS +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX3_AUX_LS_STATUS +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX3_AUX_SW_DATA +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX3_AUX_LS_DATA +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX3_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_TX_CONTROL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX3_AUX_DPHY_RX_CONTROL0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX3_AUX_DPHY_RX_CONTROL1 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX3_AUX_DPHY_TX_STATUS +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_RX_STATUS +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX3_AUX_GTC_SYNC_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX3_AUX_GTC_SYNC_STATUS +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX3_AUX_PHY_WAKE_CNTL +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dp_aux4_dispdec +//DP_AUX4_AUX_CONTROL +#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d +#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT 0x1e +#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT 0x1f +#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L +#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK 0x40000000L +#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK 0x80000000L +//DP_AUX4_AUX_SW_CONTROL +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX4_AUX_ARB_CONTROL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX4_AUX_INTERRUPT_CONTROL +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x00000100L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x00000200L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x00000400L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x00001000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x00002000L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x00004000L +//DP_AUX4_AUX_SW_STATUS +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xE0000000L +//DP_AUX4_AUX_LS_STATUS +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX4_AUX_SW_DATA +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX4_AUX_LS_DATA +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX4_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_TX_CONTROL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX4_AUX_DPHY_RX_CONTROL0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX4_AUX_DPHY_RX_CONTROL1 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX4_AUX_DPHY_TX_STATUS +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_RX_STATUS +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX4_AUX_GTC_SYNC_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0x00000F00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0x0000F000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x00070000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0x00C00000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x03000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x0000001FL +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x00001F00L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x00030000L +#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x00300000L +//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x00000010L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x00001E00L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x00010000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x00200000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x01000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x02000000L +#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xF0000000L +//DP_AUX4_AUX_GTC_SYNC_STATUS +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000L +#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000L +//DP_AUX4_AUX_PHY_WAKE_CNTL +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L + + +// addressBlock: dce_dc_dio_dig0_dispdec +//DIG0_DIG_FE_CNTL +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG0_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG0_DIG_OUTPUT_CRC_CNTL +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG0_DIG_OUTPUT_CRC_RESULT +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG0_DIG_CLOCK_PATTERN +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG0_DIG_TEST_PATTERN +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG0_DIG_RANDOM_PATTERN_SEED +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG0_DIG_FIFO_STATUS +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG0_HDMI_METADATA_PACKET_CONTROL +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_CONTROL +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG0_HDMI_STATUS +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG0_HDMI_AUDIO_PACKET_CONTROL +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG0_HDMI_ACR_PACKET_CONTROL +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG0_HDMI_VBI_PACKET_CONTROL +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG0_HDMI_INFOFRAME_CONTROL0 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG0_HDMI_INFOFRAME_CONTROL1 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +//DIG0_HDMI_GC +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG0_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG0_AFMT_ISRC1_0 +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG0_AFMT_ISRC1_1 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG0_AFMT_ISRC1_2 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG0_AFMT_ISRC1_3 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG0_AFMT_ISRC1_4 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG0_AFMT_ISRC2_0 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG0_AFMT_ISRC2_1 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG0_AFMT_ISRC2_2 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG0_AFMT_ISRC2_3 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_DB_CONTROL +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG0_DME_CONTROL +#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DIG0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DIG0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DIG0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DIG0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DIG0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DIG0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DIG0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DIG0_AFMT_MPEG_INFO0 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG0_AFMT_MPEG_INFO1 +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG0_AFMT_GENERIC_HDR +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_0 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_1 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_2 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_3 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_4 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_5 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_6 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG0_AFMT_GENERIC_7 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_ACR_32_0 +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_32_1 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_44_0 +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_44_1 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_48_0 +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_48_1 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_STATUS_0 +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_STATUS_1 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG0_AFMT_AUDIO_INFO0 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG0_AFMT_AUDIO_INFO1 +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG0_AFMT_60958_0 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG0_AFMT_60958_1 +#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG0_AFMT_AUDIO_CRC_CONTROL +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG0_AFMT_RAMP_CONTROL0 +#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG0_AFMT_RAMP_CONTROL1 +#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG0_AFMT_RAMP_CONTROL2 +#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG0_AFMT_RAMP_CONTROL3 +#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG0_AFMT_60958_2 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG0_AFMT_AUDIO_CRC_RESULT +#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG0_AFMT_STATUS +#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG0_AFMT_AUDIO_PACKET_CONTROL +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//DIG0_AFMT_VBI_PACKET_CONTROL +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG0_AFMT_INFOFRAME_CONTROL0 +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG0_AFMT_AUDIO_SRC_CONTROL +#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG0_DIG_BE_CNTL +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG0_DIG_BE_EN_CNTL +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG0_TMDS_CNTL +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG0_TMDS_CONTROL_CHAR +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG0_TMDS_CONTROL0_FEEDBACK +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG0_TMDS_STEREOSYNC_CTL_SEL +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG0_TMDS_CTL_BITS +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG0_TMDS_DCBALANCER_CONTROL +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG0_TMDS_SYNC_DCBALANCE_CHAR +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG0_TMDS_CTL0_1_GEN_CNTL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG0_TMDS_CTL2_3_GEN_CNTL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG0_DIG_VERSION +#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG0_DIG_LANE_ENABLE +#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG0_AFMT_CNTL +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG0_AFMT_VBI_PACKET_CONTROL1 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +//DIG0_FORCE_DIG_DISABLE +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp0_dispdec +//DP0_DP_LINK_CNTL +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP0_DP_PIXEL_FORMAT +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP0_DP_MSA_COLORIMETRY +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP0_DP_CONFIG +#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP0_DP_VID_STREAM_CNTL +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP0_DP_STEER_FIFO +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP0_DP_MSA_MISC +#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP0_DP_VID_TIMING +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP0_DP_VID_N +#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP0_DP_VID_M +#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP0_DP_LINK_FRAMING_CNTL +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP0_DP_HBR2_EYE_PATTERN +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP0_DP_VID_MSA_VBID +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP0_DP_VID_INTERRUPT_CNTL +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP0_DP_DPHY_CNTL +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP0_DP_DPHY_TRAINING_PATTERN_SEL +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP0_DP_DPHY_SYM0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM1 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM2 +#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP0_DP_DPHY_8B10B_CNTL +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP0_DP_DPHY_PRBS_CNTL +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP0_DP_DPHY_SCRAM_CNTL +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP0_DP_DPHY_CRC_EN +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP0_DP_DPHY_CRC_CNTL +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP0_DP_DPHY_CRC_RESULT +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP0_DP_DPHY_CRC_MST_CNTL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP0_DP_DPHY_CRC_MST_STATUS +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP0_DP_DPHY_FAST_TRAINING +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP0_DP_DPHY_FAST_TRAINING_STATUS +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP0_DP_SEC_CNTL +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP0_DP_SEC_CNTL1 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING1 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING2 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING3 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING4 +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP0_DP_SEC_AUD_N +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_N_READBACK +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M_READBACK +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_TIMESTAMP +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP0_DP_SEC_PACKET_CNTL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP0_DP_MSE_RATE_CNTL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP0_DP_MSE_RATE_UPDATE +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP0_DP_MSE_SAT0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP0_DP_MSE_SAT1 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP0_DP_MSE_SAT2 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP0_DP_MSE_SAT_UPDATE +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP0_DP_MSE_LINK_TIMING +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP0_DP_MSE_MISC_CNTL +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP0_DP_DPHY_BS_SR_SWAP_CNTL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP0_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP0_DP_MSE_SAT0_STATUS +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT1_STATUS +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT2_STATUS +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP0_DP_MSA_TIMING_PARAM1 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM2 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM3 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP0_DP_MSA_TIMING_PARAM4 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP0_DP_MSO_CNTL +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP0_DP_MSO_CNTL1 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP0_DP_DSC_CNTL +#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP0_DP_SEC_CNTL2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP0_DP_SEC_CNTL3 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL4 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL5 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL6 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP0_DP_SEC_CNTL7 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP0_DP_DB_CNTL +#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP0_DP_MSA_VBID_MISC +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_METADATA_TRANSMISSION +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP0_DP_DSC_BYTES_PER_PIXEL +#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP0_DP_ALPM_CNTL +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig1_dispdec +//DIG1_DIG_FE_CNTL +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG1_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG1_DIG_OUTPUT_CRC_CNTL +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG1_DIG_OUTPUT_CRC_RESULT +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG1_DIG_CLOCK_PATTERN +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG1_DIG_TEST_PATTERN +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG1_DIG_RANDOM_PATTERN_SEED +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG1_DIG_FIFO_STATUS +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG1_HDMI_METADATA_PACKET_CONTROL +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_CONTROL +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG1_HDMI_STATUS +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG1_HDMI_AUDIO_PACKET_CONTROL +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG1_HDMI_ACR_PACKET_CONTROL +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG1_HDMI_VBI_PACKET_CONTROL +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG1_HDMI_INFOFRAME_CONTROL0 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG1_HDMI_INFOFRAME_CONTROL1 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +//DIG1_HDMI_GC +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG1_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG1_AFMT_ISRC1_0 +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG1_AFMT_ISRC1_1 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG1_AFMT_ISRC1_2 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG1_AFMT_ISRC1_3 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG1_AFMT_ISRC1_4 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG1_AFMT_ISRC2_0 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG1_AFMT_ISRC2_1 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG1_AFMT_ISRC2_2 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG1_AFMT_ISRC2_3 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_DB_CONTROL +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG1_DME_CONTROL +#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DIG1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DIG1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DIG1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DIG1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DIG1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DIG1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DIG1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DIG1_AFMT_MPEG_INFO0 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG1_AFMT_MPEG_INFO1 +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG1_AFMT_GENERIC_HDR +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_0 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_1 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_2 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_3 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_4 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_5 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_6 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG1_AFMT_GENERIC_7 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_ACR_32_0 +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_32_1 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_44_0 +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_44_1 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_48_0 +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_48_1 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_STATUS_0 +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_STATUS_1 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG1_AFMT_AUDIO_INFO0 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG1_AFMT_AUDIO_INFO1 +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG1_AFMT_60958_0 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG1_AFMT_60958_1 +#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG1_AFMT_AUDIO_CRC_CONTROL +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG1_AFMT_RAMP_CONTROL0 +#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG1_AFMT_RAMP_CONTROL1 +#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG1_AFMT_RAMP_CONTROL2 +#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG1_AFMT_RAMP_CONTROL3 +#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG1_AFMT_60958_2 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG1_AFMT_AUDIO_CRC_RESULT +#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG1_AFMT_STATUS +#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG1_AFMT_AUDIO_PACKET_CONTROL +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//DIG1_AFMT_VBI_PACKET_CONTROL +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG1_AFMT_INFOFRAME_CONTROL0 +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG1_AFMT_AUDIO_SRC_CONTROL +#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG1_DIG_BE_CNTL +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG1_DIG_BE_EN_CNTL +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG1_TMDS_CNTL +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG1_TMDS_CONTROL_CHAR +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG1_TMDS_CONTROL0_FEEDBACK +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG1_TMDS_STEREOSYNC_CTL_SEL +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG1_TMDS_CTL_BITS +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG1_TMDS_DCBALANCER_CONTROL +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG1_TMDS_SYNC_DCBALANCE_CHAR +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG1_TMDS_CTL0_1_GEN_CNTL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG1_TMDS_CTL2_3_GEN_CNTL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG1_DIG_VERSION +#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG1_DIG_LANE_ENABLE +#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG1_AFMT_CNTL +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG1_AFMT_VBI_PACKET_CONTROL1 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +//DIG1_FORCE_DIG_DISABLE +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp1_dispdec +//DP1_DP_LINK_CNTL +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP1_DP_PIXEL_FORMAT +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP1_DP_MSA_COLORIMETRY +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP1_DP_CONFIG +#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP1_DP_VID_STREAM_CNTL +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP1_DP_STEER_FIFO +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP1_DP_MSA_MISC +#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP1_DP_VID_TIMING +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP1_DP_VID_N +#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP1_DP_VID_M +#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP1_DP_LINK_FRAMING_CNTL +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP1_DP_HBR2_EYE_PATTERN +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP1_DP_VID_MSA_VBID +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP1_DP_VID_INTERRUPT_CNTL +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP1_DP_DPHY_CNTL +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP1_DP_DPHY_TRAINING_PATTERN_SEL +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP1_DP_DPHY_SYM0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM1 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM2 +#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP1_DP_DPHY_8B10B_CNTL +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP1_DP_DPHY_PRBS_CNTL +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP1_DP_DPHY_SCRAM_CNTL +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP1_DP_DPHY_CRC_EN +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP1_DP_DPHY_CRC_CNTL +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP1_DP_DPHY_CRC_RESULT +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP1_DP_DPHY_CRC_MST_CNTL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP1_DP_DPHY_CRC_MST_STATUS +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP1_DP_DPHY_FAST_TRAINING +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP1_DP_DPHY_FAST_TRAINING_STATUS +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP1_DP_SEC_CNTL +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP1_DP_SEC_CNTL1 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING1 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING2 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING3 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING4 +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP1_DP_SEC_AUD_N +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_N_READBACK +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M_READBACK +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_TIMESTAMP +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP1_DP_SEC_PACKET_CNTL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP1_DP_MSE_RATE_CNTL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP1_DP_MSE_RATE_UPDATE +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP1_DP_MSE_SAT0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP1_DP_MSE_SAT1 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP1_DP_MSE_SAT2 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP1_DP_MSE_SAT_UPDATE +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP1_DP_MSE_LINK_TIMING +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP1_DP_MSE_MISC_CNTL +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP1_DP_DPHY_BS_SR_SWAP_CNTL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP1_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP1_DP_MSE_SAT0_STATUS +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT1_STATUS +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT2_STATUS +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP1_DP_MSA_TIMING_PARAM1 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM2 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM3 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP1_DP_MSA_TIMING_PARAM4 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP1_DP_MSO_CNTL +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP1_DP_MSO_CNTL1 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP1_DP_DSC_CNTL +#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP1_DP_SEC_CNTL2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP1_DP_SEC_CNTL3 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL4 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL5 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL6 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP1_DP_SEC_CNTL7 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP1_DP_DB_CNTL +#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP1_DP_MSA_VBID_MISC +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_METADATA_TRANSMISSION +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP1_DP_DSC_BYTES_PER_PIXEL +#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP1_DP_ALPM_CNTL +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig2_dispdec +//DIG2_DIG_FE_CNTL +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG2_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG2_DIG_OUTPUT_CRC_CNTL +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG2_DIG_OUTPUT_CRC_RESULT +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG2_DIG_CLOCK_PATTERN +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG2_DIG_TEST_PATTERN +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG2_DIG_RANDOM_PATTERN_SEED +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG2_DIG_FIFO_STATUS +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG2_HDMI_METADATA_PACKET_CONTROL +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_CONTROL +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG2_HDMI_STATUS +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG2_HDMI_AUDIO_PACKET_CONTROL +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG2_HDMI_ACR_PACKET_CONTROL +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG2_HDMI_VBI_PACKET_CONTROL +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG2_HDMI_INFOFRAME_CONTROL0 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG2_HDMI_INFOFRAME_CONTROL1 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +//DIG2_HDMI_GC +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG2_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG2_AFMT_ISRC1_0 +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG2_AFMT_ISRC1_1 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG2_AFMT_ISRC1_2 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG2_AFMT_ISRC1_3 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG2_AFMT_ISRC1_4 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG2_AFMT_ISRC2_0 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG2_AFMT_ISRC2_1 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG2_AFMT_ISRC2_2 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG2_AFMT_ISRC2_3 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_DB_CONTROL +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG2_DME_CONTROL +#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DIG2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DIG2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DIG2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DIG2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DIG2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DIG2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DIG2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DIG2_AFMT_MPEG_INFO0 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG2_AFMT_MPEG_INFO1 +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG2_AFMT_GENERIC_HDR +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_0 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_1 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_2 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_3 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_4 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_5 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_6 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG2_AFMT_GENERIC_7 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_ACR_32_0 +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_32_1 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_44_0 +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_44_1 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_48_0 +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_48_1 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_STATUS_0 +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_STATUS_1 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG2_AFMT_AUDIO_INFO0 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG2_AFMT_AUDIO_INFO1 +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG2_AFMT_60958_0 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG2_AFMT_60958_1 +#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG2_AFMT_AUDIO_CRC_CONTROL +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG2_AFMT_RAMP_CONTROL0 +#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG2_AFMT_RAMP_CONTROL1 +#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG2_AFMT_RAMP_CONTROL2 +#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG2_AFMT_RAMP_CONTROL3 +#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG2_AFMT_60958_2 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG2_AFMT_AUDIO_CRC_RESULT +#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG2_AFMT_STATUS +#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG2_AFMT_AUDIO_PACKET_CONTROL +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//DIG2_AFMT_VBI_PACKET_CONTROL +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG2_AFMT_INFOFRAME_CONTROL0 +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG2_AFMT_AUDIO_SRC_CONTROL +#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG2_DIG_BE_CNTL +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG2_DIG_BE_EN_CNTL +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG2_TMDS_CNTL +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG2_TMDS_CONTROL_CHAR +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG2_TMDS_CONTROL0_FEEDBACK +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG2_TMDS_STEREOSYNC_CTL_SEL +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG2_TMDS_CTL_BITS +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG2_TMDS_DCBALANCER_CONTROL +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG2_TMDS_SYNC_DCBALANCE_CHAR +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG2_TMDS_CTL0_1_GEN_CNTL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG2_TMDS_CTL2_3_GEN_CNTL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG2_DIG_VERSION +#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG2_DIG_LANE_ENABLE +#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG2_AFMT_CNTL +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG2_AFMT_VBI_PACKET_CONTROL1 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +//DIG2_FORCE_DIG_DISABLE +#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp2_dispdec +//DP2_DP_LINK_CNTL +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP2_DP_PIXEL_FORMAT +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP2_DP_MSA_COLORIMETRY +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP2_DP_CONFIG +#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP2_DP_VID_STREAM_CNTL +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP2_DP_STEER_FIFO +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP2_DP_MSA_MISC +#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP2_DP_VID_TIMING +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP2_DP_VID_N +#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP2_DP_VID_M +#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP2_DP_LINK_FRAMING_CNTL +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP2_DP_HBR2_EYE_PATTERN +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP2_DP_VID_MSA_VBID +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP2_DP_VID_INTERRUPT_CNTL +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP2_DP_DPHY_CNTL +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP2_DP_DPHY_TRAINING_PATTERN_SEL +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP2_DP_DPHY_SYM0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM1 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM2 +#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP2_DP_DPHY_8B10B_CNTL +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP2_DP_DPHY_PRBS_CNTL +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP2_DP_DPHY_SCRAM_CNTL +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP2_DP_DPHY_CRC_EN +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP2_DP_DPHY_CRC_CNTL +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP2_DP_DPHY_CRC_RESULT +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP2_DP_DPHY_CRC_MST_CNTL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP2_DP_DPHY_CRC_MST_STATUS +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP2_DP_DPHY_FAST_TRAINING +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP2_DP_DPHY_FAST_TRAINING_STATUS +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP2_DP_SEC_CNTL +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP2_DP_SEC_CNTL1 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING1 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING2 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING3 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING4 +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP2_DP_SEC_AUD_N +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_N_READBACK +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M_READBACK +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_TIMESTAMP +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP2_DP_SEC_PACKET_CNTL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP2_DP_MSE_RATE_CNTL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP2_DP_MSE_RATE_UPDATE +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP2_DP_MSE_SAT0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP2_DP_MSE_SAT1 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP2_DP_MSE_SAT2 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP2_DP_MSE_SAT_UPDATE +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP2_DP_MSE_LINK_TIMING +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP2_DP_MSE_MISC_CNTL +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP2_DP_DPHY_BS_SR_SWAP_CNTL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP2_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP2_DP_MSE_SAT0_STATUS +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT1_STATUS +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT2_STATUS +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP2_DP_MSA_TIMING_PARAM1 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM2 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM3 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP2_DP_MSA_TIMING_PARAM4 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP2_DP_MSO_CNTL +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP2_DP_MSO_CNTL1 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP2_DP_DSC_CNTL +#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP2_DP_SEC_CNTL2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP2_DP_SEC_CNTL3 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL4 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL5 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL6 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP2_DP_SEC_CNTL7 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP2_DP_DB_CNTL +#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP2_DP_MSA_VBID_MISC +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_METADATA_TRANSMISSION +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP2_DP_DSC_BYTES_PER_PIXEL +#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP2_DP_ALPM_CNTL +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig3_dispdec +//DIG3_DIG_FE_CNTL +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG3_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG3_DIG_OUTPUT_CRC_CNTL +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG3_DIG_OUTPUT_CRC_RESULT +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG3_DIG_CLOCK_PATTERN +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG3_DIG_TEST_PATTERN +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG3_DIG_RANDOM_PATTERN_SEED +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG3_DIG_FIFO_STATUS +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG3_HDMI_METADATA_PACKET_CONTROL +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_CONTROL +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG3_HDMI_STATUS +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG3_HDMI_AUDIO_PACKET_CONTROL +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG3_HDMI_ACR_PACKET_CONTROL +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG3_HDMI_VBI_PACKET_CONTROL +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG3_HDMI_INFOFRAME_CONTROL0 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG3_HDMI_INFOFRAME_CONTROL1 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +//DIG3_HDMI_GC +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG3_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG3_AFMT_ISRC1_0 +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG3_AFMT_ISRC1_1 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG3_AFMT_ISRC1_2 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG3_AFMT_ISRC1_3 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG3_AFMT_ISRC1_4 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG3_AFMT_ISRC2_0 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG3_AFMT_ISRC2_1 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG3_AFMT_ISRC2_2 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG3_AFMT_ISRC2_3 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_DB_CONTROL +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG3_DME_CONTROL +#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DIG3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DIG3_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DIG3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DIG3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DIG3_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DIG3_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DIG3_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DIG3_AFMT_MPEG_INFO0 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG3_AFMT_MPEG_INFO1 +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG3_AFMT_GENERIC_HDR +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_0 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_1 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_2 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_3 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_4 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_5 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_6 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG3_AFMT_GENERIC_7 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_ACR_32_0 +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_32_1 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_44_0 +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_44_1 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_48_0 +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_48_1 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_STATUS_0 +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_STATUS_1 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG3_AFMT_AUDIO_INFO0 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG3_AFMT_AUDIO_INFO1 +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG3_AFMT_60958_0 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG3_AFMT_60958_1 +#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG3_AFMT_AUDIO_CRC_CONTROL +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG3_AFMT_RAMP_CONTROL0 +#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG3_AFMT_RAMP_CONTROL1 +#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG3_AFMT_RAMP_CONTROL2 +#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG3_AFMT_RAMP_CONTROL3 +#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG3_AFMT_60958_2 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG3_AFMT_AUDIO_CRC_RESULT +#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG3_AFMT_STATUS +#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG3_AFMT_AUDIO_PACKET_CONTROL +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//DIG3_AFMT_VBI_PACKET_CONTROL +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG3_AFMT_INFOFRAME_CONTROL0 +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG3_AFMT_AUDIO_SRC_CONTROL +#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG3_DIG_BE_CNTL +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG3_DIG_BE_EN_CNTL +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG3_TMDS_CNTL +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG3_TMDS_CONTROL_CHAR +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG3_TMDS_CONTROL0_FEEDBACK +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG3_TMDS_STEREOSYNC_CTL_SEL +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG3_TMDS_CTL_BITS +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG3_TMDS_DCBALANCER_CONTROL +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG3_TMDS_SYNC_DCBALANCE_CHAR +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG3_TMDS_CTL0_1_GEN_CNTL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG3_TMDS_CTL2_3_GEN_CNTL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG3_DIG_VERSION +#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG3_DIG_LANE_ENABLE +#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG3_AFMT_CNTL +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG3_AFMT_VBI_PACKET_CONTROL1 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +//DIG3_FORCE_DIG_DISABLE +#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp3_dispdec +//DP3_DP_LINK_CNTL +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP3_DP_PIXEL_FORMAT +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP3_DP_MSA_COLORIMETRY +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP3_DP_CONFIG +#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP3_DP_VID_STREAM_CNTL +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP3_DP_STEER_FIFO +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP3_DP_MSA_MISC +#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP3_DP_VID_TIMING +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP3_DP_VID_N +#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP3_DP_VID_M +#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP3_DP_LINK_FRAMING_CNTL +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP3_DP_HBR2_EYE_PATTERN +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP3_DP_VID_MSA_VBID +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP3_DP_VID_INTERRUPT_CNTL +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP3_DP_DPHY_CNTL +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP3_DP_DPHY_TRAINING_PATTERN_SEL +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP3_DP_DPHY_SYM0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM1 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM2 +#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP3_DP_DPHY_8B10B_CNTL +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP3_DP_DPHY_PRBS_CNTL +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP3_DP_DPHY_SCRAM_CNTL +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP3_DP_DPHY_CRC_EN +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP3_DP_DPHY_CRC_CNTL +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP3_DP_DPHY_CRC_RESULT +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP3_DP_DPHY_CRC_MST_CNTL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP3_DP_DPHY_CRC_MST_STATUS +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP3_DP_DPHY_FAST_TRAINING +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP3_DP_DPHY_FAST_TRAINING_STATUS +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP3_DP_SEC_CNTL +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP3_DP_SEC_CNTL1 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING1 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING2 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING3 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING4 +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP3_DP_SEC_AUD_N +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_N_READBACK +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M_READBACK +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_TIMESTAMP +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP3_DP_SEC_PACKET_CNTL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP3_DP_MSE_RATE_CNTL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP3_DP_MSE_RATE_UPDATE +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP3_DP_MSE_SAT0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP3_DP_MSE_SAT1 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP3_DP_MSE_SAT2 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP3_DP_MSE_SAT_UPDATE +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP3_DP_MSE_LINK_TIMING +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP3_DP_MSE_MISC_CNTL +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP3_DP_DPHY_BS_SR_SWAP_CNTL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP3_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP3_DP_MSE_SAT0_STATUS +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT1_STATUS +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT2_STATUS +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP3_DP_MSA_TIMING_PARAM1 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM2 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM3 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP3_DP_MSA_TIMING_PARAM4 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP3_DP_MSO_CNTL +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP3_DP_MSO_CNTL1 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP3_DP_DSC_CNTL +#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP3_DP_SEC_CNTL2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP3_DP_SEC_CNTL3 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL4 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL5 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL6 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP3_DP_SEC_CNTL7 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP3_DP_DB_CNTL +#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP3_DP_MSA_VBID_MISC +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_METADATA_TRANSMISSION +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP3_DP_DSC_BYTES_PER_PIXEL +#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP3_DP_ALPM_CNTL +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dio_dig4_dispdec +//DIG4_DIG_FE_CNTL +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT 0xa +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT 0x10 +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT 0x12 +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0x13 +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x1c +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x1e +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG4_DIG_FE_CNTL__DIG_START_MASK 0x00000400L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK 0x00030000L +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK 0x00040000L +#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00080000L +#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L +#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10000000L +#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK 0xC0000000L +//DIG4_DIG_OUTPUT_CRC_CNTL +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG4_DIG_OUTPUT_CRC_RESULT +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG4_DIG_CLOCK_PATTERN +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG4_DIG_TEST_PATTERN +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG4_DIG_RANDOM_PATTERN_SEED +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG4_DIG_FIFO_STATUS +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x1a +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK 0x04000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG4_HDMI_METADATA_PACKET_CONTROL +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_CONTROL +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG4_HDMI_STATUS +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG4_HDMI_AUDIO_PACKET_CONTROL +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +//DIG4_HDMI_ACR_PACKET_CONTROL +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//DIG4_HDMI_VBI_PACKET_CONTROL +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +//DIG4_HDMI_INFOFRAME_CONTROL0 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L +//DIG4_HDMI_INFOFRAME_CONTROL1 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003F0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +//DIG4_HDMI_GC +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG4_AFMT_AUDIO_PACKET_CONTROL2 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//DIG4_AFMT_ISRC1_0 +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L +#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L +//DIG4_AFMT_ISRC1_1 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000FFL +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xFF000000L +//DIG4_AFMT_ISRC1_2 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000FFL +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xFF000000L +//DIG4_AFMT_ISRC1_3 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000FFL +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xFF000000L +//DIG4_AFMT_ISRC1_4 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000FFL +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xFF000000L +//DIG4_AFMT_ISRC2_0 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000FFL +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xFF000000L +//DIG4_AFMT_ISRC2_1 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000FFL +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xFF000000L +//DIG4_AFMT_ISRC2_2 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000FFL +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xFF000000L +//DIG4_AFMT_ISRC2_3 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000FFL +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000FF00L +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00FF0000L +#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xFF000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_DB_CONTROL +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG4_DME_CONTROL +#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DIG4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DIG4_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DIG4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DIG4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DIG4_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DIG4_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DIG4_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DIG4_AFMT_MPEG_INFO0 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000FF00L +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00FF0000L +#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xFF000000L +//DIG4_AFMT_MPEG_INFO1 +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000FFL +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L +#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L +//DIG4_AFMT_GENERIC_HDR +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_0 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_1 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_2 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_3 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_4 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_5 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_6 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xFF000000L +//DIG4_AFMT_GENERIC_7 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000FFL +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000FF00L +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00FF0000L +#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xFF000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_ACR_32_0 +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_32_1 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_44_0 +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_44_1 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_48_0 +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_48_1 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_STATUS_0 +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_STATUS_1 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG4_AFMT_AUDIO_INFO0 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//DIG4_AFMT_AUDIO_INFO1 +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//DIG4_AFMT_60958_0 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//DIG4_AFMT_60958_1 +#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//DIG4_AFMT_AUDIO_CRC_CONTROL +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//DIG4_AFMT_RAMP_CONTROL0 +#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//DIG4_AFMT_RAMP_CONTROL1 +#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//DIG4_AFMT_RAMP_CONTROL2 +#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//DIG4_AFMT_RAMP_CONTROL3 +#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//DIG4_AFMT_60958_2 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//DIG4_AFMT_AUDIO_CRC_RESULT +#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//DIG4_AFMT_STATUS +#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//DIG4_AFMT_AUDIO_PACKET_CONTROL +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//DIG4_AFMT_VBI_PACKET_CONTROL +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT 0x8 +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT 0x10 +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT 0x11 +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1c +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK 0x00000100L +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK 0x00010000L +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK 0x00020000L +#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xF0000000L +//DIG4_AFMT_INFOFRAME_CONTROL0 +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L +//DIG4_AFMT_AUDIO_SRC_CONTROL +#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//DIG4_DIG_BE_CNTL +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG4_DIG_BE_EN_CNTL +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 +#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L +//DIG4_TMDS_CNTL +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG4_TMDS_CONTROL_CHAR +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG4_TMDS_CONTROL0_FEEDBACK +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG4_TMDS_STEREOSYNC_CTL_SEL +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG4_TMDS_CTL_BITS +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG4_TMDS_DCBALANCER_CONTROL +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG4_TMDS_SYNC_DCBALANCE_CHAR +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG4_TMDS_CTL0_1_GEN_CNTL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG4_TMDS_CTL2_3_GEN_CNTL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG4_DIG_VERSION +#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L +//DIG4_DIG_LANE_ENABLE +#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 +#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 +#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 +#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 +#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 +#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L +#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L +#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L +#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L +#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L +//DIG4_AFMT_CNTL +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT 0x0 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT 0x8 +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK 0x00000001L +#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK 0x00000100L +//DIG4_AFMT_VBI_PACKET_CONTROL1 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x1 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x2 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x3 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT 0x4 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x5 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x6 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x7 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT 0x8 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x9 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0xa +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0xb +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT 0xc +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0xd +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0xe +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0xf +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT 0x10 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x12 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT 0x14 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x16 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT 0x18 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x1a +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT 0x1c +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x1e +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1f +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00000002L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000004L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00000008L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK 0x00000010L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00000020L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000040L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00000080L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK 0x00000100L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00000200L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000400L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00000800L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK 0x00001000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00002000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00004000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00008000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK 0x00010000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00040000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK 0x00100000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00400000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK 0x01000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK 0x04000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK 0x10000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK 0x40000000L +#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x80000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +//DIG4_FORCE_DIG_DISABLE +#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT 0x0 +#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp4_dispdec +//DP4_DP_LINK_CNTL +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L +//DP4_DP_PIXEL_FORMAT +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT 0x1c +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000007L +#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L +#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK 0x30000000L +//DP4_DP_MSA_COLORIMETRY +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP4_DP_CONFIG +#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP4_DP_VID_STREAM_CNTL +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP4_DP_STEER_FIFO +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +//DP4_DP_MSA_MISC +#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP4_DP_VID_TIMING +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT 0xa +#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK 0x00000C00L +#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP4_DP_VID_N +#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP4_DP_VID_M +#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP4_DP_LINK_FRAMING_CNTL +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP4_DP_HBR2_EYE_PATTERN +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP4_DP_VID_MSA_VBID +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP4_DP_VID_INTERRUPT_CNTL +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP4_DP_DPHY_CNTL +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP4_DP_DPHY_TRAINING_PATTERN_SEL +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP4_DP_DPHY_SYM0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM1 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM2 +#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP4_DP_DPHY_8B10B_CNTL +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP4_DP_DPHY_PRBS_CNTL +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP4_DP_DPHY_SCRAM_CNTL +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP4_DP_DPHY_CRC_EN +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L +//DP4_DP_DPHY_CRC_CNTL +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00FF0000L +//DP4_DP_DPHY_CRC_RESULT +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000FFL +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000FF00L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00FF0000L +#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xFF000000L +//DP4_DP_DPHY_CRC_MST_CNTL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP4_DP_DPHY_CRC_MST_STATUS +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L +#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP4_DP_DPHY_FAST_TRAINING +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP4_DP_DPHY_FAST_TRAINING_STATUS +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L +//DP4_DP_SEC_CNTL +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L +//DP4_DP_SEC_CNTL1 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING1 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING2 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING3 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING4 +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP4_DP_SEC_AUD_N +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_N_READBACK +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M_READBACK +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_TIMESTAMP +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP4_DP_SEC_PACKET_CNTL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000EL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003F00L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L +//DP4_DP_MSE_RATE_CNTL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP4_DP_MSE_RATE_UPDATE +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP4_DP_MSE_SAT0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP4_DP_MSE_SAT1 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP4_DP_MSE_SAT2 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP4_DP_MSE_SAT_UPDATE +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP4_DP_MSE_LINK_TIMING +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP4_DP_MSE_MISC_CNTL +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP4_DP_DPHY_BS_SR_SWAP_CNTL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP4_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP4_DP_MSE_SAT0_STATUS +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT1_STATUS +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT2_STATUS +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP4_DP_MSA_TIMING_PARAM1 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM2 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM3 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP4_DP_MSA_TIMING_PARAM4 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP4_DP_MSO_CNTL +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP4_DP_MSO_CNTL1 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP4_DP_DSC_CNTL +#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT 0x0 +#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT 0x10 +#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK 0x00000003L +#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//DP4_DP_SEC_CNTL2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT 0x1c +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK 0x10000000L +//DP4_DP_SEC_CNTL3 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL4 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL5 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL6 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +//DP4_DP_SEC_CNTL7 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP4_DP_DB_CNTL +#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP4_DP_MSA_VBID_MISC +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_METADATA_TRANSMISSION +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP4_DP_DSC_BYTES_PER_PIXEL +#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//DP4_DP_ALPM_CNTL +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_EN__SHIFT 0x0 +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICA__GENERICA_EN_MASK 0x00000001L +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_GENERICB +#define DC_GENERICB__GENERICB_EN__SHIFT 0x0 +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 +#define DC_GENERICB__GENERICB_EN_MASK 0x00000001L +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x0000F000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x000F0000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00F00000L +#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x0F000000L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//UNIPHYA_LINK_CNTL +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYB_LINK_CNTL +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYC_LINK_CNTL +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYC_CHANNEL_XBAR_CNTL +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYD_LINK_CNTL +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYD_CHANNEL_XBAR_CNTL +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//UNIPHYE_LINK_CNTL +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x18 +#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L +#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L +#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L +#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x03000000L +//UNIPHYE_CHANNEL_XBAR_CNTL +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT 0x1c +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK 0x10000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT 0x4 +#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT 0x8 +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT 0xc +#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT 0x10 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 +#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK 0x000000F0L +#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK 0x00000F00L +#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK 0x0000F000L +#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK 0x000F0000L +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT 0x11 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK 0x000E0000L +//LVTMA_PWRSEQ_CNTL +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L +#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L +#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L +#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L +//LVTMA_PWRSEQ_STATE +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L +#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000F00L +//LVTMA_PWRSEQ_REF_DIV +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 +#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000FFFL +#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xFFFF0000L +//LVTMA_PWRSEQ_DELAY1 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000FFL +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000FF00L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00FF0000L +#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xFF000000L +//LVTMA_PWRSEQ_DELAY2 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000FFL +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000FF00L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00FF0000L +#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L +//BL_PWM_CNTL +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e +#define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f +#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000FFFFL +#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L +#define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L +//BL_PWM_CNTL2 +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f +#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000FFFFL +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L +#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L +//BL_PWM_PERIOD_CNTL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000FFFFL +#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000F0000L +//BL_PWM_GRP1_REG_LOCK +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000E0000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L +#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x7 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x8 +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x9 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0xa +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0xb +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0xc +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0xd +#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT 0x14 +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT 0x18 +#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT 0x1a +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000080L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000100L +#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000200L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000400L +#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000800L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00001000L +#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x00002000L +#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00010000L +#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK 0x00100000L +#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK 0x01000000L +#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK 0x04000000L + + +// addressBlock: dce_dc_dcio_dcio_chip_dispdec +//DC_GPIO_GENERIC_MASK +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x0000000CL +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x000000C0L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000C00L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x0000C000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x000C0000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00C00000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x0C000000L +//DC_GPIO_GENERIC_A +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L +#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L +//DC_GPIO_GENERIC_EN +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L +#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L +//DC_GPIO_GENERIC_Y +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L +#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC3_MASK +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC3_A +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +//DC_GPIO_DDC3_EN +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC3_Y +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC4_MASK +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC4_A +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +//DC_GPIO_DDC4_EN +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC4_Y +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC5_MASK +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xF0000000L +//DC_GPIO_DDC5_A +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +//DC_GPIO_DDC5_EN +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC5_Y +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L +#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0F000000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_GENLK_MASK +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x4 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xc +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x14 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1c +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000030L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L +#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00003000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00300000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L +#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x30000000L +//DC_GPIO_GENLK_A +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L +#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L +#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L +//DC_GPIO_GENLK_EN +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L +#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L +#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L +//DC_GPIO_GENLK_Y +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L +#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L +#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L +//DC_GPIO_HPD_MASK +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT 0x1 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT 0x2 +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT 0x3 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK 0x00000002L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK 0x00000004L +#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK 0x00000008L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x000000C0L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000C00L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x000C0000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00C00000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x0C000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L +#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0xC0000000L +//DC_GPIO_HPD_A +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c +#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L +#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L +#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L +#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L +//DC_GPIO_HPD_EN +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT 0x1 +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT 0x2 +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT 0x3 +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT 0x4 +#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT 0x5 +#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT 0x6 +#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT 0x7 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT 0x9 +#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT 0xa +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT 0x11 +#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT 0x12 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x14 +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT 0x15 +#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT 0x16 +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x18 +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT 0x19 +#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT 0x1a +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT 0x1d +#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT 0x1e +#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L +#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK 0x00000002L +#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK 0x00000004L +#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK 0x00000008L +#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK 0x00000010L +#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK 0x00000020L +#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK 0x00000040L +#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK 0x00000080L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L +#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK 0x00000200L +#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK 0x00000400L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L +#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK 0x00020000L +#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK 0x00040000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x00100000L +#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK 0x00200000L +#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK 0x00400000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x01000000L +#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK 0x02000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK 0x04000000L +#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L +#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK 0x20000000L +#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK 0x40000000L +//DC_GPIO_HPD_Y +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c +#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L +#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L +//DC_GPIO_PWRSEQ_MASK +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x000000C0L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x0000C000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00C00000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x02000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x04000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000L +#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000L +//DC_GPIO_PWRSEQ_A +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000L +//DC_GPIO_PWRSEQ_EN +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000L +//DC_GPIO_PWRSEQ_Y +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x01000000L +#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK 0x00000F00L +#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK 0x0000F000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//DC_GPIO_PAD_STRENGTH_2 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x00000700L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x00007000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000F0000L +#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00F00000L +#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xC0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT 0x0 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT 0x1 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT 0x3 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT 0x4 +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT 0x5 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT 0x6 +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT 0x7 +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT 0x8 +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT 0x17 +#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT 0x18 +#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT 0x1c +#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK 0x00000001L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK 0x00000002L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK 0x00000004L +#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK 0x00000008L +#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK 0x00000010L +#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK 0x00000020L +#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK 0x00000040L +#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK 0x00000080L +#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK 0x00000100L +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L +#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK 0x00800000L +#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK 0x03000000L +#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK 0x70000000L +//DC_GPIO_TX12_EN +#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT 0x0 +#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT 0x1 +#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT 0x2 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT 0x3 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT 0x4 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT 0x5 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT 0x6 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT 0x7 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT 0x8 +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT 0x9 +#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK 0x00000001L +#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK 0x00000002L +#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK 0x00000004L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK 0x00000008L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK 0x00000010L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK 0x00000020L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK 0x00000040L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK 0x00000080L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK 0x00000100L +#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK 0x00000200L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0x40000000L +//DC_GPIO_AUX_CTRL_2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK 0x40000000L +//DC_GPIO_RXEN +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT 0x0 +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT 0x1 +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT 0x2 +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT 0x3 +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT 0x4 +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT 0x5 +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT 0x6 +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT 0x8 +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT 0x9 +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT 0xa +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT 0xb +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT 0xc +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT 0xd +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT 0xe +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT 0xf +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT 0x10 +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT 0x11 +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT 0x12 +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT 0x13 +#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT 0x14 +#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT 0x15 +#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT 0x16 +#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK 0x00000001L +#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK 0x00000002L +#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK 0x00000004L +#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK 0x00000008L +#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK 0x00000010L +#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK 0x00000020L +#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK 0x00000040L +#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK 0x00000100L +#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK 0x00000200L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK 0x00000400L +#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK 0x00000800L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK 0x00001000L +#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK 0x00002000L +#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK 0x00004000L +#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK 0x00008000L +#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK 0x00010000L +#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK 0x00020000L +#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK 0x00040000L +#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK 0x00080000L +#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK 0x00100000L +#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK 0x00200000L +#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK 0x00400000L +//DC_GPIO_PULLUPEN +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT 0x0 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT 0x1 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT 0x2 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT 0x3 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT 0x4 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT 0x5 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT 0x6 +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT 0x8 +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT 0x9 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT 0xe +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT 0xf +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT 0x10 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT 0x11 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT 0x12 +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT 0x13 +#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT 0x14 +#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT 0x15 +#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT 0x16 +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK 0x00000001L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK 0x00000002L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK 0x00000004L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK 0x00000008L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK 0x00000010L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK 0x00000020L +#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK 0x00000040L +#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK 0x00000100L +#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK 0x00000200L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK 0x00004000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK 0x00008000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK 0x00010000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK 0x00020000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK 0x00040000L +#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK 0x00080000L +#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK 0x00100000L +#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK 0x00200000L +#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK 0x00400000L +//DC_GPIO_AUX_CTRL_3 +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L +//DC_GPIO_AUX_CTRL_4 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L +//DC_GPIO_AUX_CTRL_5 +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L +//AUXI2C_PAD_ALL_PWR_OK +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +//DSC_TOP0_DSC_TOP_CONTROL +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP0_DSC_DEBUG_CONTROL +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +//DSCCIF0_DSCCIF_CONFIG0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF0_DSCCIF_CONFIG1 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +//DSCC0_DSCC_CONFIG0 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC0_DSCC_CONFIG1 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC0_DSCC_STATUS +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC0_DSCC_PPS_CONFIG0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG1 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG2 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG3 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG4 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG5 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG6 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC0_DSCC_PPS_CONFIG7 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG8 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG9 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG11 +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG12 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG13 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG14 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG15 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG16 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG17 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG18 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG19 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG20 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG21 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG22 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC0_DSCC_MEM_POWER_CONTROL +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_MAX_ABS_ERROR0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC0_DSCC_MAX_ABS_ERROR1 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON19_PERFCOUNTER_CNTL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_CNTL2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_STATE +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON19_PERFMON_CNTL +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON19_PERFMON_CNTL2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON19_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON19_PERFMON_CVALUE_LOW +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON19_PERFMON_HI +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFMON_LOW +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +//DSC_TOP1_DSC_TOP_CONTROL +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP1_DSC_DEBUG_CONTROL +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +//DSCCIF1_DSCCIF_CONFIG0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF1_DSCCIF_CONFIG1 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +//DSCC1_DSCC_CONFIG0 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC1_DSCC_CONFIG1 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC1_DSCC_STATUS +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC1_DSCC_PPS_CONFIG0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG1 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG2 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG3 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG4 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG5 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG6 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC1_DSCC_PPS_CONFIG7 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG8 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG9 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG11 +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG12 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG13 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG14 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG15 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG16 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG17 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG18 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG19 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG20 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG21 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG22 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC1_DSCC_MEM_POWER_CONTROL +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_MAX_ABS_ERROR0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC1_DSCC_MAX_ABS_ERROR1 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON20_PERFCOUNTER_CNTL +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFCOUNTER_CNTL2 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFCOUNTER_STATE +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON20_PERFMON_CNTL +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON20_PERFMON_CNTL2 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON20_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON20_PERFMON_CVALUE_LOW +#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON20_PERFMON_HI +#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFMON_LOW +#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +//DSC_TOP2_DSC_TOP_CONTROL +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP2_DSC_DEBUG_CONTROL +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +//DSCCIF2_DSCCIF_CONFIG0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF2_DSCCIF_CONFIG1 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +//DSCC2_DSCC_CONFIG0 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC2_DSCC_CONFIG1 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC2_DSCC_STATUS +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC2_DSCC_PPS_CONFIG0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG1 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG2 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG3 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG4 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG5 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG6 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC2_DSCC_PPS_CONFIG7 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG8 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG9 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG11 +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG12 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG13 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG14 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG15 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG16 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG17 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG18 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG19 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG20 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG21 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG22 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC2_DSCC_MEM_POWER_CONTROL +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_MAX_ABS_ERROR0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC2_DSCC_MAX_ABS_ERROR1 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON21_PERFCOUNTER_CNTL +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFCOUNTER_CNTL2 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFCOUNTER_STATE +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON21_PERFMON_CNTL +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON21_PERFMON_CNTL2 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON21_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON21_PERFMON_CVALUE_LOW +#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON21_PERFMON_HI +#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFMON_LOW +#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec +//DSC_TOP3_DSC_TOP_CONTROL +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP3_DSC_DEBUG_CONTROL +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec +//DSCCIF3_DSCCIF_CONFIG0 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF3_DSCCIF_CONFIG1 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec +//DSCC3_DSCC_CONFIG0 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC3_DSCC_CONFIG1 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC3_DSCC_STATUS +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC3_DSCC_PPS_CONFIG0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG1 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG2 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG3 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG4 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG5 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG6 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC3_DSCC_PPS_CONFIG7 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG8 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG9 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG11 +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG12 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG13 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG14 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG15 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG16 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG17 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG18 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG19 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG20 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG21 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG22 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC3_DSCC_MEM_POWER_CONTROL +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_MAX_ABS_ERROR0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC3_DSCC_MAX_ABS_ERROR1 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON22_PERFCOUNTER_CNTL +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFCOUNTER_CNTL2 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFCOUNTER_STATE +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON22_PERFMON_CNTL +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON22_PERFMON_CNTL2 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON22_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON22_PERFMON_CVALUE_LOW +#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON22_PERFMON_HI +#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFMON_LOW +#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec +//DSC_TOP4_DSC_TOP_CONTROL +#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP4_DSC_DEBUG_CONTROL +#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec +//DSCCIF4_DSCCIF_CONFIG0 +#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF4_DSCCIF_CONFIG1 +#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec +//DSCC4_DSCC_CONFIG0 +#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC4_DSCC_CONFIG1 +#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC4_DSCC_STATUS +#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC4_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC4_DSCC_PPS_CONFIG0 +#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC4_DSCC_PPS_CONFIG1 +#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG2 +#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG3 +#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG4 +#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG5 +#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG6 +#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC4_DSCC_PPS_CONFIG7 +#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG8 +#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG9 +#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG10 +#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC4_DSCC_PPS_CONFIG11 +#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC4_DSCC_PPS_CONFIG12 +#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC4_DSCC_PPS_CONFIG13 +#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC4_DSCC_PPS_CONFIG14 +#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC4_DSCC_PPS_CONFIG15 +#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC4_DSCC_PPS_CONFIG16 +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC4_DSCC_PPS_CONFIG17 +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC4_DSCC_PPS_CONFIG18 +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC4_DSCC_PPS_CONFIG19 +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC4_DSCC_PPS_CONFIG20 +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC4_DSCC_PPS_CONFIG21 +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC4_DSCC_PPS_CONFIG22 +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC4_DSCC_MEM_POWER_CONTROL +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC4_DSCC_MAX_ABS_ERROR0 +#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC4_DSCC_MAX_ABS_ERROR1 +#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON23_PERFCOUNTER_CNTL +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFCOUNTER_CNTL2 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFCOUNTER_STATE +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON23_PERFMON_CNTL +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON23_PERFMON_CNTL2 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON23_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON23_PERFMON_CVALUE_LOW +#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON23_PERFMON_HI +#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFMON_LOW +#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec +//DSC_TOP5_DSC_TOP_CONTROL +#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +//DSC_TOP5_DSC_DEBUG_CONTROL +#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L + + +// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec +//DSCCIF5_DSCCIF_CONFIG0 +#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT 0x0 +#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x4 +#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x8 +#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK 0x00000001L +#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00000010L +#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000100L +#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//DSCCIF5_DSCCIF_CONFIG1 +#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT 0x0 +#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT 0x10 +#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec +//DSCC5_DSCC_CONFIG0 +#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC5_DSCC_CONFIG1 +#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC5_DSCC_STATUS +#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC5_DSCC_INTERRUPT_CONTROL_STATUS +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT 0x0 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT 0x1 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT 0x2 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT 0x3 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT 0x4 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT 0x5 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT 0x6 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT 0x7 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT 0x8 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT 0x9 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT 0xa +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT 0xb +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x10 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x11 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x12 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x13 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x14 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x15 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x16 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT 0x17 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x18 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x19 +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1a +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT 0x1b +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK 0x00000001L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK 0x00000002L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK 0x00000004L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK 0x00000008L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK 0x00000010L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK 0x00000020L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK 0x00000040L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK 0x00000080L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK 0x00000100L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK 0x00000200L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK 0x00000400L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK 0x00000800L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK 0x00010000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK 0x00020000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK 0x00040000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK 0x00080000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00100000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00200000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00400000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK 0x00800000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK 0x01000000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK 0x02000000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK 0x04000000L +#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK 0x08000000L +//DSCC5_DSCC_PPS_CONFIG0 +#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC5_DSCC_PPS_CONFIG1 +#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG2 +#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG3 +#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG4 +#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG5 +#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG6 +#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC5_DSCC_PPS_CONFIG7 +#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG8 +#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG9 +#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG10 +#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC5_DSCC_PPS_CONFIG11 +#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC5_DSCC_PPS_CONFIG12 +#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC5_DSCC_PPS_CONFIG13 +#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC5_DSCC_PPS_CONFIG14 +#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC5_DSCC_PPS_CONFIG15 +#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC5_DSCC_PPS_CONFIG16 +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC5_DSCC_PPS_CONFIG17 +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC5_DSCC_PPS_CONFIG18 +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC5_DSCC_PPS_CONFIG19 +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC5_DSCC_PPS_CONFIG20 +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC5_DSCC_PPS_CONFIG21 +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC5_DSCC_PPS_CONFIG22 +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC5_DSCC_MEM_POWER_CONTROL +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT 0x18 +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT 0x1c +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK 0x00030000L +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK 0x01000000L +#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK 0x30000000L +//DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC5_DSCC_MAX_ABS_ERROR0 +#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC5_DSCC_MAX_ABS_ERROR1 +#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL +#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL +#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL +#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL +#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT 0x0 +#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK 0x0003FFFFL +//DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L + + +// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON24_PERFCOUNTER_CNTL +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON24_PERFCOUNTER_CNTL2 +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON24_PERFCOUNTER_STATE +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON24_PERFMON_CNTL +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON24_PERFMON_CNTL2 +#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON24_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON24_PERFMON_CVALUE_LOW +#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON24_PERFMON_HI +#define DC_PERFMON24_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON24_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON24_PERFMON_LOW +#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +//DMCUB_REGION0_OFFSET +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION0_OFFSET_HIGH +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION1_OFFSET +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION1_OFFSET_HIGH +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION2_OFFSET +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION2_OFFSET_HIGH +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION4_OFFSET +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION4_OFFSET_HIGH +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION5_OFFSET +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION5_OFFSET_HIGH +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION6_OFFSET +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION6_OFFSET_HIGH +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION7_OFFSET +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION7_OFFSET_HIGH +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION0_TOP_ADDRESS +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L +//DMCUB_REGION1_TOP_ADDRESS +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L +//DMCUB_REGION2_TOP_ADDRESS +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L +//DMCUB_REGION4_TOP_ADDRESS +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L +//DMCUB_REGION5_TOP_ADDRESS +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L +//DMCUB_REGION6_TOP_ADDRESS +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L +//DMCUB_REGION7_TOP_ADDRESS +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_BASE_ADDRESS +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW1_BASE_ADDRESS +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW2_BASE_ADDRESS +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW3_BASE_ADDRESS +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW4_BASE_ADDRESS +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW5_BASE_ADDRESS +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW6_BASE_ADDRESS +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW7_BASE_ADDRESS +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW0_TOP_ADDRESS +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW1_TOP_ADDRESS +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW2_TOP_ADDRESS +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW3_TOP_ADDRESS +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW4_TOP_ADDRESS +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW5_TOP_ADDRESS +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW6_TOP_ADDRESS +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW7_TOP_ADDRESS +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_OFFSET +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW0_OFFSET_HIGH +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW1_OFFSET +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW1_OFFSET_HIGH +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW2_OFFSET +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW2_OFFSET_HIGH +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW3_OFFSET +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW3_OFFSET_HIGH +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW4_OFFSET +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW4_OFFSET_HIGH +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW5_OFFSET +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW5_OFFSET_HIGH +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW6_OFFSET +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW6_OFFSET_HIGH +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW7_OFFSET +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW7_OFFSET_HIGH +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_INTERRUPT_ENABLE +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0xd +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00002000L +//DMCUB_INTERRUPT_ACK +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0xd +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00002000L +//DMCUB_INTERRUPT_STATUS +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0xd +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0xe +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0xf +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00002000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00004000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00008000L +//DMCUB_INTERRUPT_TYPE +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0xd +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00002000L +//DMCUB_EXT_INTERRUPT_STATUS +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L +//DMCUB_EXT_INTERRUPT_CTXID +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL +//DMCUB_EXT_INTERRUPT_ACK +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L +//DMCUB_INST_FETCH_FAULT_ADDR +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_DATA_WRITE_FAULT_ADDR +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_SEC_CNTL +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT 0x0 +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10 +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11 +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15 +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18 +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19 +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK 0x00000007L +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L +//DMCUB_MEM_CNTL +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4 +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT 0x8 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT 0xc +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK 0x00000700L +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK 0x00007000L +//DMCUB_INBOX0_BASE_ADDRESS +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_SIZE +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0 +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_WPTR +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0 +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_RPTR +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0 +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_BASE_ADDRESS +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_SIZE +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0 +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_WPTR +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0 +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_RPTR +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0 +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_BASE_ADDRESS +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_SIZE +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_WPTR +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_RPTR +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_BASE_ADDRESS +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_SIZE +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_WPTR +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_RPTR +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER1 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL +//DMCUB_TIMER_WINDOW +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0 +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L +//DMCUB_SCRATCH0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH1 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH2 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH3 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH4 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH5 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH6 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH7 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH8 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH9 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH10 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH11 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH12 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH13 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH14 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH15 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL +//DMCUB_CNTL +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0 +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8 +#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10 +#define DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT 0x11 +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12 +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13 +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14 +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L +#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L +#define DMCUB_CNTL__DMCUB_SOFT_RESET_MASK 0x00020000L +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L +//DMCUB_GPINT_DATAIN0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN1 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAOUT +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0 +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL +//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_LS_WAKE_INT_ENABLE +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0 +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL +//DMCUB_MEM_PWR_CNTL +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L +//DMCUB_TIMER_CURRENT +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0 +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL +//DMCUB_PROC_ID +#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0 +#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec +//MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x00000002L +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0x000F0000L +#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R +#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x00001FFFL +//MCIF_WB2_MCIF_WB_BUFMGR_STATUS +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x2 +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000002L +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000004L +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB2_MCIF_WB_BUF_PITCH +#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB2_MCIF_WB_BUF_1_STATUS +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x00008000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB2_MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x00010000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00080000L +//MCIF_WB2_MCIF_WB_BUF_2_STATUS +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x00008000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB2_MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x00010000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00080000L +//MCIF_WB2_MCIF_WB_BUF_3_STATUS +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x00008000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB2_MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x00010000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00080000L +//MCIF_WB2_MCIF_WB_BUF_4_STATUS +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x00008000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000L +//MCIF_WB2_MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x11 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x12 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x13 +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x00001FFFL +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x00010000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00020000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00040000L +#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00080000L +//MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x16 +#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFC00000L +//MCIF_WB2_MCIF_WB_SCLK_CHANGE +#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x0000000EL +//MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX +#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA +#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x0003FFFFL +//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x0003FFFFL +//MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4 +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5 +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x00000010L +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x00000020L +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x0007FFFFL +//MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x2 +#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x4 +#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000004L +#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00000070L +//MCIF_WB2_MCIF_WB_WATERMARK +#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x0000FFFFL +//MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB2_MCIF_WB_WARM_UP_CNTL +#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT 0x8 +#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK 0x0000FF00L +//MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK 0x00000001L +#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MCIF_WB2_MULTI_LEVEL_QOS_CTRL +#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L + + +// addressBlock: dce_dc_dchvm_hvm_dispdec +//DCHVM_CTRL0 +#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT 0x0 +#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK 0x00000001L +//DCHVM_CTRL1 +#define DCHVM_CTRL1__DUMMY1__SHIFT 0x0 +#define DCHVM_CTRL1__DUMMY1_MASK 0xFFFFFFFFL +//DCHVM_CLK_CTRL +#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT 0x1 +#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT 0x4 +#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT 0x5 +#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT 0x8 +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT 0xa +#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK 0x00000002L +#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK 0x00000010L +#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK 0x00000020L +#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK 0x00000300L +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK 0x00000C00L +//DCHVM_MEM_CTRL +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT 0x0 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT 0x2 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT 0x4 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK 0x00000001L +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK 0x0000000CL +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK 0x00000030L +//DCHVM_RIOMMU_CTRL0 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT 0x0 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT 0x1 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK 0x00000001L +#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK 0x00000002L +//DCHVM_RIOMMU_STAT0 +#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT 0x0 +#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT 0x1 +#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK 0x00000001L +#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK 0x00000002L + + +// addressBlock: vga_vgaseqind +//SEQ00 +#define SEQ00__SEQ_RST0B__SHIFT 0x0 +#define SEQ00__SEQ_RST1B__SHIFT 0x1 +#define SEQ00__SEQ_RST0B_MASK 0x01L +#define SEQ00__SEQ_RST1B_MASK 0x02L +//SEQ01 +#define SEQ01__SEQ_DOT8__SHIFT 0x0 +#define SEQ01__SEQ_SHIFT2__SHIFT 0x2 +#define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 +#define SEQ01__SEQ_SHIFT4__SHIFT 0x4 +#define SEQ01__SEQ_MAXBW__SHIFT 0x5 +#define SEQ01__SEQ_DOT8_MASK 0x01L +#define SEQ01__SEQ_SHIFT2_MASK 0x04L +#define SEQ01__SEQ_PCLKBY2_MASK 0x08L +#define SEQ01__SEQ_SHIFT4_MASK 0x10L +#define SEQ01__SEQ_MAXBW_MASK 0x20L +//SEQ02 +#define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 +#define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 +#define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 +#define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 +#define SEQ02__SEQ_MAP0_EN_MASK 0x01L +#define SEQ02__SEQ_MAP1_EN_MASK 0x02L +#define SEQ02__SEQ_MAP2_EN_MASK 0x04L +#define SEQ02__SEQ_MAP3_EN_MASK 0x08L +//SEQ03 +#define SEQ03__SEQ_FONT_B1__SHIFT 0x0 +#define SEQ03__SEQ_FONT_B2__SHIFT 0x1 +#define SEQ03__SEQ_FONT_A1__SHIFT 0x2 +#define SEQ03__SEQ_FONT_A2__SHIFT 0x3 +#define SEQ03__SEQ_FONT_B0__SHIFT 0x4 +#define SEQ03__SEQ_FONT_A0__SHIFT 0x5 +#define SEQ03__SEQ_FONT_B1_MASK 0x01L +#define SEQ03__SEQ_FONT_B2_MASK 0x02L +#define SEQ03__SEQ_FONT_A1_MASK 0x04L +#define SEQ03__SEQ_FONT_A2_MASK 0x08L +#define SEQ03__SEQ_FONT_B0_MASK 0x10L +#define SEQ03__SEQ_FONT_A0_MASK 0x20L +//SEQ04 +#define SEQ04__SEQ_256K__SHIFT 0x1 +#define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 +#define SEQ04__SEQ_CHAIN__SHIFT 0x3 +#define SEQ04__SEQ_256K_MASK 0x02L +#define SEQ04__SEQ_ODDEVEN_MASK 0x04L +#define SEQ04__SEQ_CHAIN_MASK 0x08L + + +// addressBlock: vga_vgacrtind +//CRT00 +#define CRT00__H_TOTAL__SHIFT 0x0 +#define CRT00__H_TOTAL_MASK 0xFFL +//CRT01 +#define CRT01__H_DISP_END__SHIFT 0x0 +#define CRT01__H_DISP_END_MASK 0xFFL +//CRT02 +#define CRT02__H_BLANK_START__SHIFT 0x0 +#define CRT02__H_BLANK_START_MASK 0xFFL +//CRT03 +#define CRT03__H_BLANK_END__SHIFT 0x0 +#define CRT03__H_DE_SKEW__SHIFT 0x5 +#define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 +#define CRT03__H_BLANK_END_MASK 0x1FL +#define CRT03__H_DE_SKEW_MASK 0x60L +#define CRT03__CR10CR11_R_DIS_B_MASK 0x80L +//CRT04 +#define CRT04__H_SYNC_START__SHIFT 0x0 +#define CRT04__H_SYNC_START_MASK 0xFFL +//CRT05 +#define CRT05__H_SYNC_END__SHIFT 0x0 +#define CRT05__H_SYNC_SKEW__SHIFT 0x5 +#define CRT05__H_BLANK_END_B5__SHIFT 0x7 +#define CRT05__H_SYNC_END_MASK 0x1FL +#define CRT05__H_SYNC_SKEW_MASK 0x60L +#define CRT05__H_BLANK_END_B5_MASK 0x80L +//CRT06 +#define CRT06__V_TOTAL__SHIFT 0x0 +#define CRT06__V_TOTAL_MASK 0xFFL +//CRT07 +#define CRT07__V_TOTAL_B8__SHIFT 0x0 +#define CRT07__V_DISP_END_B8__SHIFT 0x1 +#define CRT07__V_SYNC_START_B8__SHIFT 0x2 +#define CRT07__V_BLANK_START_B8__SHIFT 0x3 +#define CRT07__LINE_CMP_B8__SHIFT 0x4 +#define CRT07__V_TOTAL_B9__SHIFT 0x5 +#define CRT07__V_DISP_END_B9__SHIFT 0x6 +#define CRT07__V_SYNC_START_B9__SHIFT 0x7 +#define CRT07__V_TOTAL_B8_MASK 0x01L +#define CRT07__V_DISP_END_B8_MASK 0x02L +#define CRT07__V_SYNC_START_B8_MASK 0x04L +#define CRT07__V_BLANK_START_B8_MASK 0x08L +#define CRT07__LINE_CMP_B8_MASK 0x10L +#define CRT07__V_TOTAL_B9_MASK 0x20L +#define CRT07__V_DISP_END_B9_MASK 0x40L +#define CRT07__V_SYNC_START_B9_MASK 0x80L +//CRT08 +#define CRT08__ROW_SCAN_START__SHIFT 0x0 +#define CRT08__BYTE_PAN__SHIFT 0x5 +#define CRT08__ROW_SCAN_START_MASK 0x1FL +#define CRT08__BYTE_PAN_MASK 0x60L +//CRT09 +#define CRT09__MAX_ROW_SCAN__SHIFT 0x0 +#define CRT09__V_BLANK_START_B9__SHIFT 0x5 +#define CRT09__LINE_CMP_B9__SHIFT 0x6 +#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 +#define CRT09__MAX_ROW_SCAN_MASK 0x1FL +#define CRT09__V_BLANK_START_B9_MASK 0x20L +#define CRT09__LINE_CMP_B9_MASK 0x40L +#define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80L +//CRT0A +#define CRT0A__CURSOR_START__SHIFT 0x0 +#define CRT0A__CURSOR_DISABLE__SHIFT 0x5 +#define CRT0A__CURSOR_START_MASK 0x1FL +#define CRT0A__CURSOR_DISABLE_MASK 0x20L +//CRT0B +#define CRT0B__CURSOR_END__SHIFT 0x0 +#define CRT0B__CURSOR_SKEW__SHIFT 0x5 +#define CRT0B__CURSOR_END_MASK 0x1FL +#define CRT0B__CURSOR_SKEW_MASK 0x60L +//CRT0C +#define CRT0C__DISP_START__SHIFT 0x0 +#define CRT0C__DISP_START_MASK 0xFFL +//CRT0D +#define CRT0D__DISP_START__SHIFT 0x0 +#define CRT0D__DISP_START_MASK 0xFFL +//CRT0E +#define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 +#define CRT0E__CURSOR_LOC_HI_MASK 0xFFL +//CRT0F +#define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 +#define CRT0F__CURSOR_LOC_LO_MASK 0xFFL +//CRT10 +#define CRT10__V_SYNC_START__SHIFT 0x0 +#define CRT10__V_SYNC_START_MASK 0xFFL +//CRT11 +#define CRT11__V_SYNC_END__SHIFT 0x0 +#define CRT11__V_INTR_CLR__SHIFT 0x4 +#define CRT11__V_INTR_EN__SHIFT 0x5 +#define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 +#define CRT11__C0T7_WR_ONLY__SHIFT 0x7 +#define CRT11__V_SYNC_END_MASK 0x0FL +#define CRT11__V_INTR_CLR_MASK 0x10L +#define CRT11__V_INTR_EN_MASK 0x20L +#define CRT11__SEL5_REFRESH_CYC_MASK 0x40L +#define CRT11__C0T7_WR_ONLY_MASK 0x80L +//CRT12 +#define CRT12__V_DISP_END__SHIFT 0x0 +#define CRT12__V_DISP_END_MASK 0xFFL +//CRT13 +#define CRT13__DISP_PITCH__SHIFT 0x0 +#define CRT13__DISP_PITCH_MASK 0xFFL +//CRT14 +#define CRT14__UNDRLN_LOC__SHIFT 0x0 +#define CRT14__ADDR_CNT_BY4__SHIFT 0x5 +#define CRT14__DOUBLE_WORD__SHIFT 0x6 +#define CRT14__UNDRLN_LOC_MASK 0x1FL +#define CRT14__ADDR_CNT_BY4_MASK 0x20L +#define CRT14__DOUBLE_WORD_MASK 0x40L +//CRT15 +#define CRT15__V_BLANK_START__SHIFT 0x0 +#define CRT15__V_BLANK_START_MASK 0xFFL +//CRT16 +#define CRT16__V_BLANK_END__SHIFT 0x0 +#define CRT16__V_BLANK_END_MASK 0xFFL +//CRT17 +#define CRT17__RA0_AS_A13B__SHIFT 0x0 +#define CRT17__RA1_AS_A14B__SHIFT 0x1 +#define CRT17__VCOUNT_BY2__SHIFT 0x2 +#define CRT17__ADDR_CNT_BY2__SHIFT 0x3 +#define CRT17__WRAP_A15TOA0__SHIFT 0x5 +#define CRT17__BYTE_MODE__SHIFT 0x6 +#define CRT17__CRTC_SYNC_EN__SHIFT 0x7 +#define CRT17__RA0_AS_A13B_MASK 0x01L +#define CRT17__RA1_AS_A14B_MASK 0x02L +#define CRT17__VCOUNT_BY2_MASK 0x04L +#define CRT17__ADDR_CNT_BY2_MASK 0x08L +#define CRT17__WRAP_A15TOA0_MASK 0x20L +#define CRT17__BYTE_MODE_MASK 0x40L +#define CRT17__CRTC_SYNC_EN_MASK 0x80L +//CRT18 +#define CRT18__LINE_CMP__SHIFT 0x0 +#define CRT18__LINE_CMP_MASK 0xFFL +//CRT1E +#define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 +#define CRT1E__GRPH_DEC_RD1_MASK 0x02L +//CRT1F +#define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 +#define CRT1F__GRPH_DEC_RD0_MASK 0xFFL +//CRT22 +#define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 +#define CRT22__GRPH_LATCH_DATA_MASK 0xFFL + + +// addressBlock: vga_vgagrphind +//GRA00 +#define GRA00__GRPH_SET_RESET0__SHIFT 0x0 +#define GRA00__GRPH_SET_RESET1__SHIFT 0x1 +#define GRA00__GRPH_SET_RESET2__SHIFT 0x2 +#define GRA00__GRPH_SET_RESET3__SHIFT 0x3 +#define GRA00__GRPH_SET_RESET0_MASK 0x01L +#define GRA00__GRPH_SET_RESET1_MASK 0x02L +#define GRA00__GRPH_SET_RESET2_MASK 0x04L +#define GRA00__GRPH_SET_RESET3_MASK 0x08L +//GRA01 +#define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 +#define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 +#define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 +#define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 +#define GRA01__GRPH_SET_RESET_ENA0_MASK 0x01L +#define GRA01__GRPH_SET_RESET_ENA1_MASK 0x02L +#define GRA01__GRPH_SET_RESET_ENA2_MASK 0x04L +#define GRA01__GRPH_SET_RESET_ENA3_MASK 0x08L +//GRA02 +#define GRA02__GRPH_CCOMP__SHIFT 0x0 +#define GRA02__GRPH_CCOMP_MASK 0x0FL +//GRA03 +#define GRA03__GRPH_ROTATE__SHIFT 0x0 +#define GRA03__GRPH_FN_SEL__SHIFT 0x3 +#define GRA03__GRPH_ROTATE_MASK 0x07L +#define GRA03__GRPH_FN_SEL_MASK 0x18L +//GRA04 +#define GRA04__GRPH_RMAP__SHIFT 0x0 +#define GRA04__GRPH_RMAP_MASK 0x03L +//GRA05 +#define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 +#define GRA05__GRPH_READ1__SHIFT 0x3 +#define GRA05__CGA_ODDEVEN__SHIFT 0x4 +#define GRA05__GRPH_OES__SHIFT 0x5 +#define GRA05__GRPH_PACK__SHIFT 0x6 +#define GRA05__GRPH_WRITE_MODE_MASK 0x03L +#define GRA05__GRPH_READ1_MASK 0x08L +#define GRA05__CGA_ODDEVEN_MASK 0x10L +#define GRA05__GRPH_OES_MASK 0x20L +#define GRA05__GRPH_PACK_MASK 0x40L +//GRA06 +#define GRA06__GRPH_GRAPHICS__SHIFT 0x0 +#define GRA06__GRPH_ODDEVEN__SHIFT 0x1 +#define GRA06__GRPH_ADRSEL__SHIFT 0x2 +#define GRA06__GRPH_GRAPHICS_MASK 0x01L +#define GRA06__GRPH_ODDEVEN_MASK 0x02L +#define GRA06__GRPH_ADRSEL_MASK 0x0CL +//GRA07 +#define GRA07__GRPH_XCARE0__SHIFT 0x0 +#define GRA07__GRPH_XCARE1__SHIFT 0x1 +#define GRA07__GRPH_XCARE2__SHIFT 0x2 +#define GRA07__GRPH_XCARE3__SHIFT 0x3 +#define GRA07__GRPH_XCARE0_MASK 0x01L +#define GRA07__GRPH_XCARE1_MASK 0x02L +#define GRA07__GRPH_XCARE2_MASK 0x04L +#define GRA07__GRPH_XCARE3_MASK 0x08L +//GRA08 +#define GRA08__GRPH_BMSK__SHIFT 0x0 +#define GRA08__GRPH_BMSK_MASK 0xFFL + + +// addressBlock: vga_vgaattrind +//ATTR00 +#define ATTR00__ATTR_PAL__SHIFT 0x0 +#define ATTR00__ATTR_PAL_MASK 0x3FL +//ATTR01 +#define ATTR01__ATTR_PAL__SHIFT 0x0 +#define ATTR01__ATTR_PAL_MASK 0x3FL +//ATTR02 +#define ATTR02__ATTR_PAL__SHIFT 0x0 +#define ATTR02__ATTR_PAL_MASK 0x3FL +//ATTR03 +#define ATTR03__ATTR_PAL__SHIFT 0x0 +#define ATTR03__ATTR_PAL_MASK 0x3FL +//ATTR04 +#define ATTR04__ATTR_PAL__SHIFT 0x0 +#define ATTR04__ATTR_PAL_MASK 0x3FL +//ATTR05 +#define ATTR05__ATTR_PAL__SHIFT 0x0 +#define ATTR05__ATTR_PAL_MASK 0x3FL +//ATTR06 +#define ATTR06__ATTR_PAL__SHIFT 0x0 +#define ATTR06__ATTR_PAL_MASK 0x3FL +//ATTR07 +#define ATTR07__ATTR_PAL__SHIFT 0x0 +#define ATTR07__ATTR_PAL_MASK 0x3FL +//ATTR08 +#define ATTR08__ATTR_PAL__SHIFT 0x0 +#define ATTR08__ATTR_PAL_MASK 0x3FL +//ATTR09 +#define ATTR09__ATTR_PAL__SHIFT 0x0 +#define ATTR09__ATTR_PAL_MASK 0x3FL +//ATTR0A +#define ATTR0A__ATTR_PAL__SHIFT 0x0 +#define ATTR0A__ATTR_PAL_MASK 0x3FL +//ATTR0B +#define ATTR0B__ATTR_PAL__SHIFT 0x0 +#define ATTR0B__ATTR_PAL_MASK 0x3FL +//ATTR0C +#define ATTR0C__ATTR_PAL__SHIFT 0x0 +#define ATTR0C__ATTR_PAL_MASK 0x3FL +//ATTR0D +#define ATTR0D__ATTR_PAL__SHIFT 0x0 +#define ATTR0D__ATTR_PAL_MASK 0x3FL +//ATTR0E +#define ATTR0E__ATTR_PAL__SHIFT 0x0 +#define ATTR0E__ATTR_PAL_MASK 0x3FL +//ATTR0F +#define ATTR0F__ATTR_PAL__SHIFT 0x0 +#define ATTR0F__ATTR_PAL_MASK 0x3FL +//ATTR10 +#define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 +#define ATTR10__ATTR_MONO_EN__SHIFT 0x1 +#define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 +#define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 +#define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 +#define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 +#define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 +#define ATTR10__ATTR_GRPH_MODE_MASK 0x01L +#define ATTR10__ATTR_MONO_EN_MASK 0x02L +#define ATTR10__ATTR_LGRPH_EN_MASK 0x04L +#define ATTR10__ATTR_BLINK_EN_MASK 0x08L +#define ATTR10__ATTR_PANTOPONLY_MASK 0x20L +#define ATTR10__ATTR_PCLKBY2_MASK 0x40L +#define ATTR10__ATTR_CSEL_EN_MASK 0x80L +//ATTR11 +#define ATTR11__ATTR_OVSC__SHIFT 0x0 +#define ATTR11__ATTR_OVSC_MASK 0xFFL +//ATTR12 +#define ATTR12__ATTR_MAP_EN__SHIFT 0x0 +#define ATTR12__ATTR_VSMUX__SHIFT 0x4 +#define ATTR12__ATTR_MAP_EN_MASK 0x0FL +#define ATTR12__ATTR_VSMUX_MASK 0x30L +//ATTR13 +#define ATTR13__ATTR_PPAN__SHIFT 0x0 +#define ATTR13__ATTR_PPAN_MASK 0x0FL +//ATTR14 +#define ATTR14__ATTR_CSEL1__SHIFT 0x0 +#define ATTR14__ATTR_CSEL2__SHIFT 0x2 +#define ATTR14__ATTR_CSEL1_MASK 0x03L +#define ATTR14__ATTR_CSEL2_MASK 0x0CL + + +// addressBlock: azendpoint_f2codecind +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL +//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L +//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_descriptorind +//AUDIO_DESCRIPTOR0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR1 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR2 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR3 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR4 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR5 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR6 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR8 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR9 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR10 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR11 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR12 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR13 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L + + +// addressBlock: azendpoint_sinkinfoind +//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL +//SINK_DESCRIPTION0 +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION1 +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION2 +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION3 +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION4 +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION5 +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION6 +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION7 +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION8 +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION9 +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION10 +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION11 +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION12 +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION13 +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION14 +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION15 +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION16 +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION17 +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL + + +// addressBlock: azf0controller_azinputcrc0resultind +//AZALIA_INPUT_CRC0_CHANNEL0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL1 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL2 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL3 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL4 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL5 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL6 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL7 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azinputcrc1resultind +//AZALIA_INPUT_CRC1_CHANNEL0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL1 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL2 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL3 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL4 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL5 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL6 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL7 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc0resultind +//AZALIA_CRC0_CHANNEL0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL1 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL2 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL3 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL4 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL5 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL6 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL7 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc1resultind +//AZALIA_CRC1_CHANNEL0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL1 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL2 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL3 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL4 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL5 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL6 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL7 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azinputendpoint_f2codecind +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L + + +// addressBlock: azroot_f2codecind +//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L + + +// addressBlock: azf0stream0_streamind +//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream1_streamind +//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream2_streamind +//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream3_streamind +//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream4_streamind +//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream5_streamind +//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream6_streamind +//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream7_streamind +//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream8_streamind +//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream9_streamind +//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream10_streamind +//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream11_streamind +//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream12_streamind +//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream13_streamind +//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream14_streamind +//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream15_streamind +//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: azf0endpoint0_endpointind +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint1_endpointind +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint2_endpointind +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint3_endpointind +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint4_endpointind +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint5_endpointind +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint6_endpointind +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0endpoint7_endpointind +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x00000070L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L + + +// addressBlock: azf0inputendpoint0_inputendpointind +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint1_inputendpointind +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint2_inputendpointind +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint3_inputendpointind +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint4_inputendpointind +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint5_inputendpointind +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint6_inputendpointind +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint7_inputendpointind +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h new file mode 100644 index 000000000000..945bb6101a9d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h @@ -0,0 +1,565 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dpcs_2_1_0_OFFSET_HEADER +#define _dpcs_2_1_0_OFFSET_HEADER + + + +// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec +// base address: 0x0 +#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928 +#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929 +#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a +#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b +#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d +#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e +#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec +// base address: 0x0 +#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930 +#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931 +#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932 +#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933 +#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934 +#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935 +#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936 +#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2937 +#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_SPARE 0x2938 +#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_CNTL2 0x2939 +#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d +#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952 +#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953 +#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2955 +#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG 0x2956 +#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15 0x2958 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16 0x2959 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17 0x295a +#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2 0x295b +#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr0_dispdec +// base address: 0x0 +#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934 +#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935 +#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec +// base address: 0x360 +#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x2a00 +#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_TX_CNTL 0x2a01 +#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x2a02 +#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL 0x2a03 +#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x2a04 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x2a05 +#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x2a06 +#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec +// base address: 0x360 +#define mmRDPCSTX1_RDPCSTX_CNTL 0x2a08 +#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL 0x2a09 +#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL 0x2a0a +#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA 0x2a0b +#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmRDPCSTX1_RDPCS_TX_CR_ADDR 0x2a0c +#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define mmRDPCSTX1_RDPCS_TX_CR_DATA 0x2a0d +#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL 0x2a0e +#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_SCRATCH 0x2a0f +#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_SPARE 0x2a10 +#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_CNTL2 0x2a11 +#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2a14 +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG 0x2a15 +#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0 0x2a18 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1 0x2a19 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2 0x2a1a +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3 0x2a1b +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4 0x2a1c +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5 0x2a1d +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6 0x2a1e +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7 0x2a1f +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8 0x2a20 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9 0x2a21 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10 0x2a22 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11 0x2a23 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12 0x2a24 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13 0x2a25 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14 0x2a26 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0 0x2a27 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1 0x2a28 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2 0x2a29 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3 0x2a2a +#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL 0x2a2b +#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2a2c +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2a2d +#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG 0x2a2e +#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15 0x2a30 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16 0x2a31 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17 0x2a32 +#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2 0x2a33 +#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr1_dispdec +// base address: 0x360 +#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c +#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d +#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec +// base address: 0x6c0 +#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x2ad8 +#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 +#define mmDPCSTX2_DPCSTX_TX_CNTL 0x2ad9 +#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX 2 +#define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x2ada +#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX 2 +#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL 0x2adb +#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x2adc +#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 +#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x2add +#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x2ade +#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec +// base address: 0x6c0 +#define mmRDPCSTX2_RDPCSTX_CNTL 0x2ae0 +#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL 0x2ae1 +#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL 0x2ae2 +#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA 0x2ae3 +#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmRDPCSTX2_RDPCS_TX_CR_ADDR 0x2ae4 +#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define mmRDPCSTX2_RDPCS_TX_CR_DATA 0x2ae5 +#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL 0x2ae6 +#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_SCRATCH 0x2ae7 +#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_SPARE 0x2ae8 +#define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_CNTL2 0x2ae9 +#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2aec +#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG 0x2aed +#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0 0x2af0 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1 0x2af1 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2 0x2af2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3 0x2af3 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4 0x2af4 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5 0x2af5 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6 0x2af6 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7 0x2af7 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8 0x2af8 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9 0x2af9 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10 0x2afa +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11 0x2afb +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12 0x2afc +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13 0x2afd +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14 0x2afe +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0 0x2aff +#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1 0x2b00 +#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2 0x2b01 +#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3 0x2b02 +#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL 0x2b03 +#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2b04 +#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2b05 +#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG 0x2b06 +#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15 0x2b08 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16 0x2b09 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17 0x2b0a +#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2 0x2b0b +#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr2_dispdec +// base address: 0x6c0 +#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4 +#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5 +#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec +// base address: 0xa20 +#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x2bb0 +#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 +#define mmDPCSTX3_DPCSTX_TX_CNTL 0x2bb1 +#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX 2 +#define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x2bb2 +#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX 2 +#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL 0x2bb3 +#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x2bb4 +#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 +#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x2bb5 +#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x2bb6 +#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec +// base address: 0xa20 +#define mmRDPCSTX3_RDPCSTX_CNTL 0x2bb8 +#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL 0x2bb9 +#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL 0x2bba +#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA 0x2bbb +#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmRDPCSTX3_RDPCS_TX_CR_ADDR 0x2bbc +#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define mmRDPCSTX3_RDPCS_TX_CR_DATA 0x2bbd +#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL 0x2bbe +#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_SCRATCH 0x2bbf +#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_SPARE 0x2bc0 +#define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_CNTL2 0x2bc1 +#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2bc4 +#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG 0x2bc5 +#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0 0x2bc8 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1 0x2bc9 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2 0x2bca +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3 0x2bcb +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4 0x2bcc +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5 0x2bcd +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6 0x2bce +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7 0x2bcf +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8 0x2bd0 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9 0x2bd1 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10 0x2bd2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11 0x2bd3 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12 0x2bd4 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13 0x2bd5 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14 0x2bd6 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0 0x2bd7 +#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1 0x2bd8 +#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2 0x2bd9 +#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3 0x2bda +#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL 0x2bdb +#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2bdc +#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2bdd +#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG 0x2bde +#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15 0x2be0 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16 0x2be1 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17 0x2be2 +#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2 0x2be3 +#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr3_dispdec +// base address: 0xa20 +#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc +#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd +#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec +// base address: 0xd80 +#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x2c88 +#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2 +#define mmDPCSTX4_DPCSTX_TX_CNTL 0x2c89 +#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX 2 +#define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x2c8a +#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX 2 +#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL 0x2c8b +#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2 +#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x2c8c +#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2 +#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x2c8d +#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x2c8e +#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec +// base address: 0xd80 +#define mmRDPCSTX4_RDPCSTX_CNTL 0x2c90 +#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL 0x2c91 +#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL 0x2c92 +#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA 0x2c93 +#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2 +#define mmRDPCSTX4_RDPCS_TX_CR_ADDR 0x2c94 +#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX 2 +#define mmRDPCSTX4_RDPCS_TX_CR_DATA 0x2c95 +#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX 2 +#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL 0x2c96 +#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_SCRATCH 0x2c97 +#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_SPARE 0x2c98 +#define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_CNTL2 0x2c99 +#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x2c9c +#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG 0x2c9d +#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0 0x2ca0 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1 0x2ca1 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2 0x2ca2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3 0x2ca3 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4 0x2ca4 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5 0x2ca5 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6 0x2ca6 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7 0x2ca7 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8 0x2ca8 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9 0x2ca9 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10 0x2caa +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11 0x2cab +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12 0x2cac +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13 0x2cad +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14 0x2cae +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0 0x2caf +#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1 0x2cb0 +#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2 0x2cb1 +#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3 0x2cb2 +#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL 0x2cb3 +#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2cb4 +#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 0x2cb5 +#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG 0x2cb6 +#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15 0x2cb8 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16 0x2cb9 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17 0x2cba +#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX 2 +#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2 0x2cbb +#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX 2 + + +// addressBlock: dpcssys_dpcssys_cr4_dispdec +// base address: 0xd80 +#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94 +#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2 +#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95 +#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h new file mode 100644 index 000000000000..6e039f2208e1 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h @@ -0,0 +1,3430 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _dpcs_2_1_0_SH_MASK_HEADER +#define _dpcs_2_1_0_SH_MASK_HEADER + + +// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec +//DPCSTX0_DPCSTX_TX_CLOCK_CNTL +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3 +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L +#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L +//DPCSTX0_DPCSTX_TX_CNTL +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT 0xf +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10 +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11 +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x00004000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK 0x00008000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L +#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L +//DPCSTX0_DPCSTX_CBUS_CNTL +#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0 +#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f +#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL +#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L +//DPCSTX0_DPCSTX_INTERRUPT_CNTL +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14 +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L +#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L +//DPCSTX0_DPCSTX_PLL_UPDATE_ADDR +#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0 +#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL +//DPCSTX0_DPCSTX_PLL_UPDATE_DATA +#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL +//DPCSTX0_DPCSTX_DEBUG_CONFIG +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT 0x0 +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT 0x1 +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT 0x4 +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT 0x8 +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT 0x10 +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT 0x18 +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK 0x00000001L +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK 0x0000000EL +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK 0x00000070L +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK 0x00000700L +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x00004000L +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK 0x00010000L +#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK 0xFF000000L + + + +// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec +//RDPCSTX0_RDPCSTX_CNTL +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_CLOCK_CNTL +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA +#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX0_RDPCS_TX_CR_ADDR +#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX0_RDPCS_TX_CR_DATA +#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX0_RDPCS_TX_SRAM_CNTL +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX0_RDPCSTX_SCRATCH +#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX0_RDPCSTX_SPARE +#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX0_RDPCSTX_CNTL2 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX0_RDPCSTX_DEBUG_CONFIG +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK 0x00000070L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK 0x00001F00L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK 0x00FF0000L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK 0xFF000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX0_RDPCSTX_PHY_CNTL2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX0_RDPCSTX_PHY_CNTL3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL5 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_PHY_CNTL7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX0_RDPCSTX_PHY_CNTL8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX0_RDPCSTX_PHY_CNTL9 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX0_RDPCSTX_PHY_CNTL11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX0_RDPCSTX_PHY_CNTL13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX0_RDPCSTX_PHY_FUSE0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX0_RDPCSTX_PHY_FUSE1 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX0_RDPCSTX_PHY_FUSE2 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX0_RDPCSTX_PHY_FUSE3 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX0_RDPCSTX_PHY_CNTL15 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX0_RDPCSTX_PHY_CNTL16 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX0_RDPCSTX_PHY_CNTL17 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX0_RDPCSTX_DEBUG_CONFIG2 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT 0x0 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT 0x4 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT 0x8 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT 0xc +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT 0x10 +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK 0x00000007L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK 0x00000070L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK 0x00000700L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK 0x00007000L +#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK 0x00010000L + + +// addressBlock: dpcssys_dpcssys_cr0_dispdec +//DPCSSYS_CR0_DPCSSYS_CR_ADDR +#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR0_DPCSSYS_CR_DATA +#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec +//DPCSTX1_DPCSTX_TX_CLOCK_CNTL +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3 +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L +#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L +//DPCSTX1_DPCSTX_TX_CNTL +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT 0xf +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10 +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11 +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x00004000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK 0x00008000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L +#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L +//DPCSTX1_DPCSTX_CBUS_CNTL +#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0 +#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f +#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL +#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L +//DPCSTX1_DPCSTX_INTERRUPT_CNTL +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14 +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L +#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L +//DPCSTX1_DPCSTX_PLL_UPDATE_ADDR +#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0 +#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL +//DPCSTX1_DPCSTX_PLL_UPDATE_DATA +#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL +//DPCSTX1_DPCSTX_DEBUG_CONFIG +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT 0x0 +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT 0x1 +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT 0x4 +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT 0x8 +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT 0x10 +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT 0x18 +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK 0x00000001L +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK 0x0000000EL +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK 0x00000070L +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK 0x00000700L +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x00004000L +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK 0x00010000L +#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK 0xFF000000L + + +// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec +//RDPCSTX1_RDPCSTX_CNTL +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_CLOCK_CNTL +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA +#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX1_RDPCS_TX_CR_ADDR +#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX1_RDPCS_TX_CR_DATA +#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX1_RDPCS_TX_SRAM_CNTL +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX1_RDPCSTX_SCRATCH +#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX1_RDPCSTX_SPARE +#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX1_RDPCSTX_CNTL2 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX1_RDPCSTX_DEBUG_CONFIG +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK 0x00000070L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK 0x00001F00L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK 0x00FF0000L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK 0xFF000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX1_RDPCSTX_PHY_CNTL2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX1_RDPCSTX_PHY_CNTL3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL5 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_PHY_CNTL7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX1_RDPCSTX_PHY_CNTL8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX1_RDPCSTX_PHY_CNTL9 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX1_RDPCSTX_PHY_CNTL11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX1_RDPCSTX_PHY_CNTL13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX1_RDPCSTX_PHY_FUSE0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX1_RDPCSTX_PHY_FUSE1 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX1_RDPCSTX_PHY_FUSE2 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX1_RDPCSTX_PHY_FUSE3 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX1_RDPCSTX_PHY_CNTL15 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX1_RDPCSTX_PHY_CNTL16 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX1_RDPCSTX_PHY_CNTL17 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX1_RDPCSTX_DEBUG_CONFIG2 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT 0x0 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT 0x4 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT 0x8 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT 0xc +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT 0x10 +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK 0x00000007L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK 0x00000070L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK 0x00000700L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK 0x00007000L +#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK 0x00010000L + + +// addressBlock: dpcssys_dpcssys_cr1_dispdec +//DPCSSYS_CR1_DPCSSYS_CR_ADDR +#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR1_DPCSSYS_CR_DATA +#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec +//DPCSTX2_DPCSTX_TX_CLOCK_CNTL +#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 +#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 +#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 +#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3 +#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L +#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L +#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L +#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L +//DPCSTX2_DPCSTX_TX_CNTL +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT 0xf +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10 +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11 +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x00004000L +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK 0x00008000L +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L +#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L +//DPCSTX2_DPCSTX_CBUS_CNTL +#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0 +#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f +#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL +#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L +//DPCSTX2_DPCSTX_INTERRUPT_CNTL +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1 +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4 +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8 +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9 +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10 +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14 +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L +#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L +//DPCSTX2_DPCSTX_PLL_UPDATE_ADDR +#define DPCSTX2_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0 +#define DPCSTX2_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL +//DPCSTX2_DPCSTX_PLL_UPDATE_DATA +#define DPCSTX2_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define DPCSTX2_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL +//DPCSTX2_DPCSTX_DEBUG_CONFIG +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT 0x0 +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT 0x1 +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT 0x4 +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT 0x8 +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT 0x10 +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT 0x18 +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK 0x00000001L +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK 0x0000000EL +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK 0x00000070L +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK 0x00000700L +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x00004000L +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK 0x00010000L +#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK 0xFF000000L + + +// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec +//RDPCSTX2_RDPCSTX_CNTL +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1a +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x04000000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX2_RDPCSTX_CLOCK_CNTL +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA +#define RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX2_RDPCS_TX_CR_ADDR +#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX2_RDPCS_TX_CR_DATA +#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX2_RDPCS_TX_SRAM_CNTL +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX2_RDPCSTX_SCRATCH +#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX2_RDPCSTX_SPARE +#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX2_RDPCSTX_CNTL2 +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +//RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX2_RDPCSTX_DEBUG_CONFIG +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT 0xf +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK 0x00000070L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK 0x00001F00L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK 0x00008000L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK 0x00FF0000L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK 0xFF000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX2_RDPCSTX_PHY_CNTL2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX2_RDPCSTX_PHY_CNTL3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL5 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX2_RDPCSTX_PHY_CNTL7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX2_RDPCSTX_PHY_CNTL8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX2_RDPCSTX_PHY_CNTL9 +#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX2_RDPCSTX_PHY_CNTL11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX2_RDPCSTX_PHY_CNTL13 +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX2_RDPCSTX_PHY_FUSE0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX2_RDPCSTX_PHY_FUSE1 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX2_RDPCSTX_PHY_FUSE2 +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX2_RDPCSTX_PHY_FUSE3 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX2_RDPCSTX_PHY_CNTL15 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX2_RDPCSTX_PHY_CNTL16 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX2_RDPCSTX_PHY_CNTL17 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX2_RDPCSTX_DEBUG_CONFIG2 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT 0x0 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT 0x4 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT 0x8 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT 0xc +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT 0x10 +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK 0x00000007L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK 0x00000070L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK 0x00000700L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK 0x00007000L +#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK 0x00010000L + + +// addressBlock: dpcssys_dpcssys_cr2_dispdec +//DPCSSYS_CR2_DPCSSYS_CR_ADDR +#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR2_DPCSSYS_CR_DATA +#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec +//DPCSTX3_DPCSTX_TX_CLOCK_CNTL +#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 +#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 +#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 +#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3 +#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L +#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L +#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L +#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L +//DPCSTX3_DPCSTX_TX_CNTL +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT 0xf +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10 +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11 +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x00004000L +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK 0x00008000L +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L +#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L +//DPCSTX3_DPCSTX_CBUS_CNTL +#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0 +#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f +#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL +#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L +//DPCSTX3_DPCSTX_INTERRUPT_CNTL +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1 +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4 +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8 +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9 +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10 +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14 +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L +#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L +//DPCSTX3_DPCSTX_PLL_UPDATE_ADDR +#define DPCSTX3_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0 +#define DPCSTX3_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL +//DPCSTX3_DPCSTX_PLL_UPDATE_DATA +#define DPCSTX3_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define DPCSTX3_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL +//DPCSTX3_DPCSTX_DEBUG_CONFIG +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT 0x0 +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT 0x1 +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT 0x4 +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT 0x8 +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT 0x10 +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT 0x18 +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK 0x00000001L +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK 0x0000000EL +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK 0x00000070L +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK 0x00000700L +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x00004000L +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK 0x00010000L +#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK 0xFF000000L + + +// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec +//RDPCSTX3_RDPCSTX_CNTL +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1a +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x04000000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX3_RDPCSTX_CLOCK_CNTL +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA +#define RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX3_RDPCS_TX_CR_ADDR +#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX3_RDPCS_TX_CR_DATA +#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX3_RDPCS_TX_SRAM_CNTL +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX3_RDPCSTX_SCRATCH +#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX3_RDPCSTX_SPARE +#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX3_RDPCSTX_CNTL2 +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +//RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX3_RDPCSTX_DEBUG_CONFIG +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT 0xf +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK 0x00000070L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK 0x00001F00L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK 0x00008000L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK 0x00FF0000L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK 0xFF000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX3_RDPCSTX_PHY_CNTL2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX3_RDPCSTX_PHY_CNTL3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL5 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX3_RDPCSTX_PHY_CNTL7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX3_RDPCSTX_PHY_CNTL8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX3_RDPCSTX_PHY_CNTL9 +#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX3_RDPCSTX_PHY_CNTL11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX3_RDPCSTX_PHY_CNTL13 +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX3_RDPCSTX_PHY_FUSE0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX3_RDPCSTX_PHY_FUSE1 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX3_RDPCSTX_PHY_FUSE2 +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX3_RDPCSTX_PHY_FUSE3 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX3_RDPCSTX_PHY_CNTL15 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX3_RDPCSTX_PHY_CNTL16 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX3_RDPCSTX_PHY_CNTL17 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX3_RDPCSTX_DEBUG_CONFIG2 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT 0x0 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT 0x4 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT 0x8 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT 0xc +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT 0x10 +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK 0x00000007L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK 0x00000070L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK 0x00000700L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK 0x00007000L +#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK 0x00010000L + + +// addressBlock: dpcssys_dpcssys_cr3_dispdec +//DPCSSYS_CR3_DPCSSYS_CR_ADDR +#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR3_DPCSSYS_CR_DATA +#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + + +// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec +//DPCSTX4_DPCSTX_TX_CLOCK_CNTL +#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 +#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 +#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 +#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3 +#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L +#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L +#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L +#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L +//DPCSTX4_DPCSTX_TX_CNTL +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT 0xe +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT 0xf +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT 0x10 +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT 0x11 +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT 0x1f +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK 0x00001000L +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK 0x00002000L +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK 0x00004000L +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK 0x00008000L +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK 0x00010000L +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK 0x00020000L +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK 0x00F00000L +#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK 0x80000000L +//DPCSTX4_DPCSTX_CBUS_CNTL +#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT 0x0 +#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT 0x1f +#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK 0x000000FFL +#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK 0x80000000L +//DPCSTX4_DPCSTX_INTERRUPT_CNTL +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT 0x1 +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT 0x4 +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT 0x8 +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT 0x9 +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT 0xb +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT 0xc +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT 0x10 +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT 0x14 +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK 0x00000002L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK 0x00000010L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK 0x00000100L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK 0x00000200L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK 0x00000400L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK 0x00000800L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK 0x00001000L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK 0x00010000L +#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK 0x00100000L +//DPCSTX4_DPCSTX_PLL_UPDATE_ADDR +#define DPCSTX4_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT 0x0 +#define DPCSTX4_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK 0x0003FFFFL +//DPCSTX4_DPCSTX_PLL_UPDATE_DATA +#define DPCSTX4_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define DPCSTX4_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK 0xFFFFFFFFL +//DPCSTX4_DPCSTX_DEBUG_CONFIG +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT 0x0 +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT 0x1 +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT 0x4 +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT 0x8 +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT 0xe +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT 0x10 +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT 0x18 +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK 0x00000001L +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK 0x0000000EL +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK 0x00000070L +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK 0x00000700L +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK 0x00004000L +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK 0x00010000L +#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK 0xFF000000L + + +// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec +//RDPCSTX4_RDPCSTX_CNTL +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT 0xf +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT 0x1a +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT 0x1f +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK 0x00002000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK 0x00008000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK 0x01F00000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK 0x04000000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK 0x20000000L +#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK 0x80000000L +//RDPCSTX4_RDPCSTX_CLOCK_CNTL +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT 0x15 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT 0x16 +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK 0x00002000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK 0x00200000L +#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK 0x00400000L +//RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK 0x00100000L +//RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA +#define RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK 0x00000001L +//RDPCSTX4_RDPCS_TX_CR_ADDR +#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//RDPCSTX4_RDPCS_TX_CR_DATA +#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL +//RDPCSTX4_RDPCS_TX_SRAM_CNTL +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT 0x14 +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT 0x18 +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT 0x1c +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK 0x00100000L +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK 0x03000000L +#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK 0x30000000L +//RDPCSTX4_RDPCSTX_SCRATCH +#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK 0xFFFFFFFFL +//RDPCSTX4_RDPCSTX_SPARE +#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK 0xFFFFFFFFL +//RDPCSTX4_RDPCSTX_CNTL2 +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK 0x00000002L +//RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX4_RDPCSTX_DEBUG_CONFIG +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT 0xf +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK 0x00000070L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK 0x00001F00L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK 0x00008000L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK 0x00FF0000L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK 0xFF000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT 0x15 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT 0x1f +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK 0x00000030L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK 0x00003E00L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK 0x00200000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK 0x02000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK 0x20000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK 0x80000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK 0x00000080L +//RDPCSTX4_RDPCSTX_PHY_CNTL2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT 0xb +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK 0x00000800L +//RDPCSTX4_RDPCSTX_PHY_CNTL3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT 0xb +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT 0x15 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT 0x1a +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT 0x1b +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK 0x00000800L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK 0x00002000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK 0x00200000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK 0x02000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK 0x04000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK 0x08000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK 0x20000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT 0xf +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT 0x16 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT 0x17 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT 0x1e +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT 0x1f +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK 0x00000007L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK 0x00000700L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK 0x00008000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK 0x00070000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK 0x00400000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK 0x00800000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK 0x07000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK 0x40000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK 0x80000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL5 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT 0xf +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT 0x16 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT 0x17 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT 0x1e +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT 0x1f +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK 0x0000000EL +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK 0x00000030L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK 0x00000E00L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK 0x00003000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK 0x00008000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK 0x000E0000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK 0x00300000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK 0x00400000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK 0x00800000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK 0x0E000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK 0x30000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK 0x40000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK 0x80000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK 0x00000003L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK 0x00000030L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK 0x00000300L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK 0x00003000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK 0x00100000L +//RDPCSTX4_RDPCSTX_PHY_CNTL7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK 0x0000FFFFL +#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK 0xFFFF0000L +//RDPCSTX4_RDPCSTX_PHY_CNTL8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK 0x000FFFFFL +//RDPCSTX4_RDPCSTX_PHY_CNTL9 +#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK 0x001FFFFFL +#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK 0x01000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK 0x0000FFFFL +//RDPCSTX4_RDPCSTX_PHY_CNTL11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK 0x0000FFF0L +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK 0x00070000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK 0x00700000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK 0x03000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT 0x7 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK 0x00000070L +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK 0x00000080L +#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK 0x00000100L +//RDPCSTX4_RDPCSTX_PHY_CNTL13 +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT 0x1e +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK 0x0FF00000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK 0x20000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK 0x40000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK 0x10000000L +//RDPCSTX4_RDPCSTX_PHY_FUSE0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT 0x16 +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK 0x0003F000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK 0x000C0000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK 0x00300000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK 0x1FC00000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK 0xE0000000L +//RDPCSTX4_RDPCSTX_PHY_FUSE1 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK 0x0003F000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK 0x01FC0000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK 0xFE000000L +//RDPCSTX4_RDPCSTX_PHY_FUSE2 +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT 0x17 +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK 0x0003F000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK 0x3F800000L +//RDPCSTX4_RDPCSTX_PHY_FUSE3 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT 0x1a +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK 0x0000003FL +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK 0x00000FC0L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK 0x0003F000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK 0x00FC0000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK 0x03000000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK 0x1C000000L +#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK 0xE0000000L +//RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK 0x0000007FL +#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK 0x001FFF00L +//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT 0x1 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT 0x3 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT 0x5 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT 0x9 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT 0xb +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT 0x15 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT 0x19 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT 0x1a +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT 0x1b +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT 0x1c +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT 0x1d +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK 0x00000002L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK 0x00000008L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK 0x00000020L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK 0x00000100L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK 0x00000200L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK 0x00000800L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK 0x00001000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK 0x00002000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK 0x00100000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK 0x00200000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK 0x01000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK 0x02000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK 0x04000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK 0x08000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK 0x10000000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK 0x20000000L +//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT 0x2 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT 0xe +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK 0x00000003L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK 0x00000004L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK 0x00000030L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK 0x00000040L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK 0x00000300L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK 0x00000400L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK 0x00003000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK 0x00004000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK 0x00100000L +//RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK 0x00000010L +#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK 0x0000FF00L +//RDPCSTX4_RDPCSTX_PHY_CNTL15 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT 0x11 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT 0x13 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT 0x14 +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK 0x00000001L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK 0x00010000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK 0x00020000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK 0x00040000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK 0x00080000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK 0x00100000L +//RDPCSTX4_RDPCSTX_PHY_CNTL16 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX4_RDPCSTX_PHY_CNTL17 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT 0x6 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT 0x12 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT 0x18 +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK 0x0000001FL +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK 0x000007C0L +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK 0x0001F000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK 0x007C0000L +#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK 0x1F000000L +//RDPCSTX4_RDPCSTX_DEBUG_CONFIG2 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT 0x0 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT 0x4 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT 0x8 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT 0xc +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT 0x10 +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK 0x00000007L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK 0x00000070L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK 0x00000700L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK 0x00007000L +#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK 0x00010000L + + +// addressBlock: dpcssys_dpcssys_cr4_dispdec +//DPCSSYS_CR4_DPCSSYS_CR_ADDR +#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 +#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL +//DPCSSYS_CR4_DPCSSYS_CR_DATA +#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 +#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h index 6efcaa93e17b..c2bd25589e84 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h @@ -48,4 +48,8 @@ #define smnPerfMonCtrLo3 0x01d478UL #define smnPerfMonCtrHi3 0x01d47cUL +#define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3 0x1d05cUL +#define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3 0x1d098UL +#define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3 0x1d09cUL + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h index 1dbc7cefbc05..075867d4b1da 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h @@ -10107,6 +10107,8 @@ #define mmCGTT_IA_CLK_CTRL_BASE_IDX 1 #define mmCGTT_WD_CLK_CTRL 0x5086 #define mmCGTT_WD_CLK_CTRL_BASE_IDX 1 +#define mmCGTT_GS_NGG_CLK_CTRL 0x5087 +#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 #define mmCGTT_PA_CLK_CTRL 0x5088 #define mmCGTT_PA_CLK_CTRL_BASE_IDX 1 #define mmCGTT_SC_CLK_CTRL0 0x5089 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h index 6c2a421fe8b7..e7db6f9f9c86 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h @@ -37872,6 +37872,45 @@ #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_GS_NGG_CLK_CTRL +#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b +#define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE__SHIFT 0x1c +#define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE__SHIFT 0x1d +#define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L +#define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE_MASK 0x10000000L +#define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE_MASK 0x20000000L +#define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L +#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L //CGTT_PA_CLK_CTRL #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index f1d048e0ed2c..ca16d9125fbc 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -1700,6 +1700,8 @@ #define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX 0 #define mmTCP_EDC_CNT 0x0b17 #define mmTCP_EDC_CNT_BASE_IDX 0 +#define mmTCP_EDC_CNT_NEW 0x0b18 +#define mmTCP_EDC_CNT_NEW_BASE_IDX 0 #define mmTC_CFG_L1_LOAD_POLICY0 0x0b1a #define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX 0 #define mmTC_CFG_L1_LOAD_POLICY1 0x0b1b diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h index 2e1214be67a2..064c4bb1dc62 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h @@ -21,6 +21,105 @@ #ifndef _gc_9_0_SH_MASK_HEADER #define _gc_9_0_SH_MASK_HEADER +//GCEA_EDC_CNT +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L + +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L + +// addressBlock: gc_cppdec2 +//CPF_EDC_TAG_CNT +#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 +#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 +#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L +#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL +//CPF_EDC_ROQ_CNT +#define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT 0x0 +#define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT 0x2 +#define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK 0x00000003L +#define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK 0x0000000CL +//CPG_EDC_TAG_CNT +#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 +#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 +#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L +#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL +//CPG_EDC_DMA_CNT +#define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT 0x0 +#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x2 +#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x4 +#define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK 0x00000003L +#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x0000000CL +#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x00000030L +//CPC_EDC_SCRATCH_CNT +#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0 +#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2 +#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L +#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL +//CPC_EDC_UCODE_CNT +#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0 +#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2 +#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L +#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL +//DC_EDC_STATE_CNT +#define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT 0x0 +#define DC_EDC_STATE_CNT__COUNT_ME1_MASK 0x00000003L +//DC_EDC_CSINVOC_CNT +#define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT 0x0 +#define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK 0x00000003L +//DC_EDC_RESTORE_CNT +#define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT 0x0 +#define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK 0x00000003L // addressBlock: gc_grbmdec //GRBM_CNTL @@ -9033,11 +9132,15 @@ #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4 #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8 +#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT__SHIFT 0xa +#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT__SHIFT 0xc #define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L #define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L +#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT_MASK 0x00000C00L +#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT_MASK 0x00003000L //TCC_REDUNDANCY #define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 #define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 @@ -29818,6 +29921,60 @@ #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL +//TA_EDC_CNT +#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0 +#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2 +#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT__SHIFT 0x4 +#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT__SHIFT 0x6 +#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT__SHIFT 0x8 +#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT__SHIFT 0xa +#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L +#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL +#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT_MASK 0x00000030L +#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT_MASK 0x000000C0L +#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT_MASK 0x00000300L +#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT_MASK 0x00000C00L + +//TCI_EDC_CNT +#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT__SHIFT 0x0 +#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT_MASK 0x00000003L + +//TCP_EDC_CNT_NEW +#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT 0x0 +#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT 0x2 +#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT 0x4 +#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT 0x6 +#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT__SHIFT 0x8 +#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT 0xa +#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT 0xc +#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT 0xe +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT 0x10 +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x12 +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT 0x14 +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT 0x16 +#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK 0x00000003L +#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK 0x0000000CL +#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK 0x00000030L +#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK 0x000000C0L +#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT_MASK 0x00000300L +#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK 0x00000C00L +#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK 0x00003000L +#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK 0x0000C000L +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK 0x00030000L +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK 0x000C0000L +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK 0x00300000L +#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK 0x00C00000L +//TD_EDC_CNT +#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT 0x0 +#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT 0x2 +#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT 0x4 +#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT 0x6 +#define TD_EDC_CNT__CS_FIFO_SED_COUNT__SHIFT 0x8 +#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK 0x00000003L +#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK 0x0000000CL +#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK 0x00000030L +#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK 0x000000C0L +#define TD_EDC_CNT__CS_FIFO_SED_COUNT_MASK 0x00000300L #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h index 8f515875a34d..f2ae3a58949e 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h @@ -21,6 +21,27 @@ #ifndef _mmhub_9_4_0_OFFSET_HEADER #define _mmhub_9_4_0_OFFSET_HEADER +/* MMEA */ +#define mmMMEA0_SDP_ARB_FINAL_VG20 0x01ee +#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX 0 +#define mmMMEA0_EDC_CNT_VG20 0x0206 +#define mmMMEA0_EDC_CNT_VG20_BASE_IDX 0 +#define mmMMEA0_EDC_CNT2_VG20 0x0207 +#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX 0 +#define mmMMEA0_EDC_MODE_VG20 0x0210 +#define mmMMEA0_EDC_MODE_VG20_BASE_IDX 0 +#define mmMMEA0_ERR_STATUS_VG20 0x0211 +#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX 0 +#define mmMMEA1_SDP_ARB_FINAL_VG20 0x032e +#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX 0 +#define mmMMEA1_EDC_CNT_VG20 0x0346 +#define mmMMEA1_EDC_CNT_VG20_BASE_IDX 0 +#define mmMMEA1_EDC_CNT2_VG20 0x0347 +#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX 0 +#define mmMMEA1_EDC_MODE_VG20 0x0350 +#define mmMMEA1_EDC_MODE_VG20_BASE_IDX 0 +#define mmMMEA1_ERR_STATUS_VG20 0x0351 +#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX 0 // addressBlock: mmhub_utcl2_vmsharedpfdec // base address: 0x6a040 diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h index 0a6b072d191e..c24259ed12a1 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h @@ -21,6 +21,228 @@ #ifndef _mmhub_9_4_0_SH_MASK_HEADER #define _mmhub_9_4_0_SH_MASK_HEADER +//MMEA0_SDP_ARB_FINAL +#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +//MMEA0_EDC_CNT +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA0_EDC_CNT2 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +//MMEA0_EDC_MODE +#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA0_ERR_STATUS +#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA1_SDP_ARB_FINAL +#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +//MMEA1_EDC_CNT +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA1_EDC_CNT2 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 +#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 +#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 +#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L +#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L +#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L +#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L +//MMEA1_EDC_MODE +#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA1_ERR_STATUS +#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L // addressBlock: mmhub_utcl2_vmsharedpfdec //MC_VM_XGMI_LFB_CNTL diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h new file mode 100644 index 000000000000..ec631c816d18 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h @@ -0,0 +1,3933 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mmhub_9_4_1_DEFAULT_HEADER +#define _mmhub_9_4_1_DEFAULT_HEADER + + +// addressBlock: mmhub_dagb_dagbdec0 +#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x60606070 +#define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB0_CNTL_MISC2_DEFAULT 0x003c0000 +#define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x1fffffff +#define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB0_RESERVE0_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE1_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE2_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE3_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE4_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE5_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE6_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE7_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE8_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE9_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE10_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE11_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE12_DEFAULT 0xffffffff +#define mmDAGB0_RESERVE13_DEFAULT 0xffffffff + + +// addressBlock: mmhub_dagb_dagbdec1 +#define mmDAGB1_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB1_RD_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB1_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB1_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB1_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_RD_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB1_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB1_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB1_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB1_WR_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB1_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB1_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB1_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB1_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB1_WR_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB1_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB1_WR_DATA_CREDIT_DEFAULT 0x60606070 +#define mmDAGB1_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB1_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB1_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB1_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB1_CNTL_MISC2_DEFAULT 0x003c0000 +#define mmDAGB1_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB1_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB1_WR_CREDITS_FULL_DEFAULT 0x1fffffff +#define mmDAGB1_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB1_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB1_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB1_RESERVE0_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE1_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE2_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE3_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE4_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE5_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE6_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE7_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE8_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE9_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE10_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE11_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE12_DEFAULT 0xffffffff +#define mmDAGB1_RESERVE13_DEFAULT 0xffffffff + + +// addressBlock: mmhub_dagb_dagbdec2 +#define mmDAGB2_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB2_RD_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB2_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB2_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB2_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_RD_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB2_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB2_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB2_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB2_WR_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB2_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB2_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB2_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB2_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB2_WR_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB2_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB2_WR_DATA_CREDIT_DEFAULT 0x60606070 +#define mmDAGB2_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB2_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB2_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB2_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB2_CNTL_MISC2_DEFAULT 0x003c0000 +#define mmDAGB2_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB2_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB2_WR_CREDITS_FULL_DEFAULT 0x1fffffff +#define mmDAGB2_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB2_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB2_RESERVE0_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE1_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE2_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE3_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE4_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE5_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE6_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE7_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE8_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE9_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE10_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE11_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE12_DEFAULT 0xffffffff +#define mmDAGB2_RESERVE13_DEFAULT 0xffffffff + + +// addressBlock: mmhub_dagb_dagbdec3 +#define mmDAGB3_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB3_RD_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB3_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB3_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB3_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_RD_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB3_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB3_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB3_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB3_WR_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB3_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB3_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB3_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB3_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB3_WR_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB3_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB3_WR_DATA_CREDIT_DEFAULT 0x60606070 +#define mmDAGB3_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB3_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB3_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB3_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB3_CNTL_MISC2_DEFAULT 0x003c0000 +#define mmDAGB3_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB3_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB3_WR_CREDITS_FULL_DEFAULT 0x1fffffff +#define mmDAGB3_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB3_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB3_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB3_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB3_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB3_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB3_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB3_RESERVE0_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE1_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE2_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE3_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE4_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE5_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE6_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE7_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE8_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE9_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE10_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE11_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE12_DEFAULT 0xffffffff +#define mmDAGB3_RESERVE13_DEFAULT 0xffffffff + + +// addressBlock: mmhub_dagb_dagbdec4 +#define mmDAGB4_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB4_RD_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB4_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB4_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB4_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_RD_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB4_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB4_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB4_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB4_WR_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB4_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB4_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB4_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB4_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB4_WR_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB4_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB4_WR_DATA_CREDIT_DEFAULT 0x60606070 +#define mmDAGB4_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB4_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB4_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB4_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB4_CNTL_MISC2_DEFAULT 0x003c0000 +#define mmDAGB4_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB4_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB4_WR_CREDITS_FULL_DEFAULT 0x1fffffff +#define mmDAGB4_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB4_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB4_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB4_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB4_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB4_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB4_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB4_RESERVE0_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE1_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE2_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE3_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE4_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE5_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE6_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE7_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE8_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE9_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE10_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE11_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE12_DEFAULT 0xffffffff +#define mmDAGB4_RESERVE13_DEFAULT 0xffffffff + + +// addressBlock: mmhub_ea_mmeadec0 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA0_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA0_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA0_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA0_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA0_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA0_GMI_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA0_GMI_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA0_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA0_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA0_GMI_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA0_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA0_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf +#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA0_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00101e40 +#define mmMMEA0_SDP_ARB_GMI_DEFAULT 0x00101e40 +#define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA0_SDP_GMI_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA0_SDP_CREDITS_DEFAULT 0x000101bf +#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define mmMMEA0_MISC_DEFAULT 0x0c00a070 +#define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA0_ERR_STATUS_DEFAULT 0x00000300 +#define mmMMEA0_MISC2_DEFAULT 0x00000000 +#define mmMMEA0_ADDRDEC_SELECT_DEFAULT 0x00000000 +#define mmMMEA0_EDC_CNT3_DEFAULT 0x00000000 + + +// addressBlock: mmhub_ea_mmeadec1 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA1_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA1_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA1_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA1_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA1_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA1_GMI_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA1_GMI_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA1_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA1_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA1_GMI_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA1_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA1_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf +#define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA1_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00101e40 +#define mmMMEA1_SDP_ARB_GMI_DEFAULT 0x00101e40 +#define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA1_SDP_GMI_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA1_SDP_CREDITS_DEFAULT 0x000101bf +#define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define mmMMEA1_MISC_DEFAULT 0x0c00a070 +#define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA1_ERR_STATUS_DEFAULT 0x00000300 +#define mmMMEA1_MISC2_DEFAULT 0x00000000 +#define mmMMEA1_ADDRDEC_SELECT_DEFAULT 0x00000000 +#define mmMMEA1_EDC_CNT3_DEFAULT 0x00000000 + + +// addressBlock: mmhub_ea_mmeadec2 +#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA2_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA2_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA2_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA2_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA2_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA2_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA2_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA2_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA2_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA2_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA2_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA2_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA2_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA2_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA2_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA2_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA2_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA2_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA2_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA2_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA2_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA2_GMI_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA2_GMI_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA2_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA2_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA2_GMI_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA2_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA2_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA2_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA2_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA2_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA2_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA2_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA2_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA2_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf +#define mmMMEA2_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA2_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA2_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA2_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA2_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA2_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA2_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA2_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA2_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA2_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA2_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA2_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA2_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA2_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA2_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA2_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA2_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA2_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA2_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA2_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA2_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA2_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA2_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA2_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA2_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA2_SDP_ARB_DRAM_DEFAULT 0x00101e40 +#define mmMMEA2_SDP_ARB_GMI_DEFAULT 0x00101e40 +#define mmMMEA2_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA2_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA2_SDP_GMI_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA2_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA2_SDP_CREDITS_DEFAULT 0x000101bf +#define mmMMEA2_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA2_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA2_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA2_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA2_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA2_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA2_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define mmMMEA2_MISC_DEFAULT 0x0c00a070 +#define mmMMEA2_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA2_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA2_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA2_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA2_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA2_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA2_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA2_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA2_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA2_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA2_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA2_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA2_ERR_STATUS_DEFAULT 0x00000300 +#define mmMMEA2_MISC2_DEFAULT 0x00000000 +#define mmMMEA2_ADDRDEC_SELECT_DEFAULT 0x00000000 +#define mmMMEA2_EDC_CNT3_DEFAULT 0x00000000 + + +// addressBlock: mmhub_ea_mmeadec3 +#define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA3_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA3_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA3_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA3_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA3_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA3_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA3_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA3_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA3_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA3_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA3_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA3_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA3_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA3_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA3_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA3_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA3_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA3_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA3_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA3_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA3_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA3_GMI_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA3_GMI_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA3_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA3_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA3_GMI_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA3_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA3_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA3_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA3_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA3_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA3_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA3_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA3_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA3_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf +#define mmMMEA3_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA3_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA3_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA3_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA3_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA3_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA3_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA3_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA3_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA3_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA3_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA3_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA3_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA3_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA3_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA3_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA3_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA3_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA3_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA3_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA3_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA3_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA3_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA3_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA3_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA3_SDP_ARB_DRAM_DEFAULT 0x00101e40 +#define mmMMEA3_SDP_ARB_GMI_DEFAULT 0x00101e40 +#define mmMMEA3_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA3_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA3_SDP_GMI_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA3_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA3_SDP_CREDITS_DEFAULT 0x000101bf +#define mmMMEA3_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA3_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA3_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA3_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA3_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA3_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA3_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define mmMMEA3_MISC_DEFAULT 0x0c00a070 +#define mmMMEA3_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA3_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA3_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA3_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA3_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA3_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA3_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA3_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA3_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA3_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA3_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA3_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA3_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA3_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA3_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA3_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA3_ERR_STATUS_DEFAULT 0x00000300 +#define mmMMEA3_MISC2_DEFAULT 0x00000000 +#define mmMMEA3_ADDRDEC_SELECT_DEFAULT 0x00000000 +#define mmMMEA3_EDC_CNT3_DEFAULT 0x00000000 + + +// addressBlock: mmhub_ea_mmeadec4 +#define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA4_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA4_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA4_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA4_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA4_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA4_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA4_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA4_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA4_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA4_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA4_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA4_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA4_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA4_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA4_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA4_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA4_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA4_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA4_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA4_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA4_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA4_GMI_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA4_GMI_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA4_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA4_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA4_GMI_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA4_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA4_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA4_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA4_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA4_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA4_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA4_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA4_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA4_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf +#define mmMMEA4_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA4_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA4_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA4_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA4_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA4_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA4_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA4_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA4_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA4_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA4_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA4_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA4_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA4_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA4_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA4_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA4_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA4_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA4_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA4_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA4_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA4_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA4_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA4_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA4_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA4_SDP_ARB_DRAM_DEFAULT 0x00101e40 +#define mmMMEA4_SDP_ARB_GMI_DEFAULT 0x00101e40 +#define mmMMEA4_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA4_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA4_SDP_GMI_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA4_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA4_SDP_CREDITS_DEFAULT 0x000101bf +#define mmMMEA4_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA4_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA4_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA4_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA4_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA4_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA4_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define mmMMEA4_MISC_DEFAULT 0x0c00a070 +#define mmMMEA4_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA4_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA4_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA4_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA4_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA4_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA4_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA4_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA4_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA4_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA4_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA4_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA4_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA4_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA4_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA4_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA4_ERR_STATUS_DEFAULT 0x00000300 +#define mmMMEA4_MISC2_DEFAULT 0x00000000 +#define mmMMEA4_ADDRDEC_SELECT_DEFAULT 0x00000000 +#define mmMMEA4_EDC_CNT3_DEFAULT 0x00000000 + + +// addressBlock: mmhub_pctldec0 +#define mmPCTL0_CTRL_DEFAULT 0x00011040 +#define mmPCTL0_MMHUB_DEEPSLEEP_IB_DEFAULT 0x00000000 +#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 +#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT 0x00000000 +#define mmPCTL0_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 +#define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_MISC_DEFAULT 0x00011000 +#define mmPCTL0_SLICE0_MISC_DEFAULT 0x00000800 +#define mmPCTL0_SLICE1_MISC_DEFAULT 0x00000800 +#define mmPCTL0_SLICE2_MISC_DEFAULT 0x00000800 +#define mmPCTL0_SLICE3_MISC_DEFAULT 0x00000800 +#define mmPCTL0_SLICE4_MISC_DEFAULT 0x00000800 +#define mmPCTL0_UTCL2_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff + + +// addressBlock: mmhub_l1tlb_vml1dec +#define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 +#define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 +#define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 +#define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 +#define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 +#define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 +#define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 +#define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 + + +// addressBlock: mmhub_l1tlb_vml1pldec +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: mmhub_l1tlb_vml1prdec +#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_atcl2dec +#define mmATCL2_0_ATC_L2_CNTL_DEFAULT 0x0001c0c9 +#define mmATCL2_0_ATC_L2_CNTL2_DEFAULT 0x00600100 +#define mmATCL2_0_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_CNTL3_DEFAULT 0x000001f8 +#define mmATCL2_0_ATC_L2_STATUS_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_STATUS2_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_STATUS3_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_MISC_CG_DEFAULT 0x00000200 +#define mmATCL2_0_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 +#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_CNTL4_DEFAULT 0x00000000 +#define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000005 + + +// addressBlock: mmhub_utcl2_vml2pfdec +#define mmVML2PF0_VM_L2_CNTL_DEFAULT 0x00080602 +#define mmVML2PF0_VM_L2_CNTL2_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CNTL3_DEFAULT 0x80100007 +#define mmVML2PF0_VM_L2_STATUS_DEFAULT 0x00000000 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CNTL4_DEFAULT 0x000000c1 +#define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 +#define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 + + +// addressBlock: mmhub_utcl2_vml2vcdec +#define mmVML2VC0_VM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC0_VM_CONTEXTS_DISABLE_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_vmsharedpfdec +#define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_DEFAULT 0x00000008 +#define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_FB_OFFSET_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_STEERING_DEFAULT 0x00000001 +#define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_APT_CNTL_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_DEFAULT 0x00000000 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_vmsharedvcdec +#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 +#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 +#define mmVMSHAREDVC0_MC_VM_AGP_TOP_DEFAULT 0x00000000 +#define mmVMSHAREDVC0_MC_VM_AGP_BOT_DEFAULT 0x00000000 +#define mmVMSHAREDVC0_MC_VM_AGP_BASE_DEFAULT 0x00000000 +#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 +#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 +#define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 + + +// addressBlock: mmhub_utcl2_vmsharedhvdec +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 +#define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec +#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: mmhub_utcl2_vml2pldec +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: mmhub_utcl2_vml2prdec +#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: mmhub_dagb_dagbdec5 +#define mmDAGB5_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB5_RD_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB5_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB5_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB5_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_RD_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB5_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB5_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB5_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB5_WR_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB5_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB5_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB5_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB5_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB5_WR_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB5_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB5_WR_DATA_CREDIT_DEFAULT 0x60606070 +#define mmDAGB5_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB5_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB5_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB5_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB5_CNTL_MISC2_DEFAULT 0x003c0000 +#define mmDAGB5_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB5_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB5_WR_CREDITS_FULL_DEFAULT 0x1fffffff +#define mmDAGB5_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB5_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB5_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB5_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB5_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB5_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB5_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB5_RESERVE0_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE1_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE2_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE3_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE4_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE5_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE6_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE7_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE8_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE9_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE10_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE11_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE12_DEFAULT 0xffffffff +#define mmDAGB5_RESERVE13_DEFAULT 0xffffffff + + +// addressBlock: mmhub_dagb_dagbdec6 +#define mmDAGB6_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB6_RD_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB6_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB6_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB6_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_RD_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB6_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB6_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB6_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB6_WR_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB6_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB6_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB6_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB6_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB6_WR_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB6_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB6_WR_DATA_CREDIT_DEFAULT 0x60606070 +#define mmDAGB6_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB6_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB6_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB6_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB6_CNTL_MISC2_DEFAULT 0x003c0000 +#define mmDAGB6_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB6_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB6_WR_CREDITS_FULL_DEFAULT 0x1fffffff +#define mmDAGB6_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB6_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB6_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB6_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB6_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB6_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB6_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB6_RESERVE0_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE1_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE2_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE3_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE4_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE5_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE6_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE7_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE8_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE9_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE10_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE11_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE12_DEFAULT 0xffffffff +#define mmDAGB6_RESERVE13_DEFAULT 0xffffffff + + +// addressBlock: mmhub_dagb_dagbdec7 +#define mmDAGB7_RDCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RDCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_RD_CNTL_DEFAULT 0x03527df8 +#define mmDAGB7_RD_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB7_RD_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB7_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB7_RD_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_RD_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_RD_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_RD_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_RD_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_RD_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_RD_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_RD_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_RD_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB7_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB7_RDCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_RDCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_RDCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_RDCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_RDCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_WRCLI0_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI1_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI2_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI3_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI4_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI5_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI6_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI7_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI8_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI9_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI10_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI11_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI12_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI13_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI14_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WRCLI15_DEFAULT 0xfe5fe0f9 +#define mmDAGB7_WR_CNTL_DEFAULT 0x03527df8 +#define mmDAGB7_WR_GMI_CNTL_DEFAULT 0x00003045 +#define mmDAGB7_WR_ADDR_DAGB_DEFAULT 0x00000039 +#define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 +#define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 +#define mmDAGB7_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 +#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 +#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 +#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 +#define mmDAGB7_WR_DATA_DAGB_DEFAULT 0x00000001 +#define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 +#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 +#define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 +#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 +#define mmDAGB7_WR_VC0_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_WR_VC1_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_WR_VC2_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_WR_VC3_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_WR_VC4_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_WR_VC5_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_WR_VC6_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_WR_VC7_CNTL_DEFAULT 0xff2ff082 +#define mmDAGB7_WR_CNTL_MISC_DEFAULT 0x69a0e408 +#define mmDAGB7_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 +#define mmDAGB7_WR_DATA_CREDIT_DEFAULT 0x60606070 +#define mmDAGB7_WR_MISC_CREDIT_DEFAULT 0x0078dc88 +#define mmDAGB7_WRCLI_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_WRCLI_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_WRCLI_TLB_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_WRCLI_OARB_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_WRCLI_OSD_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 +#define mmDAGB7_DAGB_DLY_DEFAULT 0x00000000 +#define mmDAGB7_CNTL_MISC_DEFAULT 0xcf7c1ffa +#define mmDAGB7_CNTL_MISC2_DEFAULT 0x003c0000 +#define mmDAGB7_FIFO_EMPTY_DEFAULT 0x00ffffff +#define mmDAGB7_FIFO_FULL_DEFAULT 0x00000000 +#define mmDAGB7_WR_CREDITS_FULL_DEFAULT 0x1fffffff +#define mmDAGB7_RD_CREDITS_FULL_DEFAULT 0x0003ffff +#define mmDAGB7_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmDAGB7_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmDAGB7_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmDAGB7_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmDAGB7_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmDAGB7_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmDAGB7_RESERVE0_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE1_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE2_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE3_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE4_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE5_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE6_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE7_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE8_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE9_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE10_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE11_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE12_DEFAULT 0xffffffff +#define mmDAGB7_RESERVE13_DEFAULT 0xffffffff + + +// addressBlock: mmhub_ea_mmeadec5 +#define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA5_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA5_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA5_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA5_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA5_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA5_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA5_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA5_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA5_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA5_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA5_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA5_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA5_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA5_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA5_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA5_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA5_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA5_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA5_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA5_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA5_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA5_GMI_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA5_GMI_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA5_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA5_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA5_GMI_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA5_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA5_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA5_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA5_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA5_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA5_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA5_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA5_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA5_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf +#define mmMMEA5_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA5_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA5_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA5_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA5_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA5_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA5_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA5_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA5_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA5_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA5_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA5_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA5_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA5_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA5_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA5_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA5_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA5_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA5_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA5_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA5_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA5_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA5_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA5_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA5_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA5_SDP_ARB_DRAM_DEFAULT 0x00101e40 +#define mmMMEA5_SDP_ARB_GMI_DEFAULT 0x00101e40 +#define mmMMEA5_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA5_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA5_SDP_GMI_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA5_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA5_SDP_CREDITS_DEFAULT 0x000101bf +#define mmMMEA5_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA5_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA5_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA5_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA5_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA5_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA5_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define mmMMEA5_MISC_DEFAULT 0x0c00a070 +#define mmMMEA5_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA5_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA5_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA5_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA5_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA5_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA5_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA5_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA5_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA5_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA5_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA5_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA5_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA5_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA5_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA5_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA5_ERR_STATUS_DEFAULT 0x00000300 +#define mmMMEA5_MISC2_DEFAULT 0x00000000 +#define mmMMEA5_ADDRDEC_SELECT_DEFAULT 0x00000000 +#define mmMMEA5_EDC_CNT3_DEFAULT 0x00000000 + + +// addressBlock: mmhub_ea_mmeadec6 +#define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA6_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA6_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA6_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA6_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA6_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA6_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA6_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA6_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA6_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA6_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA6_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA6_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA6_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA6_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA6_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA6_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA6_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA6_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA6_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA6_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA6_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA6_GMI_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA6_GMI_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA6_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA6_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA6_GMI_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA6_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA6_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA6_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA6_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA6_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA6_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA6_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA6_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA6_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf +#define mmMMEA6_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA6_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA6_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA6_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA6_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA6_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA6_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA6_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA6_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA6_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA6_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA6_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA6_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA6_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA6_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA6_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA6_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA6_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA6_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA6_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA6_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA6_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA6_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA6_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA6_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA6_SDP_ARB_DRAM_DEFAULT 0x00101e40 +#define mmMMEA6_SDP_ARB_GMI_DEFAULT 0x00101e40 +#define mmMMEA6_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA6_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA6_SDP_GMI_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA6_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA6_SDP_CREDITS_DEFAULT 0x000101bf +#define mmMMEA6_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA6_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA6_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA6_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA6_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA6_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA6_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define mmMMEA6_MISC_DEFAULT 0x0c00a070 +#define mmMMEA6_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA6_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA6_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA6_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA6_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA6_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA6_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA6_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA6_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA6_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA6_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA6_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA6_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA6_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA6_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA6_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA6_ERR_STATUS_DEFAULT 0x00000300 +#define mmMMEA6_MISC2_DEFAULT 0x00000000 +#define mmMMEA6_ADDRDEC_SELECT_DEFAULT 0x00000000 +#define mmMMEA6_EDC_CNT3_DEFAULT 0x00000000 + + +// addressBlock: mmhub_ea_mmeadec7 +#define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 +#define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 +#define mmMMEA7_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA7_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 +#define mmMMEA7_DRAM_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA7_DRAM_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA7_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA7_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA7_DRAM_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA7_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA7_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA7_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA7_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA7_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA7_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA7_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA7_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA7_GMI_RD_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA7_GMI_RD_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA7_GMI_WR_CLI2GRP_MAP0_DEFAULT 0x00000000 +#define mmMMEA7_GMI_WR_CLI2GRP_MAP1_DEFAULT 0x00000000 +#define mmMMEA7_GMI_RD_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA7_GMI_WR_GRP2VC_MAP_DEFAULT 0x00000fff +#define mmMMEA7_GMI_RD_LAZY_DEFAULT 0x78000924 +#define mmMMEA7_GMI_WR_LAZY_DEFAULT 0x78000924 +#define mmMMEA7_GMI_RD_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA7_GMI_WR_CAM_CNTL_DEFAULT 0x16db4444 +#define mmMMEA7_GMI_PAGE_BURST_DEFAULT 0x20002000 +#define mmMMEA7_GMI_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA7_GMI_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA7_GMI_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA7_GMI_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA7_GMI_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA7_GMI_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA7_GMI_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA7_GMI_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 +#define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA7_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_BASE_ADDR2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_BASE_ADDR3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_OFFSET_ADDR3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_BASE_ADDR4_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR4_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_BASE_ADDR5_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR5_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORM_OFFSET_ADDR5_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC_BANK_CFG_DEFAULT 0x000003cf +#define mmMMEA7_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA7_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA7_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe +#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_DEFAULT 0x00050408 +#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_DEFAULT 0x00050408 +#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_DEFAULT 0x04076543 +#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_DEFAULT 0x04076543 +#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT 0x00000008 +#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT 0x00000008 +#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT 0x87654321 +#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT 0x87654321 +#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT 0xa9876543 +#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT 0xa9876543 +#define mmMMEA7_ADDRDEC2_RM_SEL_CS01_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_RM_SEL_CS23_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_DEFAULT 0x00000000 +#define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT 0x00600000 +#define mmMMEA7_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA7_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA7_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 +#define mmMMEA7_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 +#define mmMMEA7_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA7_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 +#define mmMMEA7_IO_GROUP_BURST_DEFAULT 0x1f031f03 +#define mmMMEA7_IO_RD_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA7_IO_WR_PRI_AGE_DEFAULT 0x00db6249 +#define mmMMEA7_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA7_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 +#define mmMMEA7_IO_RD_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA7_IO_WR_PRI_FIXED_DEFAULT 0x00000924 +#define mmMMEA7_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA7_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 +#define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff +#define mmMMEA7_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA7_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA7_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA7_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f +#define mmMMEA7_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f +#define mmMMEA7_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff +#define mmMMEA7_SDP_ARB_DRAM_DEFAULT 0x00101e40 +#define mmMMEA7_SDP_ARB_GMI_DEFAULT 0x00101e40 +#define mmMMEA7_SDP_ARB_FINAL_DEFAULT 0x00007fff +#define mmMMEA7_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA7_SDP_GMI_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA7_SDP_IO_PRIORITY_DEFAULT 0x00000000 +#define mmMMEA7_SDP_CREDITS_DEFAULT 0x000101bf +#define mmMMEA7_SDP_TAG_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA7_SDP_TAG_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA7_SDP_VCC_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA7_SDP_VCC_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA7_SDP_VCD_RESERVE0_DEFAULT 0x00000000 +#define mmMMEA7_SDP_VCD_RESERVE1_DEFAULT 0x00000000 +#define mmMMEA7_SDP_REQ_CNTL_DEFAULT 0x0000001f +#define mmMMEA7_MISC_DEFAULT 0x0c00a070 +#define mmMMEA7_LATENCY_SAMPLING_DEFAULT 0x00000000 +#define mmMMEA7_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmMMEA7_PERFCOUNTER_HI_DEFAULT 0x00000000 +#define mmMMEA7_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmMMEA7_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmMMEA7_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 +#define mmMMEA7_EDC_CNT_DEFAULT 0x00000000 +#define mmMMEA7_EDC_CNT2_DEFAULT 0x00000000 +#define mmMMEA7_DSM_CNTL_DEFAULT 0x00000000 +#define mmMMEA7_DSM_CNTLA_DEFAULT 0x00000000 +#define mmMMEA7_DSM_CNTLB_DEFAULT 0x00000000 +#define mmMMEA7_DSM_CNTL2_DEFAULT 0x00000000 +#define mmMMEA7_DSM_CNTL2A_DEFAULT 0x00000000 +#define mmMMEA7_DSM_CNTL2B_DEFAULT 0x00000000 +#define mmMMEA7_CGTT_CLK_CTRL_DEFAULT 0x00000100 +#define mmMMEA7_EDC_MODE_DEFAULT 0x00000000 +#define mmMMEA7_ERR_STATUS_DEFAULT 0x00000300 +#define mmMMEA7_MISC2_DEFAULT 0x00000000 +#define mmMMEA7_ADDRDEC_SELECT_DEFAULT 0x00000000 +#define mmMMEA7_EDC_CNT3_DEFAULT 0x00000000 + + +// addressBlock: mmhub_pctldec1 +#define mmPCTL1_CTRL_DEFAULT 0x00011040 +#define mmPCTL1_MMHUB_DEEPSLEEP_IB_DEFAULT 0x00000000 +#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 +#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT 0x00000000 +#define mmPCTL1_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 +#define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_CFG_DAGB_BUSY_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_CFG_DS_ALLOW_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_MISC_DEFAULT 0x00011000 +#define mmPCTL1_SLICE0_MISC_DEFAULT 0x00000800 +#define mmPCTL1_SLICE1_MISC_DEFAULT 0x00000800 +#define mmPCTL1_SLICE2_MISC_DEFAULT 0x00000800 +#define mmPCTL1_SLICE3_MISC_DEFAULT 0x00000800 +#define mmPCTL1_SLICE4_MISC_DEFAULT 0x00000800 +#define mmPCTL1_UTCL2_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_RENG_EXECUTE_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_RENG_RAM_INDEX_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_RENG_RAM_DATA_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT 0xffffffff +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff + + +// addressBlock: mmhub_l1tlb_vml1dec:1 +#define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 +#define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 +#define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 +#define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 +#define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 +#define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 +#define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 +#define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 +#define mmVML1_1_MC_VM_MX_L1_TMZ_CNTL_DEFAULT 0x00000000 + + +// addressBlock: mmhub_l1tlb_vml1pldec:1 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: mmhub_l1tlb_vml1prdec:1 +#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_atcl2dec:1 +#define mmATCL2_1_ATC_L2_CNTL_DEFAULT 0x0001c0c9 +#define mmATCL2_1_ATC_L2_CNTL2_DEFAULT 0x00600100 +#define mmATCL2_1_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_CNTL3_DEFAULT 0x000001f8 +#define mmATCL2_1_ATC_L2_STATUS_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_STATUS2_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_STATUS3_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_MISC_CG_DEFAULT 0x00000200 +#define mmATCL2_1_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 +#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_CNTL4_DEFAULT 0x00000000 +#define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000005 + + +// addressBlock: mmhub_utcl2_vml2pfdec:1 +#define mmVML2PF1_VM_L2_CNTL_DEFAULT 0x00080602 +#define mmVML2PF1_VM_L2_CNTL2_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CNTL3_DEFAULT 0x80100007 +#define mmVML2PF1_VM_L2_STATUS_DEFAULT 0x00000000 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CNTL4_DEFAULT 0x000000c1 +#define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 +#define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 + + +// addressBlock: mmhub_utcl2_vml2vcdec:1 +#define mmVML2VC1_VM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 +#define mmVML2VC1_VM_CONTEXTS_DISABLE_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_vmsharedpfdec:1 +#define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_DEFAULT 0x00000008 +#define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_FB_OFFSET_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_STEERING_DEFAULT 0x00000001 +#define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_MEM_POWER_LS_DEFAULT 0x00000208 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_APT_CNTL_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_DEFAULT 0x00000000 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_vmsharedvcdec:1 +#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 +#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 +#define mmVMSHAREDVC1_MC_VM_AGP_TOP_DEFAULT 0x00000000 +#define mmVMSHAREDVC1_MC_VM_AGP_BOT_DEFAULT 0x00000000 +#define mmVMSHAREDVC1_MC_VM_AGP_BASE_DEFAULT 0x00000000 +#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 +#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 +#define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 + + +// addressBlock: mmhub_utcl2_vmsharedhvdec:1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 +#define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 +#define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 +#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec:1 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: mmhub_utcl2_vml2pldec:1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 + + +// addressBlock: mmhub_utcl2_vml2prdec:1 +#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 +#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h new file mode 100644 index 000000000000..d8632ccf3494 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h @@ -0,0 +1,7753 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mmhub_9_4_1_OFFSET_HEADER +#define _mmhub_9_4_1_OFFSET_HEADER + + + +// addressBlock: mmhub_dagb_dagbdec0 +// base address: 0x68000 +#define mmDAGB0_RDCLI0 0x0000 +#define mmDAGB0_RDCLI0_BASE_IDX 1 +#define mmDAGB0_RDCLI1 0x0001 +#define mmDAGB0_RDCLI1_BASE_IDX 1 +#define mmDAGB0_RDCLI2 0x0002 +#define mmDAGB0_RDCLI2_BASE_IDX 1 +#define mmDAGB0_RDCLI3 0x0003 +#define mmDAGB0_RDCLI3_BASE_IDX 1 +#define mmDAGB0_RDCLI4 0x0004 +#define mmDAGB0_RDCLI4_BASE_IDX 1 +#define mmDAGB0_RDCLI5 0x0005 +#define mmDAGB0_RDCLI5_BASE_IDX 1 +#define mmDAGB0_RDCLI6 0x0006 +#define mmDAGB0_RDCLI6_BASE_IDX 1 +#define mmDAGB0_RDCLI7 0x0007 +#define mmDAGB0_RDCLI7_BASE_IDX 1 +#define mmDAGB0_RDCLI8 0x0008 +#define mmDAGB0_RDCLI8_BASE_IDX 1 +#define mmDAGB0_RDCLI9 0x0009 +#define mmDAGB0_RDCLI9_BASE_IDX 1 +#define mmDAGB0_RDCLI10 0x000a +#define mmDAGB0_RDCLI10_BASE_IDX 1 +#define mmDAGB0_RDCLI11 0x000b +#define mmDAGB0_RDCLI11_BASE_IDX 1 +#define mmDAGB0_RDCLI12 0x000c +#define mmDAGB0_RDCLI12_BASE_IDX 1 +#define mmDAGB0_RDCLI13 0x000d +#define mmDAGB0_RDCLI13_BASE_IDX 1 +#define mmDAGB0_RDCLI14 0x000e +#define mmDAGB0_RDCLI14_BASE_IDX 1 +#define mmDAGB0_RDCLI15 0x000f +#define mmDAGB0_RDCLI15_BASE_IDX 1 +#define mmDAGB0_RD_CNTL 0x0010 +#define mmDAGB0_RD_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_GMI_CNTL 0x0011 +#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_ADDR_DAGB 0x0012 +#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013 +#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014 +#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015 +#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016 +#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017 +#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a +#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b +#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB0_RD_VC0_CNTL 0x001c +#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_VC1_CNTL 0x001d +#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_VC2_CNTL 0x001e +#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_VC3_CNTL 0x001f +#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_VC4_CNTL 0x0020 +#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_VC5_CNTL 0x0021 +#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_VC6_CNTL 0x0022 +#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_VC7_CNTL 0x0023 +#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 1 +#define mmDAGB0_RD_CNTL_MISC 0x0024 +#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 1 +#define mmDAGB0_RD_TLB_CREDIT 0x0025 +#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB0_RDCLI_ASK_PENDING 0x0026 +#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB0_RDCLI_GO_PENDING 0x0027 +#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028 +#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB0_RDCLI_TLB_PENDING 0x0029 +#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB0_RDCLI_OARB_PENDING 0x002a +#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB0_RDCLI_OSD_PENDING 0x002b +#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB0_WRCLI0 0x002c +#define mmDAGB0_WRCLI0_BASE_IDX 1 +#define mmDAGB0_WRCLI1 0x002d +#define mmDAGB0_WRCLI1_BASE_IDX 1 +#define mmDAGB0_WRCLI2 0x002e +#define mmDAGB0_WRCLI2_BASE_IDX 1 +#define mmDAGB0_WRCLI3 0x002f +#define mmDAGB0_WRCLI3_BASE_IDX 1 +#define mmDAGB0_WRCLI4 0x0030 +#define mmDAGB0_WRCLI4_BASE_IDX 1 +#define mmDAGB0_WRCLI5 0x0031 +#define mmDAGB0_WRCLI5_BASE_IDX 1 +#define mmDAGB0_WRCLI6 0x0032 +#define mmDAGB0_WRCLI6_BASE_IDX 1 +#define mmDAGB0_WRCLI7 0x0033 +#define mmDAGB0_WRCLI7_BASE_IDX 1 +#define mmDAGB0_WRCLI8 0x0034 +#define mmDAGB0_WRCLI8_BASE_IDX 1 +#define mmDAGB0_WRCLI9 0x0035 +#define mmDAGB0_WRCLI9_BASE_IDX 1 +#define mmDAGB0_WRCLI10 0x0036 +#define mmDAGB0_WRCLI10_BASE_IDX 1 +#define mmDAGB0_WRCLI11 0x0037 +#define mmDAGB0_WRCLI11_BASE_IDX 1 +#define mmDAGB0_WRCLI12 0x0038 +#define mmDAGB0_WRCLI12_BASE_IDX 1 +#define mmDAGB0_WRCLI13 0x0039 +#define mmDAGB0_WRCLI13_BASE_IDX 1 +#define mmDAGB0_WRCLI14 0x003a +#define mmDAGB0_WRCLI14_BASE_IDX 1 +#define mmDAGB0_WRCLI15 0x003b +#define mmDAGB0_WRCLI15_BASE_IDX 1 +#define mmDAGB0_WR_CNTL 0x003c +#define mmDAGB0_WR_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_GMI_CNTL 0x003d +#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_ADDR_DAGB 0x003e +#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f +#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040 +#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041 +#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042 +#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043 +#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046 +#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047 +#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB0_WR_DATA_DAGB 0x0048 +#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 1 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b +#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c +#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB0_WR_VC0_CNTL 0x004d +#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_VC1_CNTL 0x004e +#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_VC2_CNTL 0x004f +#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_VC3_CNTL 0x0050 +#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_VC4_CNTL 0x0051 +#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_VC5_CNTL 0x0052 +#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_VC6_CNTL 0x0053 +#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_VC7_CNTL 0x0054 +#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 1 +#define mmDAGB0_WR_CNTL_MISC 0x0055 +#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 1 +#define mmDAGB0_WR_TLB_CREDIT 0x0056 +#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB0_WR_DATA_CREDIT 0x0057 +#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 1 +#define mmDAGB0_WR_MISC_CREDIT 0x0058 +#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 1 +#define mmDAGB0_WRCLI_ASK_PENDING 0x005d +#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB0_WRCLI_GO_PENDING 0x005e +#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005f +#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB0_WRCLI_TLB_PENDING 0x0060 +#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB0_WRCLI_OARB_PENDING 0x0061 +#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB0_WRCLI_OSD_PENDING 0x0062 +#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x0063 +#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0064 +#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define mmDAGB0_DAGB_DLY 0x0065 +#define mmDAGB0_DAGB_DLY_BASE_IDX 1 +#define mmDAGB0_CNTL_MISC 0x0066 +#define mmDAGB0_CNTL_MISC_BASE_IDX 1 +#define mmDAGB0_CNTL_MISC2 0x0067 +#define mmDAGB0_CNTL_MISC2_BASE_IDX 1 +#define mmDAGB0_FIFO_EMPTY 0x0068 +#define mmDAGB0_FIFO_EMPTY_BASE_IDX 1 +#define mmDAGB0_FIFO_FULL 0x0069 +#define mmDAGB0_FIFO_FULL_BASE_IDX 1 +#define mmDAGB0_WR_CREDITS_FULL 0x006a +#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB0_RD_CREDITS_FULL 0x006b +#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB0_PERFCOUNTER_LO 0x006c +#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 1 +#define mmDAGB0_PERFCOUNTER_HI 0x006d +#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 1 +#define mmDAGB0_PERFCOUNTER0_CFG 0x006e +#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmDAGB0_PERFCOUNTER1_CFG 0x006f +#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmDAGB0_PERFCOUNTER2_CFG 0x0070 +#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x0071 +#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmDAGB0_RESERVE0 0x0072 +#define mmDAGB0_RESERVE0_BASE_IDX 1 +#define mmDAGB0_RESERVE1 0x0073 +#define mmDAGB0_RESERVE1_BASE_IDX 1 +#define mmDAGB0_RESERVE2 0x0074 +#define mmDAGB0_RESERVE2_BASE_IDX 1 +#define mmDAGB0_RESERVE3 0x0075 +#define mmDAGB0_RESERVE3_BASE_IDX 1 +#define mmDAGB0_RESERVE4 0x0076 +#define mmDAGB0_RESERVE4_BASE_IDX 1 +#define mmDAGB0_RESERVE5 0x0077 +#define mmDAGB0_RESERVE5_BASE_IDX 1 +#define mmDAGB0_RESERVE6 0x0078 +#define mmDAGB0_RESERVE6_BASE_IDX 1 +#define mmDAGB0_RESERVE7 0x0079 +#define mmDAGB0_RESERVE7_BASE_IDX 1 +#define mmDAGB0_RESERVE8 0x007a +#define mmDAGB0_RESERVE8_BASE_IDX 1 +#define mmDAGB0_RESERVE9 0x007b +#define mmDAGB0_RESERVE9_BASE_IDX 1 +#define mmDAGB0_RESERVE10 0x007c +#define mmDAGB0_RESERVE10_BASE_IDX 1 +#define mmDAGB0_RESERVE11 0x007d +#define mmDAGB0_RESERVE11_BASE_IDX 1 +#define mmDAGB0_RESERVE12 0x007e +#define mmDAGB0_RESERVE12_BASE_IDX 1 +#define mmDAGB0_RESERVE13 0x007f +#define mmDAGB0_RESERVE13_BASE_IDX 1 + + +// addressBlock: mmhub_dagb_dagbdec1 +// base address: 0x68200 +#define mmDAGB1_RDCLI0 0x0080 +#define mmDAGB1_RDCLI0_BASE_IDX 1 +#define mmDAGB1_RDCLI1 0x0081 +#define mmDAGB1_RDCLI1_BASE_IDX 1 +#define mmDAGB1_RDCLI2 0x0082 +#define mmDAGB1_RDCLI2_BASE_IDX 1 +#define mmDAGB1_RDCLI3 0x0083 +#define mmDAGB1_RDCLI3_BASE_IDX 1 +#define mmDAGB1_RDCLI4 0x0084 +#define mmDAGB1_RDCLI4_BASE_IDX 1 +#define mmDAGB1_RDCLI5 0x0085 +#define mmDAGB1_RDCLI5_BASE_IDX 1 +#define mmDAGB1_RDCLI6 0x0086 +#define mmDAGB1_RDCLI6_BASE_IDX 1 +#define mmDAGB1_RDCLI7 0x0087 +#define mmDAGB1_RDCLI7_BASE_IDX 1 +#define mmDAGB1_RDCLI8 0x0088 +#define mmDAGB1_RDCLI8_BASE_IDX 1 +#define mmDAGB1_RDCLI9 0x0089 +#define mmDAGB1_RDCLI9_BASE_IDX 1 +#define mmDAGB1_RDCLI10 0x008a +#define mmDAGB1_RDCLI10_BASE_IDX 1 +#define mmDAGB1_RDCLI11 0x008b +#define mmDAGB1_RDCLI11_BASE_IDX 1 +#define mmDAGB1_RDCLI12 0x008c +#define mmDAGB1_RDCLI12_BASE_IDX 1 +#define mmDAGB1_RDCLI13 0x008d +#define mmDAGB1_RDCLI13_BASE_IDX 1 +#define mmDAGB1_RDCLI14 0x008e +#define mmDAGB1_RDCLI14_BASE_IDX 1 +#define mmDAGB1_RDCLI15 0x008f +#define mmDAGB1_RDCLI15_BASE_IDX 1 +#define mmDAGB1_RD_CNTL 0x0090 +#define mmDAGB1_RD_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_GMI_CNTL 0x0091 +#define mmDAGB1_RD_GMI_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_ADDR_DAGB 0x0092 +#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093 +#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094 +#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095 +#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096 +#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097 +#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098 +#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099 +#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a +#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b +#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB1_RD_VC0_CNTL 0x009c +#define mmDAGB1_RD_VC0_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_VC1_CNTL 0x009d +#define mmDAGB1_RD_VC1_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_VC2_CNTL 0x009e +#define mmDAGB1_RD_VC2_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_VC3_CNTL 0x009f +#define mmDAGB1_RD_VC3_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_VC4_CNTL 0x00a0 +#define mmDAGB1_RD_VC4_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_VC5_CNTL 0x00a1 +#define mmDAGB1_RD_VC5_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_VC6_CNTL 0x00a2 +#define mmDAGB1_RD_VC6_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_VC7_CNTL 0x00a3 +#define mmDAGB1_RD_VC7_CNTL_BASE_IDX 1 +#define mmDAGB1_RD_CNTL_MISC 0x00a4 +#define mmDAGB1_RD_CNTL_MISC_BASE_IDX 1 +#define mmDAGB1_RD_TLB_CREDIT 0x00a5 +#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB1_RDCLI_ASK_PENDING 0x00a6 +#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB1_RDCLI_GO_PENDING 0x00a7 +#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8 +#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB1_RDCLI_TLB_PENDING 0x00a9 +#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB1_RDCLI_OARB_PENDING 0x00aa +#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB1_RDCLI_OSD_PENDING 0x00ab +#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB1_WRCLI0 0x00ac +#define mmDAGB1_WRCLI0_BASE_IDX 1 +#define mmDAGB1_WRCLI1 0x00ad +#define mmDAGB1_WRCLI1_BASE_IDX 1 +#define mmDAGB1_WRCLI2 0x00ae +#define mmDAGB1_WRCLI2_BASE_IDX 1 +#define mmDAGB1_WRCLI3 0x00af +#define mmDAGB1_WRCLI3_BASE_IDX 1 +#define mmDAGB1_WRCLI4 0x00b0 +#define mmDAGB1_WRCLI4_BASE_IDX 1 +#define mmDAGB1_WRCLI5 0x00b1 +#define mmDAGB1_WRCLI5_BASE_IDX 1 +#define mmDAGB1_WRCLI6 0x00b2 +#define mmDAGB1_WRCLI6_BASE_IDX 1 +#define mmDAGB1_WRCLI7 0x00b3 +#define mmDAGB1_WRCLI7_BASE_IDX 1 +#define mmDAGB1_WRCLI8 0x00b4 +#define mmDAGB1_WRCLI8_BASE_IDX 1 +#define mmDAGB1_WRCLI9 0x00b5 +#define mmDAGB1_WRCLI9_BASE_IDX 1 +#define mmDAGB1_WRCLI10 0x00b6 +#define mmDAGB1_WRCLI10_BASE_IDX 1 +#define mmDAGB1_WRCLI11 0x00b7 +#define mmDAGB1_WRCLI11_BASE_IDX 1 +#define mmDAGB1_WRCLI12 0x00b8 +#define mmDAGB1_WRCLI12_BASE_IDX 1 +#define mmDAGB1_WRCLI13 0x00b9 +#define mmDAGB1_WRCLI13_BASE_IDX 1 +#define mmDAGB1_WRCLI14 0x00ba +#define mmDAGB1_WRCLI14_BASE_IDX 1 +#define mmDAGB1_WRCLI15 0x00bb +#define mmDAGB1_WRCLI15_BASE_IDX 1 +#define mmDAGB1_WR_CNTL 0x00bc +#define mmDAGB1_WR_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_GMI_CNTL 0x00bd +#define mmDAGB1_WR_GMI_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_ADDR_DAGB 0x00be +#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf +#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0 +#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1 +#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2 +#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3 +#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4 +#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5 +#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6 +#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7 +#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB1_WR_DATA_DAGB 0x00c8 +#define mmDAGB1_WR_DATA_DAGB_BASE_IDX 1 +#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9 +#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca +#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb +#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc +#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB1_WR_VC0_CNTL 0x00cd +#define mmDAGB1_WR_VC0_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_VC1_CNTL 0x00ce +#define mmDAGB1_WR_VC1_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_VC2_CNTL 0x00cf +#define mmDAGB1_WR_VC2_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_VC3_CNTL 0x00d0 +#define mmDAGB1_WR_VC3_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_VC4_CNTL 0x00d1 +#define mmDAGB1_WR_VC4_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_VC5_CNTL 0x00d2 +#define mmDAGB1_WR_VC5_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_VC6_CNTL 0x00d3 +#define mmDAGB1_WR_VC6_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_VC7_CNTL 0x00d4 +#define mmDAGB1_WR_VC7_CNTL_BASE_IDX 1 +#define mmDAGB1_WR_CNTL_MISC 0x00d5 +#define mmDAGB1_WR_CNTL_MISC_BASE_IDX 1 +#define mmDAGB1_WR_TLB_CREDIT 0x00d6 +#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB1_WR_DATA_CREDIT 0x00d7 +#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 1 +#define mmDAGB1_WR_MISC_CREDIT 0x00d8 +#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 1 +#define mmDAGB1_WRCLI_ASK_PENDING 0x00dd +#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB1_WRCLI_GO_PENDING 0x00de +#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00df +#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB1_WRCLI_TLB_PENDING 0x00e0 +#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB1_WRCLI_OARB_PENDING 0x00e1 +#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB1_WRCLI_OSD_PENDING 0x00e2 +#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e3 +#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e4 +#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define mmDAGB1_DAGB_DLY 0x00e5 +#define mmDAGB1_DAGB_DLY_BASE_IDX 1 +#define mmDAGB1_CNTL_MISC 0x00e6 +#define mmDAGB1_CNTL_MISC_BASE_IDX 1 +#define mmDAGB1_CNTL_MISC2 0x00e7 +#define mmDAGB1_CNTL_MISC2_BASE_IDX 1 +#define mmDAGB1_FIFO_EMPTY 0x00e8 +#define mmDAGB1_FIFO_EMPTY_BASE_IDX 1 +#define mmDAGB1_FIFO_FULL 0x00e9 +#define mmDAGB1_FIFO_FULL_BASE_IDX 1 +#define mmDAGB1_WR_CREDITS_FULL 0x00ea +#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB1_RD_CREDITS_FULL 0x00eb +#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB1_PERFCOUNTER_LO 0x00ec +#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 1 +#define mmDAGB1_PERFCOUNTER_HI 0x00ed +#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 1 +#define mmDAGB1_PERFCOUNTER0_CFG 0x00ee +#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmDAGB1_PERFCOUNTER1_CFG 0x00ef +#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmDAGB1_PERFCOUNTER2_CFG 0x00f0 +#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00f1 +#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmDAGB1_RESERVE0 0x00f2 +#define mmDAGB1_RESERVE0_BASE_IDX 1 +#define mmDAGB1_RESERVE1 0x00f3 +#define mmDAGB1_RESERVE1_BASE_IDX 1 +#define mmDAGB1_RESERVE2 0x00f4 +#define mmDAGB1_RESERVE2_BASE_IDX 1 +#define mmDAGB1_RESERVE3 0x00f5 +#define mmDAGB1_RESERVE3_BASE_IDX 1 +#define mmDAGB1_RESERVE4 0x00f6 +#define mmDAGB1_RESERVE4_BASE_IDX 1 +#define mmDAGB1_RESERVE5 0x00f7 +#define mmDAGB1_RESERVE5_BASE_IDX 1 +#define mmDAGB1_RESERVE6 0x00f8 +#define mmDAGB1_RESERVE6_BASE_IDX 1 +#define mmDAGB1_RESERVE7 0x00f9 +#define mmDAGB1_RESERVE7_BASE_IDX 1 +#define mmDAGB1_RESERVE8 0x00fa +#define mmDAGB1_RESERVE8_BASE_IDX 1 +#define mmDAGB1_RESERVE9 0x00fb +#define mmDAGB1_RESERVE9_BASE_IDX 1 +#define mmDAGB1_RESERVE10 0x00fc +#define mmDAGB1_RESERVE10_BASE_IDX 1 +#define mmDAGB1_RESERVE11 0x00fd +#define mmDAGB1_RESERVE11_BASE_IDX 1 +#define mmDAGB1_RESERVE12 0x00fe +#define mmDAGB1_RESERVE12_BASE_IDX 1 +#define mmDAGB1_RESERVE13 0x00ff +#define mmDAGB1_RESERVE13_BASE_IDX 1 + + +// addressBlock: mmhub_dagb_dagbdec2 +// base address: 0x68400 +#define mmDAGB2_RDCLI0 0x0100 +#define mmDAGB2_RDCLI0_BASE_IDX 1 +#define mmDAGB2_RDCLI1 0x0101 +#define mmDAGB2_RDCLI1_BASE_IDX 1 +#define mmDAGB2_RDCLI2 0x0102 +#define mmDAGB2_RDCLI2_BASE_IDX 1 +#define mmDAGB2_RDCLI3 0x0103 +#define mmDAGB2_RDCLI3_BASE_IDX 1 +#define mmDAGB2_RDCLI4 0x0104 +#define mmDAGB2_RDCLI4_BASE_IDX 1 +#define mmDAGB2_RDCLI5 0x0105 +#define mmDAGB2_RDCLI5_BASE_IDX 1 +#define mmDAGB2_RDCLI6 0x0106 +#define mmDAGB2_RDCLI6_BASE_IDX 1 +#define mmDAGB2_RDCLI7 0x0107 +#define mmDAGB2_RDCLI7_BASE_IDX 1 +#define mmDAGB2_RDCLI8 0x0108 +#define mmDAGB2_RDCLI8_BASE_IDX 1 +#define mmDAGB2_RDCLI9 0x0109 +#define mmDAGB2_RDCLI9_BASE_IDX 1 +#define mmDAGB2_RDCLI10 0x010a +#define mmDAGB2_RDCLI10_BASE_IDX 1 +#define mmDAGB2_RDCLI11 0x010b +#define mmDAGB2_RDCLI11_BASE_IDX 1 +#define mmDAGB2_RDCLI12 0x010c +#define mmDAGB2_RDCLI12_BASE_IDX 1 +#define mmDAGB2_RDCLI13 0x010d +#define mmDAGB2_RDCLI13_BASE_IDX 1 +#define mmDAGB2_RDCLI14 0x010e +#define mmDAGB2_RDCLI14_BASE_IDX 1 +#define mmDAGB2_RDCLI15 0x010f +#define mmDAGB2_RDCLI15_BASE_IDX 1 +#define mmDAGB2_RD_CNTL 0x0110 +#define mmDAGB2_RD_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_GMI_CNTL 0x0111 +#define mmDAGB2_RD_GMI_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_ADDR_DAGB 0x0112 +#define mmDAGB2_RD_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113 +#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114 +#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB2_RD_CGTT_CLK_CTRL 0x0115 +#define mmDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116 +#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117 +#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118 +#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119 +#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a +#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b +#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB2_RD_VC0_CNTL 0x011c +#define mmDAGB2_RD_VC0_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_VC1_CNTL 0x011d +#define mmDAGB2_RD_VC1_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_VC2_CNTL 0x011e +#define mmDAGB2_RD_VC2_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_VC3_CNTL 0x011f +#define mmDAGB2_RD_VC3_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_VC4_CNTL 0x0120 +#define mmDAGB2_RD_VC4_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_VC5_CNTL 0x0121 +#define mmDAGB2_RD_VC5_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_VC6_CNTL 0x0122 +#define mmDAGB2_RD_VC6_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_VC7_CNTL 0x0123 +#define mmDAGB2_RD_VC7_CNTL_BASE_IDX 1 +#define mmDAGB2_RD_CNTL_MISC 0x0124 +#define mmDAGB2_RD_CNTL_MISC_BASE_IDX 1 +#define mmDAGB2_RD_TLB_CREDIT 0x0125 +#define mmDAGB2_RD_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB2_RDCLI_ASK_PENDING 0x0126 +#define mmDAGB2_RDCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB2_RDCLI_GO_PENDING 0x0127 +#define mmDAGB2_RDCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB2_RDCLI_GBLSEND_PENDING 0x0128 +#define mmDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB2_RDCLI_TLB_PENDING 0x0129 +#define mmDAGB2_RDCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB2_RDCLI_OARB_PENDING 0x012a +#define mmDAGB2_RDCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB2_RDCLI_OSD_PENDING 0x012b +#define mmDAGB2_RDCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB2_WRCLI0 0x012c +#define mmDAGB2_WRCLI0_BASE_IDX 1 +#define mmDAGB2_WRCLI1 0x012d +#define mmDAGB2_WRCLI1_BASE_IDX 1 +#define mmDAGB2_WRCLI2 0x012e +#define mmDAGB2_WRCLI2_BASE_IDX 1 +#define mmDAGB2_WRCLI3 0x012f +#define mmDAGB2_WRCLI3_BASE_IDX 1 +#define mmDAGB2_WRCLI4 0x0130 +#define mmDAGB2_WRCLI4_BASE_IDX 1 +#define mmDAGB2_WRCLI5 0x0131 +#define mmDAGB2_WRCLI5_BASE_IDX 1 +#define mmDAGB2_WRCLI6 0x0132 +#define mmDAGB2_WRCLI6_BASE_IDX 1 +#define mmDAGB2_WRCLI7 0x0133 +#define mmDAGB2_WRCLI7_BASE_IDX 1 +#define mmDAGB2_WRCLI8 0x0134 +#define mmDAGB2_WRCLI8_BASE_IDX 1 +#define mmDAGB2_WRCLI9 0x0135 +#define mmDAGB2_WRCLI9_BASE_IDX 1 +#define mmDAGB2_WRCLI10 0x0136 +#define mmDAGB2_WRCLI10_BASE_IDX 1 +#define mmDAGB2_WRCLI11 0x0137 +#define mmDAGB2_WRCLI11_BASE_IDX 1 +#define mmDAGB2_WRCLI12 0x0138 +#define mmDAGB2_WRCLI12_BASE_IDX 1 +#define mmDAGB2_WRCLI13 0x0139 +#define mmDAGB2_WRCLI13_BASE_IDX 1 +#define mmDAGB2_WRCLI14 0x013a +#define mmDAGB2_WRCLI14_BASE_IDX 1 +#define mmDAGB2_WRCLI15 0x013b +#define mmDAGB2_WRCLI15_BASE_IDX 1 +#define mmDAGB2_WR_CNTL 0x013c +#define mmDAGB2_WR_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_GMI_CNTL 0x013d +#define mmDAGB2_WR_GMI_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_ADDR_DAGB 0x013e +#define mmDAGB2_WR_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x013f +#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0140 +#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB2_WR_CGTT_CLK_CTRL 0x0141 +#define mmDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0142 +#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0143 +#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0144 +#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0145 +#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0146 +#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0147 +#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB2_WR_DATA_DAGB 0x0148 +#define mmDAGB2_WR_DATA_DAGB_BASE_IDX 1 +#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0 0x0149 +#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014a +#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014b +#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014c +#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB2_WR_VC0_CNTL 0x014d +#define mmDAGB2_WR_VC0_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_VC1_CNTL 0x014e +#define mmDAGB2_WR_VC1_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_VC2_CNTL 0x014f +#define mmDAGB2_WR_VC2_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_VC3_CNTL 0x0150 +#define mmDAGB2_WR_VC3_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_VC4_CNTL 0x0151 +#define mmDAGB2_WR_VC4_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_VC5_CNTL 0x0152 +#define mmDAGB2_WR_VC5_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_VC6_CNTL 0x0153 +#define mmDAGB2_WR_VC6_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_VC7_CNTL 0x0154 +#define mmDAGB2_WR_VC7_CNTL_BASE_IDX 1 +#define mmDAGB2_WR_CNTL_MISC 0x0155 +#define mmDAGB2_WR_CNTL_MISC_BASE_IDX 1 +#define mmDAGB2_WR_TLB_CREDIT 0x0156 +#define mmDAGB2_WR_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB2_WR_DATA_CREDIT 0x0157 +#define mmDAGB2_WR_DATA_CREDIT_BASE_IDX 1 +#define mmDAGB2_WR_MISC_CREDIT 0x0158 +#define mmDAGB2_WR_MISC_CREDIT_BASE_IDX 1 +#define mmDAGB2_WRCLI_ASK_PENDING 0x015d +#define mmDAGB2_WRCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB2_WRCLI_GO_PENDING 0x015e +#define mmDAGB2_WRCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB2_WRCLI_GBLSEND_PENDING 0x015f +#define mmDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB2_WRCLI_TLB_PENDING 0x0160 +#define mmDAGB2_WRCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB2_WRCLI_OARB_PENDING 0x0161 +#define mmDAGB2_WRCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB2_WRCLI_OSD_PENDING 0x0162 +#define mmDAGB2_WRCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB2_WRCLI_DBUS_ASK_PENDING 0x0163 +#define mmDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define mmDAGB2_WRCLI_DBUS_GO_PENDING 0x0164 +#define mmDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define mmDAGB2_DAGB_DLY 0x0165 +#define mmDAGB2_DAGB_DLY_BASE_IDX 1 +#define mmDAGB2_CNTL_MISC 0x0166 +#define mmDAGB2_CNTL_MISC_BASE_IDX 1 +#define mmDAGB2_CNTL_MISC2 0x0167 +#define mmDAGB2_CNTL_MISC2_BASE_IDX 1 +#define mmDAGB2_FIFO_EMPTY 0x0168 +#define mmDAGB2_FIFO_EMPTY_BASE_IDX 1 +#define mmDAGB2_FIFO_FULL 0x0169 +#define mmDAGB2_FIFO_FULL_BASE_IDX 1 +#define mmDAGB2_WR_CREDITS_FULL 0x016a +#define mmDAGB2_WR_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB2_RD_CREDITS_FULL 0x016b +#define mmDAGB2_RD_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB2_PERFCOUNTER_LO 0x016c +#define mmDAGB2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmDAGB2_PERFCOUNTER_HI 0x016d +#define mmDAGB2_PERFCOUNTER_HI_BASE_IDX 1 +#define mmDAGB2_PERFCOUNTER0_CFG 0x016e +#define mmDAGB2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmDAGB2_PERFCOUNTER1_CFG 0x016f +#define mmDAGB2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmDAGB2_PERFCOUNTER2_CFG 0x0170 +#define mmDAGB2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmDAGB2_PERFCOUNTER_RSLT_CNTL 0x0171 +#define mmDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmDAGB2_RESERVE0 0x0172 +#define mmDAGB2_RESERVE0_BASE_IDX 1 +#define mmDAGB2_RESERVE1 0x0173 +#define mmDAGB2_RESERVE1_BASE_IDX 1 +#define mmDAGB2_RESERVE2 0x0174 +#define mmDAGB2_RESERVE2_BASE_IDX 1 +#define mmDAGB2_RESERVE3 0x0175 +#define mmDAGB2_RESERVE3_BASE_IDX 1 +#define mmDAGB2_RESERVE4 0x0176 +#define mmDAGB2_RESERVE4_BASE_IDX 1 +#define mmDAGB2_RESERVE5 0x0177 +#define mmDAGB2_RESERVE5_BASE_IDX 1 +#define mmDAGB2_RESERVE6 0x0178 +#define mmDAGB2_RESERVE6_BASE_IDX 1 +#define mmDAGB2_RESERVE7 0x0179 +#define mmDAGB2_RESERVE7_BASE_IDX 1 +#define mmDAGB2_RESERVE8 0x017a +#define mmDAGB2_RESERVE8_BASE_IDX 1 +#define mmDAGB2_RESERVE9 0x017b +#define mmDAGB2_RESERVE9_BASE_IDX 1 +#define mmDAGB2_RESERVE10 0x017c +#define mmDAGB2_RESERVE10_BASE_IDX 1 +#define mmDAGB2_RESERVE11 0x017d +#define mmDAGB2_RESERVE11_BASE_IDX 1 +#define mmDAGB2_RESERVE12 0x017e +#define mmDAGB2_RESERVE12_BASE_IDX 1 +#define mmDAGB2_RESERVE13 0x017f +#define mmDAGB2_RESERVE13_BASE_IDX 1 + + +// addressBlock: mmhub_dagb_dagbdec3 +// base address: 0x68600 +#define mmDAGB3_RDCLI0 0x0180 +#define mmDAGB3_RDCLI0_BASE_IDX 1 +#define mmDAGB3_RDCLI1 0x0181 +#define mmDAGB3_RDCLI1_BASE_IDX 1 +#define mmDAGB3_RDCLI2 0x0182 +#define mmDAGB3_RDCLI2_BASE_IDX 1 +#define mmDAGB3_RDCLI3 0x0183 +#define mmDAGB3_RDCLI3_BASE_IDX 1 +#define mmDAGB3_RDCLI4 0x0184 +#define mmDAGB3_RDCLI4_BASE_IDX 1 +#define mmDAGB3_RDCLI5 0x0185 +#define mmDAGB3_RDCLI5_BASE_IDX 1 +#define mmDAGB3_RDCLI6 0x0186 +#define mmDAGB3_RDCLI6_BASE_IDX 1 +#define mmDAGB3_RDCLI7 0x0187 +#define mmDAGB3_RDCLI7_BASE_IDX 1 +#define mmDAGB3_RDCLI8 0x0188 +#define mmDAGB3_RDCLI8_BASE_IDX 1 +#define mmDAGB3_RDCLI9 0x0189 +#define mmDAGB3_RDCLI9_BASE_IDX 1 +#define mmDAGB3_RDCLI10 0x018a +#define mmDAGB3_RDCLI10_BASE_IDX 1 +#define mmDAGB3_RDCLI11 0x018b +#define mmDAGB3_RDCLI11_BASE_IDX 1 +#define mmDAGB3_RDCLI12 0x018c +#define mmDAGB3_RDCLI12_BASE_IDX 1 +#define mmDAGB3_RDCLI13 0x018d +#define mmDAGB3_RDCLI13_BASE_IDX 1 +#define mmDAGB3_RDCLI14 0x018e +#define mmDAGB3_RDCLI14_BASE_IDX 1 +#define mmDAGB3_RDCLI15 0x018f +#define mmDAGB3_RDCLI15_BASE_IDX 1 +#define mmDAGB3_RD_CNTL 0x0190 +#define mmDAGB3_RD_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_GMI_CNTL 0x0191 +#define mmDAGB3_RD_GMI_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_ADDR_DAGB 0x0192 +#define mmDAGB3_RD_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193 +#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194 +#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB3_RD_CGTT_CLK_CTRL 0x0195 +#define mmDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196 +#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197 +#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198 +#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199 +#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a +#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b +#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB3_RD_VC0_CNTL 0x019c +#define mmDAGB3_RD_VC0_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_VC1_CNTL 0x019d +#define mmDAGB3_RD_VC1_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_VC2_CNTL 0x019e +#define mmDAGB3_RD_VC2_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_VC3_CNTL 0x019f +#define mmDAGB3_RD_VC3_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_VC4_CNTL 0x01a0 +#define mmDAGB3_RD_VC4_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_VC5_CNTL 0x01a1 +#define mmDAGB3_RD_VC5_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_VC6_CNTL 0x01a2 +#define mmDAGB3_RD_VC6_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_VC7_CNTL 0x01a3 +#define mmDAGB3_RD_VC7_CNTL_BASE_IDX 1 +#define mmDAGB3_RD_CNTL_MISC 0x01a4 +#define mmDAGB3_RD_CNTL_MISC_BASE_IDX 1 +#define mmDAGB3_RD_TLB_CREDIT 0x01a5 +#define mmDAGB3_RD_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB3_RDCLI_ASK_PENDING 0x01a6 +#define mmDAGB3_RDCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB3_RDCLI_GO_PENDING 0x01a7 +#define mmDAGB3_RDCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB3_RDCLI_GBLSEND_PENDING 0x01a8 +#define mmDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB3_RDCLI_TLB_PENDING 0x01a9 +#define mmDAGB3_RDCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB3_RDCLI_OARB_PENDING 0x01aa +#define mmDAGB3_RDCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB3_RDCLI_OSD_PENDING 0x01ab +#define mmDAGB3_RDCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB3_WRCLI0 0x01ac +#define mmDAGB3_WRCLI0_BASE_IDX 1 +#define mmDAGB3_WRCLI1 0x01ad +#define mmDAGB3_WRCLI1_BASE_IDX 1 +#define mmDAGB3_WRCLI2 0x01ae +#define mmDAGB3_WRCLI2_BASE_IDX 1 +#define mmDAGB3_WRCLI3 0x01af +#define mmDAGB3_WRCLI3_BASE_IDX 1 +#define mmDAGB3_WRCLI4 0x01b0 +#define mmDAGB3_WRCLI4_BASE_IDX 1 +#define mmDAGB3_WRCLI5 0x01b1 +#define mmDAGB3_WRCLI5_BASE_IDX 1 +#define mmDAGB3_WRCLI6 0x01b2 +#define mmDAGB3_WRCLI6_BASE_IDX 1 +#define mmDAGB3_WRCLI7 0x01b3 +#define mmDAGB3_WRCLI7_BASE_IDX 1 +#define mmDAGB3_WRCLI8 0x01b4 +#define mmDAGB3_WRCLI8_BASE_IDX 1 +#define mmDAGB3_WRCLI9 0x01b5 +#define mmDAGB3_WRCLI9_BASE_IDX 1 +#define mmDAGB3_WRCLI10 0x01b6 +#define mmDAGB3_WRCLI10_BASE_IDX 1 +#define mmDAGB3_WRCLI11 0x01b7 +#define mmDAGB3_WRCLI11_BASE_IDX 1 +#define mmDAGB3_WRCLI12 0x01b8 +#define mmDAGB3_WRCLI12_BASE_IDX 1 +#define mmDAGB3_WRCLI13 0x01b9 +#define mmDAGB3_WRCLI13_BASE_IDX 1 +#define mmDAGB3_WRCLI14 0x01ba +#define mmDAGB3_WRCLI14_BASE_IDX 1 +#define mmDAGB3_WRCLI15 0x01bb +#define mmDAGB3_WRCLI15_BASE_IDX 1 +#define mmDAGB3_WR_CNTL 0x01bc +#define mmDAGB3_WR_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_GMI_CNTL 0x01bd +#define mmDAGB3_WR_GMI_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_ADDR_DAGB 0x01be +#define mmDAGB3_WR_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01bf +#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c0 +#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB3_WR_CGTT_CLK_CTRL 0x01c1 +#define mmDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c2 +#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c3 +#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c4 +#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c5 +#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c6 +#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c7 +#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB3_WR_DATA_DAGB 0x01c8 +#define mmDAGB3_WR_DATA_DAGB_BASE_IDX 1 +#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01c9 +#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01ca +#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cb +#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01cc +#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB3_WR_VC0_CNTL 0x01cd +#define mmDAGB3_WR_VC0_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_VC1_CNTL 0x01ce +#define mmDAGB3_WR_VC1_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_VC2_CNTL 0x01cf +#define mmDAGB3_WR_VC2_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_VC3_CNTL 0x01d0 +#define mmDAGB3_WR_VC3_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_VC4_CNTL 0x01d1 +#define mmDAGB3_WR_VC4_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_VC5_CNTL 0x01d2 +#define mmDAGB3_WR_VC5_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_VC6_CNTL 0x01d3 +#define mmDAGB3_WR_VC6_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_VC7_CNTL 0x01d4 +#define mmDAGB3_WR_VC7_CNTL_BASE_IDX 1 +#define mmDAGB3_WR_CNTL_MISC 0x01d5 +#define mmDAGB3_WR_CNTL_MISC_BASE_IDX 1 +#define mmDAGB3_WR_TLB_CREDIT 0x01d6 +#define mmDAGB3_WR_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB3_WR_DATA_CREDIT 0x01d7 +#define mmDAGB3_WR_DATA_CREDIT_BASE_IDX 1 +#define mmDAGB3_WR_MISC_CREDIT 0x01d8 +#define mmDAGB3_WR_MISC_CREDIT_BASE_IDX 1 +#define mmDAGB3_WRCLI_ASK_PENDING 0x01dd +#define mmDAGB3_WRCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB3_WRCLI_GO_PENDING 0x01de +#define mmDAGB3_WRCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB3_WRCLI_GBLSEND_PENDING 0x01df +#define mmDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB3_WRCLI_TLB_PENDING 0x01e0 +#define mmDAGB3_WRCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB3_WRCLI_OARB_PENDING 0x01e1 +#define mmDAGB3_WRCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB3_WRCLI_OSD_PENDING 0x01e2 +#define mmDAGB3_WRCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e3 +#define mmDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define mmDAGB3_WRCLI_DBUS_GO_PENDING 0x01e4 +#define mmDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define mmDAGB3_DAGB_DLY 0x01e5 +#define mmDAGB3_DAGB_DLY_BASE_IDX 1 +#define mmDAGB3_CNTL_MISC 0x01e6 +#define mmDAGB3_CNTL_MISC_BASE_IDX 1 +#define mmDAGB3_CNTL_MISC2 0x01e7 +#define mmDAGB3_CNTL_MISC2_BASE_IDX 1 +#define mmDAGB3_FIFO_EMPTY 0x01e8 +#define mmDAGB3_FIFO_EMPTY_BASE_IDX 1 +#define mmDAGB3_FIFO_FULL 0x01e9 +#define mmDAGB3_FIFO_FULL_BASE_IDX 1 +#define mmDAGB3_WR_CREDITS_FULL 0x01ea +#define mmDAGB3_WR_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB3_RD_CREDITS_FULL 0x01eb +#define mmDAGB3_RD_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB3_PERFCOUNTER_LO 0x01ec +#define mmDAGB3_PERFCOUNTER_LO_BASE_IDX 1 +#define mmDAGB3_PERFCOUNTER_HI 0x01ed +#define mmDAGB3_PERFCOUNTER_HI_BASE_IDX 1 +#define mmDAGB3_PERFCOUNTER0_CFG 0x01ee +#define mmDAGB3_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmDAGB3_PERFCOUNTER1_CFG 0x01ef +#define mmDAGB3_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmDAGB3_PERFCOUNTER2_CFG 0x01f0 +#define mmDAGB3_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmDAGB3_PERFCOUNTER_RSLT_CNTL 0x01f1 +#define mmDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmDAGB3_RESERVE0 0x01f2 +#define mmDAGB3_RESERVE0_BASE_IDX 1 +#define mmDAGB3_RESERVE1 0x01f3 +#define mmDAGB3_RESERVE1_BASE_IDX 1 +#define mmDAGB3_RESERVE2 0x01f4 +#define mmDAGB3_RESERVE2_BASE_IDX 1 +#define mmDAGB3_RESERVE3 0x01f5 +#define mmDAGB3_RESERVE3_BASE_IDX 1 +#define mmDAGB3_RESERVE4 0x01f6 +#define mmDAGB3_RESERVE4_BASE_IDX 1 +#define mmDAGB3_RESERVE5 0x01f7 +#define mmDAGB3_RESERVE5_BASE_IDX 1 +#define mmDAGB3_RESERVE6 0x01f8 +#define mmDAGB3_RESERVE6_BASE_IDX 1 +#define mmDAGB3_RESERVE7 0x01f9 +#define mmDAGB3_RESERVE7_BASE_IDX 1 +#define mmDAGB3_RESERVE8 0x01fa +#define mmDAGB3_RESERVE8_BASE_IDX 1 +#define mmDAGB3_RESERVE9 0x01fb +#define mmDAGB3_RESERVE9_BASE_IDX 1 +#define mmDAGB3_RESERVE10 0x01fc +#define mmDAGB3_RESERVE10_BASE_IDX 1 +#define mmDAGB3_RESERVE11 0x01fd +#define mmDAGB3_RESERVE11_BASE_IDX 1 +#define mmDAGB3_RESERVE12 0x01fe +#define mmDAGB3_RESERVE12_BASE_IDX 1 +#define mmDAGB3_RESERVE13 0x01ff +#define mmDAGB3_RESERVE13_BASE_IDX 1 + + +// addressBlock: mmhub_dagb_dagbdec4 +// base address: 0x68800 +#define mmDAGB4_RDCLI0 0x0200 +#define mmDAGB4_RDCLI0_BASE_IDX 1 +#define mmDAGB4_RDCLI1 0x0201 +#define mmDAGB4_RDCLI1_BASE_IDX 1 +#define mmDAGB4_RDCLI2 0x0202 +#define mmDAGB4_RDCLI2_BASE_IDX 1 +#define mmDAGB4_RDCLI3 0x0203 +#define mmDAGB4_RDCLI3_BASE_IDX 1 +#define mmDAGB4_RDCLI4 0x0204 +#define mmDAGB4_RDCLI4_BASE_IDX 1 +#define mmDAGB4_RDCLI5 0x0205 +#define mmDAGB4_RDCLI5_BASE_IDX 1 +#define mmDAGB4_RDCLI6 0x0206 +#define mmDAGB4_RDCLI6_BASE_IDX 1 +#define mmDAGB4_RDCLI7 0x0207 +#define mmDAGB4_RDCLI7_BASE_IDX 1 +#define mmDAGB4_RDCLI8 0x0208 +#define mmDAGB4_RDCLI8_BASE_IDX 1 +#define mmDAGB4_RDCLI9 0x0209 +#define mmDAGB4_RDCLI9_BASE_IDX 1 +#define mmDAGB4_RDCLI10 0x020a +#define mmDAGB4_RDCLI10_BASE_IDX 1 +#define mmDAGB4_RDCLI11 0x020b +#define mmDAGB4_RDCLI11_BASE_IDX 1 +#define mmDAGB4_RDCLI12 0x020c +#define mmDAGB4_RDCLI12_BASE_IDX 1 +#define mmDAGB4_RDCLI13 0x020d +#define mmDAGB4_RDCLI13_BASE_IDX 1 +#define mmDAGB4_RDCLI14 0x020e +#define mmDAGB4_RDCLI14_BASE_IDX 1 +#define mmDAGB4_RDCLI15 0x020f +#define mmDAGB4_RDCLI15_BASE_IDX 1 +#define mmDAGB4_RD_CNTL 0x0210 +#define mmDAGB4_RD_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_GMI_CNTL 0x0211 +#define mmDAGB4_RD_GMI_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_ADDR_DAGB 0x0212 +#define mmDAGB4_RD_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213 +#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214 +#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB4_RD_CGTT_CLK_CTRL 0x0215 +#define mmDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216 +#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217 +#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218 +#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219 +#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a +#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b +#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB4_RD_VC0_CNTL 0x021c +#define mmDAGB4_RD_VC0_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_VC1_CNTL 0x021d +#define mmDAGB4_RD_VC1_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_VC2_CNTL 0x021e +#define mmDAGB4_RD_VC2_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_VC3_CNTL 0x021f +#define mmDAGB4_RD_VC3_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_VC4_CNTL 0x0220 +#define mmDAGB4_RD_VC4_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_VC5_CNTL 0x0221 +#define mmDAGB4_RD_VC5_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_VC6_CNTL 0x0222 +#define mmDAGB4_RD_VC6_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_VC7_CNTL 0x0223 +#define mmDAGB4_RD_VC7_CNTL_BASE_IDX 1 +#define mmDAGB4_RD_CNTL_MISC 0x0224 +#define mmDAGB4_RD_CNTL_MISC_BASE_IDX 1 +#define mmDAGB4_RD_TLB_CREDIT 0x0225 +#define mmDAGB4_RD_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB4_RDCLI_ASK_PENDING 0x0226 +#define mmDAGB4_RDCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB4_RDCLI_GO_PENDING 0x0227 +#define mmDAGB4_RDCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB4_RDCLI_GBLSEND_PENDING 0x0228 +#define mmDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB4_RDCLI_TLB_PENDING 0x0229 +#define mmDAGB4_RDCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB4_RDCLI_OARB_PENDING 0x022a +#define mmDAGB4_RDCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB4_RDCLI_OSD_PENDING 0x022b +#define mmDAGB4_RDCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB4_WRCLI0 0x022c +#define mmDAGB4_WRCLI0_BASE_IDX 1 +#define mmDAGB4_WRCLI1 0x022d +#define mmDAGB4_WRCLI1_BASE_IDX 1 +#define mmDAGB4_WRCLI2 0x022e +#define mmDAGB4_WRCLI2_BASE_IDX 1 +#define mmDAGB4_WRCLI3 0x022f +#define mmDAGB4_WRCLI3_BASE_IDX 1 +#define mmDAGB4_WRCLI4 0x0230 +#define mmDAGB4_WRCLI4_BASE_IDX 1 +#define mmDAGB4_WRCLI5 0x0231 +#define mmDAGB4_WRCLI5_BASE_IDX 1 +#define mmDAGB4_WRCLI6 0x0232 +#define mmDAGB4_WRCLI6_BASE_IDX 1 +#define mmDAGB4_WRCLI7 0x0233 +#define mmDAGB4_WRCLI7_BASE_IDX 1 +#define mmDAGB4_WRCLI8 0x0234 +#define mmDAGB4_WRCLI8_BASE_IDX 1 +#define mmDAGB4_WRCLI9 0x0235 +#define mmDAGB4_WRCLI9_BASE_IDX 1 +#define mmDAGB4_WRCLI10 0x0236 +#define mmDAGB4_WRCLI10_BASE_IDX 1 +#define mmDAGB4_WRCLI11 0x0237 +#define mmDAGB4_WRCLI11_BASE_IDX 1 +#define mmDAGB4_WRCLI12 0x0238 +#define mmDAGB4_WRCLI12_BASE_IDX 1 +#define mmDAGB4_WRCLI13 0x0239 +#define mmDAGB4_WRCLI13_BASE_IDX 1 +#define mmDAGB4_WRCLI14 0x023a +#define mmDAGB4_WRCLI14_BASE_IDX 1 +#define mmDAGB4_WRCLI15 0x023b +#define mmDAGB4_WRCLI15_BASE_IDX 1 +#define mmDAGB4_WR_CNTL 0x023c +#define mmDAGB4_WR_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_GMI_CNTL 0x023d +#define mmDAGB4_WR_GMI_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_ADDR_DAGB 0x023e +#define mmDAGB4_WR_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x023f +#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0240 +#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB4_WR_CGTT_CLK_CTRL 0x0241 +#define mmDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0242 +#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0243 +#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0244 +#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0245 +#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0246 +#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0247 +#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB4_WR_DATA_DAGB 0x0248 +#define mmDAGB4_WR_DATA_DAGB_BASE_IDX 1 +#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0 0x0249 +#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024a +#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024b +#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024c +#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB4_WR_VC0_CNTL 0x024d +#define mmDAGB4_WR_VC0_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_VC1_CNTL 0x024e +#define mmDAGB4_WR_VC1_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_VC2_CNTL 0x024f +#define mmDAGB4_WR_VC2_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_VC3_CNTL 0x0250 +#define mmDAGB4_WR_VC3_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_VC4_CNTL 0x0251 +#define mmDAGB4_WR_VC4_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_VC5_CNTL 0x0252 +#define mmDAGB4_WR_VC5_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_VC6_CNTL 0x0253 +#define mmDAGB4_WR_VC6_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_VC7_CNTL 0x0254 +#define mmDAGB4_WR_VC7_CNTL_BASE_IDX 1 +#define mmDAGB4_WR_CNTL_MISC 0x0255 +#define mmDAGB4_WR_CNTL_MISC_BASE_IDX 1 +#define mmDAGB4_WR_TLB_CREDIT 0x0256 +#define mmDAGB4_WR_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB4_WR_DATA_CREDIT 0x0257 +#define mmDAGB4_WR_DATA_CREDIT_BASE_IDX 1 +#define mmDAGB4_WR_MISC_CREDIT 0x0258 +#define mmDAGB4_WR_MISC_CREDIT_BASE_IDX 1 +#define mmDAGB4_WRCLI_ASK_PENDING 0x025d +#define mmDAGB4_WRCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB4_WRCLI_GO_PENDING 0x025e +#define mmDAGB4_WRCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB4_WRCLI_GBLSEND_PENDING 0x025f +#define mmDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB4_WRCLI_TLB_PENDING 0x0260 +#define mmDAGB4_WRCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB4_WRCLI_OARB_PENDING 0x0261 +#define mmDAGB4_WRCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB4_WRCLI_OSD_PENDING 0x0262 +#define mmDAGB4_WRCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB4_WRCLI_DBUS_ASK_PENDING 0x0263 +#define mmDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define mmDAGB4_WRCLI_DBUS_GO_PENDING 0x0264 +#define mmDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define mmDAGB4_DAGB_DLY 0x0265 +#define mmDAGB4_DAGB_DLY_BASE_IDX 1 +#define mmDAGB4_CNTL_MISC 0x0266 +#define mmDAGB4_CNTL_MISC_BASE_IDX 1 +#define mmDAGB4_CNTL_MISC2 0x0267 +#define mmDAGB4_CNTL_MISC2_BASE_IDX 1 +#define mmDAGB4_FIFO_EMPTY 0x0268 +#define mmDAGB4_FIFO_EMPTY_BASE_IDX 1 +#define mmDAGB4_FIFO_FULL 0x0269 +#define mmDAGB4_FIFO_FULL_BASE_IDX 1 +#define mmDAGB4_WR_CREDITS_FULL 0x026a +#define mmDAGB4_WR_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB4_RD_CREDITS_FULL 0x026b +#define mmDAGB4_RD_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB4_PERFCOUNTER_LO 0x026c +#define mmDAGB4_PERFCOUNTER_LO_BASE_IDX 1 +#define mmDAGB4_PERFCOUNTER_HI 0x026d +#define mmDAGB4_PERFCOUNTER_HI_BASE_IDX 1 +#define mmDAGB4_PERFCOUNTER0_CFG 0x026e +#define mmDAGB4_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmDAGB4_PERFCOUNTER1_CFG 0x026f +#define mmDAGB4_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmDAGB4_PERFCOUNTER2_CFG 0x0270 +#define mmDAGB4_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmDAGB4_PERFCOUNTER_RSLT_CNTL 0x0271 +#define mmDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmDAGB4_RESERVE0 0x0272 +#define mmDAGB4_RESERVE0_BASE_IDX 1 +#define mmDAGB4_RESERVE1 0x0273 +#define mmDAGB4_RESERVE1_BASE_IDX 1 +#define mmDAGB4_RESERVE2 0x0274 +#define mmDAGB4_RESERVE2_BASE_IDX 1 +#define mmDAGB4_RESERVE3 0x0275 +#define mmDAGB4_RESERVE3_BASE_IDX 1 +#define mmDAGB4_RESERVE4 0x0276 +#define mmDAGB4_RESERVE4_BASE_IDX 1 +#define mmDAGB4_RESERVE5 0x0277 +#define mmDAGB4_RESERVE5_BASE_IDX 1 +#define mmDAGB4_RESERVE6 0x0278 +#define mmDAGB4_RESERVE6_BASE_IDX 1 +#define mmDAGB4_RESERVE7 0x0279 +#define mmDAGB4_RESERVE7_BASE_IDX 1 +#define mmDAGB4_RESERVE8 0x027a +#define mmDAGB4_RESERVE8_BASE_IDX 1 +#define mmDAGB4_RESERVE9 0x027b +#define mmDAGB4_RESERVE9_BASE_IDX 1 +#define mmDAGB4_RESERVE10 0x027c +#define mmDAGB4_RESERVE10_BASE_IDX 1 +#define mmDAGB4_RESERVE11 0x027d +#define mmDAGB4_RESERVE11_BASE_IDX 1 +#define mmDAGB4_RESERVE12 0x027e +#define mmDAGB4_RESERVE12_BASE_IDX 1 +#define mmDAGB4_RESERVE13 0x027f +#define mmDAGB4_RESERVE13_BASE_IDX 1 + + +// addressBlock: mmhub_ea_mmeadec0 +// base address: 0x68a00 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0280 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0281 +#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0282 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0283 +#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0284 +#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0285 +#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_LAZY 0x0286 +#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_LAZY 0x0287 +#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0288 +#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0289 +#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA0_DRAM_PAGE_BURST 0x028a +#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_PRI_AGE 0x028b +#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_PRI_AGE 0x028c +#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x028d +#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x028e +#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_PRI_FIXED 0x028f +#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0290 +#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0291 +#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0292 +#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0293 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0294 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0295 +#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0296 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0297 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0298 +#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA0_GMI_RD_CLI2GRP_MAP0 0x0299 +#define mmMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA0_GMI_RD_CLI2GRP_MAP1 0x029a +#define mmMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA0_GMI_WR_CLI2GRP_MAP0 0x029b +#define mmMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA0_GMI_WR_CLI2GRP_MAP1 0x029c +#define mmMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA0_GMI_RD_GRP2VC_MAP 0x029d +#define mmMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA0_GMI_WR_GRP2VC_MAP 0x029e +#define mmMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA0_GMI_RD_LAZY 0x029f +#define mmMMEA0_GMI_RD_LAZY_BASE_IDX 1 +#define mmMMEA0_GMI_WR_LAZY 0x02a0 +#define mmMMEA0_GMI_WR_LAZY_BASE_IDX 1 +#define mmMMEA0_GMI_RD_CAM_CNTL 0x02a1 +#define mmMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA0_GMI_WR_CAM_CNTL 0x02a2 +#define mmMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA0_GMI_PAGE_BURST 0x02a3 +#define mmMMEA0_GMI_PAGE_BURST_BASE_IDX 1 +#define mmMMEA0_GMI_RD_PRI_AGE 0x02a4 +#define mmMMEA0_GMI_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA0_GMI_WR_PRI_AGE 0x02a5 +#define mmMMEA0_GMI_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA0_GMI_RD_PRI_QUEUING 0x02a6 +#define mmMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA0_GMI_WR_PRI_QUEUING 0x02a7 +#define mmMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA0_GMI_RD_PRI_FIXED 0x02a8 +#define mmMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA0_GMI_WR_PRI_FIXED 0x02a9 +#define mmMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA0_GMI_RD_PRI_URGENCY 0x02aa +#define mmMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA0_GMI_WR_PRI_URGENCY 0x02ab +#define mmMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x02ac +#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x02ad +#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1 0x02ae +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2 0x02af +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3 0x02b0 +#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1 0x02b1 +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2 0x02b2 +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3 0x02b3 +#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x02b4 +#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x02b5 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x02b6 +#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x02b7 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x02b8 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_BASE_ADDR2 0x02b9 +#define mmMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR2 0x02ba +#define mmMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_BASE_ADDR3 0x02bb +#define mmMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR3 0x02bc +#define mmMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR3 0x02bd +#define mmMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_BASE_ADDR4 0x02be +#define mmMMEA0_ADDRNORM_BASE_ADDR4_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR4 0x02bf +#define mmMMEA0_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_BASE_ADDR5 0x02c0 +#define mmMMEA0_ADDRNORM_BASE_ADDR5_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR5 0x02c1 +#define mmMMEA0_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR5 0x02c2 +#define mmMMEA0_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 +#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x02c3 +#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL 0x02c4 +#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x02c5 +#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x02c6 +#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA0_ADDRDEC_BANK_CFG 0x02c7 +#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 1 +#define mmMMEA0_ADDRDEC_MISC_CFG 0x02c8 +#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x02c9 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x02ca +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x02cb +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x02cc +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x02cd +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0x02ce +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x02cf +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x02d0 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x02d1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x02d2 +#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x02d3 +#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0 0x02d4 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1 0x02d5 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2 0x02d6 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3 0x02d7 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4 0x02d8 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5 0x02d9 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC 0x02da +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2 0x02db +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0 0x02dc +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1 0x02dd +#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x02de +#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x02df +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x02e0 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x02e1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x02e2 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x02e3 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x02e4 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x02e5 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x02e6 +#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x02e7 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x02e8 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x02e9 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x02ea +#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x02eb +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x02ec +#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x02ed +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x02ee +#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x02ef +#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x02f0 +#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x02f1 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x02f2 +#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x02f3 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x02f4 +#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x02f5 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x02f6 +#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x02f7 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x02f8 +#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x02f9 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x02fa +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x02fb +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x02fc +#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x02fd +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x02fe +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x02ff +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0300 +#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0301 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0302 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0303 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0304 +#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0305 +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0306 +#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0307 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0308 +#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0309 +#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x030a +#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x030b +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x030c +#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x030d +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x030e +#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x030f +#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0310 +#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0311 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0312 +#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0313 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0314 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0315 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0316 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0317 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0318 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0319 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x031a +#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x031b +#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x031c +#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x031d +#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x031e +#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x031f +#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x0320 +#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x0321 +#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x0322 +#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x0323 +#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x0324 +#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x0325 +#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x0326 +#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x0327 +#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x0328 +#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_RM_SEL_CS01 0x0329 +#define mmMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_RM_SEL_CS23 0x032a +#define mmMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x032b +#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x032c +#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x032d +#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x032e +#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x0355 +#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x0356 +#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x0357 +#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x0358 +#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x0359 +#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x035a +#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA0_IO_GROUP_BURST 0x035b +#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 1 +#define mmMMEA0_IO_RD_PRI_AGE 0x035c +#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA0_IO_WR_PRI_AGE 0x035d +#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA0_IO_RD_PRI_QUEUING 0x035e +#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA0_IO_WR_PRI_QUEUING 0x035f +#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA0_IO_RD_PRI_FIXED 0x0360 +#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA0_IO_WR_PRI_FIXED 0x0361 +#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA0_IO_RD_PRI_URGENCY 0x0362 +#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA0_IO_WR_PRI_URGENCY 0x0363 +#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x0364 +#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x0365 +#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x0366 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x0367 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x0368 +#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x0369 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x036a +#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x036b +#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA0_SDP_ARB_DRAM 0x036c +#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 1 +#define mmMMEA0_SDP_ARB_GMI 0x036d +#define mmMMEA0_SDP_ARB_GMI_BASE_IDX 1 +#define mmMMEA0_SDP_ARB_FINAL 0x036e +#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 1 +#define mmMMEA0_SDP_DRAM_PRIORITY 0x036f +#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 1 +#define mmMMEA0_SDP_GMI_PRIORITY 0x0370 +#define mmMMEA0_SDP_GMI_PRIORITY_BASE_IDX 1 +#define mmMMEA0_SDP_IO_PRIORITY 0x0371 +#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 1 +#define mmMMEA0_SDP_CREDITS 0x0372 +#define mmMMEA0_SDP_CREDITS_BASE_IDX 1 +#define mmMMEA0_SDP_TAG_RESERVE0 0x0373 +#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 1 +#define mmMMEA0_SDP_TAG_RESERVE1 0x0374 +#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 1 +#define mmMMEA0_SDP_VCC_RESERVE0 0x0375 +#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 1 +#define mmMMEA0_SDP_VCC_RESERVE1 0x0376 +#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 1 +#define mmMMEA0_SDP_VCD_RESERVE0 0x0377 +#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 1 +#define mmMMEA0_SDP_VCD_RESERVE1 0x0378 +#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 1 +#define mmMMEA0_SDP_REQ_CNTL 0x0379 +#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 1 +#define mmMMEA0_MISC 0x037a +#define mmMMEA0_MISC_BASE_IDX 1 +#define mmMMEA0_LATENCY_SAMPLING 0x037b +#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 1 +#define mmMMEA0_PERFCOUNTER_LO 0x037c +#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMMEA0_PERFCOUNTER_HI 0x037d +#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 1 +#define mmMMEA0_PERFCOUNTER0_CFG 0x037e +#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMMEA0_PERFCOUNTER1_CFG 0x037f +#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0380 +#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmMMEA0_EDC_CNT 0x0386 +#define mmMMEA0_EDC_CNT_BASE_IDX 1 +#define mmMMEA0_EDC_CNT2 0x0387 +#define mmMMEA0_EDC_CNT2_BASE_IDX 1 +#define mmMMEA0_DSM_CNTL 0x0388 +#define mmMMEA0_DSM_CNTL_BASE_IDX 1 +#define mmMMEA0_DSM_CNTLA 0x0389 +#define mmMMEA0_DSM_CNTLA_BASE_IDX 1 +#define mmMMEA0_DSM_CNTLB 0x038a +#define mmMMEA0_DSM_CNTLB_BASE_IDX 1 +#define mmMMEA0_DSM_CNTL2 0x038b +#define mmMMEA0_DSM_CNTL2_BASE_IDX 1 +#define mmMMEA0_DSM_CNTL2A 0x038c +#define mmMMEA0_DSM_CNTL2A_BASE_IDX 1 +#define mmMMEA0_DSM_CNTL2B 0x038d +#define mmMMEA0_DSM_CNTL2B_BASE_IDX 1 +#define mmMMEA0_CGTT_CLK_CTRL 0x038f +#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmMMEA0_EDC_MODE 0x0390 +#define mmMMEA0_EDC_MODE_BASE_IDX 1 +#define mmMMEA0_ERR_STATUS 0x0391 +#define mmMMEA0_ERR_STATUS_BASE_IDX 1 +#define mmMMEA0_MISC2 0x0392 +#define mmMMEA0_MISC2_BASE_IDX 1 +#define mmMMEA0_ADDRDEC_SELECT 0x0393 +#define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 1 +#define mmMMEA0_EDC_CNT3 0x0394 +#define mmMMEA0_EDC_CNT3_BASE_IDX 1 + + +// addressBlock: mmhub_ea_mmeadec1 +// base address: 0x68f00 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x03c0 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x03c1 +#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x03c2 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x03c3 +#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x03c4 +#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x03c5 +#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_LAZY 0x03c6 +#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_LAZY 0x03c7 +#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_CAM_CNTL 0x03c8 +#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_CAM_CNTL 0x03c9 +#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA1_DRAM_PAGE_BURST 0x03ca +#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_PRI_AGE 0x03cb +#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_PRI_AGE 0x03cc +#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x03cd +#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x03ce +#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_PRI_FIXED 0x03cf +#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_PRI_FIXED 0x03d0 +#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x03d1 +#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x03d2 +#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x03d3 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x03d4 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x03d5 +#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x03d6 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x03d7 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x03d8 +#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA1_GMI_RD_CLI2GRP_MAP0 0x03d9 +#define mmMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA1_GMI_RD_CLI2GRP_MAP1 0x03da +#define mmMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA1_GMI_WR_CLI2GRP_MAP0 0x03db +#define mmMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA1_GMI_WR_CLI2GRP_MAP1 0x03dc +#define mmMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA1_GMI_RD_GRP2VC_MAP 0x03dd +#define mmMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA1_GMI_WR_GRP2VC_MAP 0x03de +#define mmMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA1_GMI_RD_LAZY 0x03df +#define mmMMEA1_GMI_RD_LAZY_BASE_IDX 1 +#define mmMMEA1_GMI_WR_LAZY 0x03e0 +#define mmMMEA1_GMI_WR_LAZY_BASE_IDX 1 +#define mmMMEA1_GMI_RD_CAM_CNTL 0x03e1 +#define mmMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA1_GMI_WR_CAM_CNTL 0x03e2 +#define mmMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA1_GMI_PAGE_BURST 0x03e3 +#define mmMMEA1_GMI_PAGE_BURST_BASE_IDX 1 +#define mmMMEA1_GMI_RD_PRI_AGE 0x03e4 +#define mmMMEA1_GMI_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA1_GMI_WR_PRI_AGE 0x03e5 +#define mmMMEA1_GMI_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA1_GMI_RD_PRI_QUEUING 0x03e6 +#define mmMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA1_GMI_WR_PRI_QUEUING 0x03e7 +#define mmMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA1_GMI_RD_PRI_FIXED 0x03e8 +#define mmMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA1_GMI_WR_PRI_FIXED 0x03e9 +#define mmMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA1_GMI_RD_PRI_URGENCY 0x03ea +#define mmMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA1_GMI_WR_PRI_URGENCY 0x03eb +#define mmMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x03ec +#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x03ed +#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1 0x03ee +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2 0x03ef +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3 0x03f0 +#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1 0x03f1 +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2 0x03f2 +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3 0x03f3 +#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x03f4 +#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x03f5 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x03f6 +#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x03f7 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x03f8 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_BASE_ADDR2 0x03f9 +#define mmMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR2 0x03fa +#define mmMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_BASE_ADDR3 0x03fb +#define mmMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR3 0x03fc +#define mmMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR3 0x03fd +#define mmMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_BASE_ADDR4 0x03fe +#define mmMMEA1_ADDRNORM_BASE_ADDR4_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR4 0x03ff +#define mmMMEA1_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_BASE_ADDR5 0x0400 +#define mmMMEA1_ADDRNORM_BASE_ADDR5_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR5 0x0401 +#define mmMMEA1_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR5 0x0402 +#define mmMMEA1_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 +#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0403 +#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0404 +#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0405 +#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0406 +#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA1_ADDRDEC_BANK_CFG 0x0407 +#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 1 +#define mmMMEA1_ADDRDEC_MISC_CFG 0x0408 +#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0409 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x040a +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x040b +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x040c +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x040d +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 0x040e +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x040f +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x0410 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x0411 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x0412 +#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0413 +#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0 0x0414 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1 0x0415 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2 0x0416 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3 0x0417 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4 0x0418 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5 0x0419 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC 0x041a +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2 0x041b +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0 0x041c +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1 0x041d +#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x041e +#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x041f +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0420 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x0421 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x0422 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x0423 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x0424 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x0425 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x0426 +#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x0427 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x0428 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x0429 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x042a +#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x042b +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x042c +#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x042d +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x042e +#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x042f +#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x0430 +#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x0431 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x0432 +#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x0433 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x0434 +#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x0435 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x0436 +#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x0437 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x0438 +#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x0439 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x043a +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x043b +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x043c +#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x043d +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x043e +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x043f +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x0440 +#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x0441 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x0442 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x0443 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x0444 +#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x0445 +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x0446 +#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x0447 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x0448 +#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x0449 +#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x044a +#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x044b +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x044c +#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x044d +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x044e +#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x044f +#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x0450 +#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x0451 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x0452 +#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x0453 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x0454 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x0455 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x0456 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x0457 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x0458 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x0459 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x045a +#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x045b +#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x045c +#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x045d +#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x045e +#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x045f +#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x0460 +#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x0461 +#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x0462 +#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x0463 +#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x0464 +#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x0465 +#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x0466 +#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x0467 +#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x0468 +#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_RM_SEL_CS01 0x0469 +#define mmMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_RM_SEL_CS23 0x046a +#define mmMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x046b +#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x046c +#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x046d +#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x046e +#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0495 +#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0496 +#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0497 +#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0498 +#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0499 +#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x049a +#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA1_IO_GROUP_BURST 0x049b +#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 1 +#define mmMMEA1_IO_RD_PRI_AGE 0x049c +#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA1_IO_WR_PRI_AGE 0x049d +#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA1_IO_RD_PRI_QUEUING 0x049e +#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA1_IO_WR_PRI_QUEUING 0x049f +#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA1_IO_RD_PRI_FIXED 0x04a0 +#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA1_IO_WR_PRI_FIXED 0x04a1 +#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA1_IO_RD_PRI_URGENCY 0x04a2 +#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA1_IO_WR_PRI_URGENCY 0x04a3 +#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING 0x04a4 +#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING 0x04a5 +#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x04a6 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x04a7 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x04a8 +#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x04a9 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x04aa +#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x04ab +#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA1_SDP_ARB_DRAM 0x04ac +#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 1 +#define mmMMEA1_SDP_ARB_GMI 0x04ad +#define mmMMEA1_SDP_ARB_GMI_BASE_IDX 1 +#define mmMMEA1_SDP_ARB_FINAL 0x04ae +#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 1 +#define mmMMEA1_SDP_DRAM_PRIORITY 0x04af +#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 1 +#define mmMMEA1_SDP_GMI_PRIORITY 0x04b0 +#define mmMMEA1_SDP_GMI_PRIORITY_BASE_IDX 1 +#define mmMMEA1_SDP_IO_PRIORITY 0x04b1 +#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 1 +#define mmMMEA1_SDP_CREDITS 0x04b2 +#define mmMMEA1_SDP_CREDITS_BASE_IDX 1 +#define mmMMEA1_SDP_TAG_RESERVE0 0x04b3 +#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 1 +#define mmMMEA1_SDP_TAG_RESERVE1 0x04b4 +#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 1 +#define mmMMEA1_SDP_VCC_RESERVE0 0x04b5 +#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 1 +#define mmMMEA1_SDP_VCC_RESERVE1 0x04b6 +#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 1 +#define mmMMEA1_SDP_VCD_RESERVE0 0x04b7 +#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 1 +#define mmMMEA1_SDP_VCD_RESERVE1 0x04b8 +#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 1 +#define mmMMEA1_SDP_REQ_CNTL 0x04b9 +#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 1 +#define mmMMEA1_MISC 0x04ba +#define mmMMEA1_MISC_BASE_IDX 1 +#define mmMMEA1_LATENCY_SAMPLING 0x04bb +#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 1 +#define mmMMEA1_PERFCOUNTER_LO 0x04bc +#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMMEA1_PERFCOUNTER_HI 0x04bd +#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 1 +#define mmMMEA1_PERFCOUNTER0_CFG 0x04be +#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMMEA1_PERFCOUNTER1_CFG 0x04bf +#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x04c0 +#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmMMEA1_EDC_CNT 0x04c6 +#define mmMMEA1_EDC_CNT_BASE_IDX 1 +#define mmMMEA1_EDC_CNT2 0x04c7 +#define mmMMEA1_EDC_CNT2_BASE_IDX 1 +#define mmMMEA1_DSM_CNTL 0x04c8 +#define mmMMEA1_DSM_CNTL_BASE_IDX 1 +#define mmMMEA1_DSM_CNTLA 0x04c9 +#define mmMMEA1_DSM_CNTLA_BASE_IDX 1 +#define mmMMEA1_DSM_CNTLB 0x04ca +#define mmMMEA1_DSM_CNTLB_BASE_IDX 1 +#define mmMMEA1_DSM_CNTL2 0x04cb +#define mmMMEA1_DSM_CNTL2_BASE_IDX 1 +#define mmMMEA1_DSM_CNTL2A 0x04cc +#define mmMMEA1_DSM_CNTL2A_BASE_IDX 1 +#define mmMMEA1_DSM_CNTL2B 0x04cd +#define mmMMEA1_DSM_CNTL2B_BASE_IDX 1 +#define mmMMEA1_CGTT_CLK_CTRL 0x04cf +#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmMMEA1_EDC_MODE 0x04d0 +#define mmMMEA1_EDC_MODE_BASE_IDX 1 +#define mmMMEA1_ERR_STATUS 0x04d1 +#define mmMMEA1_ERR_STATUS_BASE_IDX 1 +#define mmMMEA1_MISC2 0x04d2 +#define mmMMEA1_MISC2_BASE_IDX 1 +#define mmMMEA1_ADDRDEC_SELECT 0x04d3 +#define mmMMEA1_ADDRDEC_SELECT_BASE_IDX 1 +#define mmMMEA1_EDC_CNT3 0x04d4 +#define mmMMEA1_EDC_CNT3_BASE_IDX 1 + + +// addressBlock: mmhub_ea_mmeadec2 +// base address: 0x69400 +#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0500 +#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0501 +#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0502 +#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0503 +#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_GRP2VC_MAP 0x0504 +#define mmMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_GRP2VC_MAP 0x0505 +#define mmMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_LAZY 0x0506 +#define mmMMEA2_DRAM_RD_LAZY_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_LAZY 0x0507 +#define mmMMEA2_DRAM_WR_LAZY_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_CAM_CNTL 0x0508 +#define mmMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_CAM_CNTL 0x0509 +#define mmMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA2_DRAM_PAGE_BURST 0x050a +#define mmMMEA2_DRAM_PAGE_BURST_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_PRI_AGE 0x050b +#define mmMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_PRI_AGE 0x050c +#define mmMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_PRI_QUEUING 0x050d +#define mmMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_PRI_QUEUING 0x050e +#define mmMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_PRI_FIXED 0x050f +#define mmMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_PRI_FIXED 0x0510 +#define mmMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_PRI_URGENCY 0x0511 +#define mmMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_PRI_URGENCY 0x0512 +#define mmMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0513 +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0514 +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0515 +#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0516 +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0517 +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0518 +#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA2_GMI_RD_CLI2GRP_MAP0 0x0519 +#define mmMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA2_GMI_RD_CLI2GRP_MAP1 0x051a +#define mmMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA2_GMI_WR_CLI2GRP_MAP0 0x051b +#define mmMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA2_GMI_WR_CLI2GRP_MAP1 0x051c +#define mmMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA2_GMI_RD_GRP2VC_MAP 0x051d +#define mmMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA2_GMI_WR_GRP2VC_MAP 0x051e +#define mmMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA2_GMI_RD_LAZY 0x051f +#define mmMMEA2_GMI_RD_LAZY_BASE_IDX 1 +#define mmMMEA2_GMI_WR_LAZY 0x0520 +#define mmMMEA2_GMI_WR_LAZY_BASE_IDX 1 +#define mmMMEA2_GMI_RD_CAM_CNTL 0x0521 +#define mmMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA2_GMI_WR_CAM_CNTL 0x0522 +#define mmMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA2_GMI_PAGE_BURST 0x0523 +#define mmMMEA2_GMI_PAGE_BURST_BASE_IDX 1 +#define mmMMEA2_GMI_RD_PRI_AGE 0x0524 +#define mmMMEA2_GMI_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA2_GMI_WR_PRI_AGE 0x0525 +#define mmMMEA2_GMI_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA2_GMI_RD_PRI_QUEUING 0x0526 +#define mmMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA2_GMI_WR_PRI_QUEUING 0x0527 +#define mmMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA2_GMI_RD_PRI_FIXED 0x0528 +#define mmMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA2_GMI_WR_PRI_FIXED 0x0529 +#define mmMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA2_GMI_RD_PRI_URGENCY 0x052a +#define mmMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA2_GMI_WR_PRI_URGENCY 0x052b +#define mmMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x052c +#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x052d +#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1 0x052e +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2 0x052f +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3 0x0530 +#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1 0x0531 +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2 0x0532 +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3 0x0533 +#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_BASE_ADDR0 0x0534 +#define mmMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR0 0x0535 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_BASE_ADDR1 0x0536 +#define mmMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR1 0x0537 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_OFFSET_ADDR1 0x0538 +#define mmMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_BASE_ADDR2 0x0539 +#define mmMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR2 0x053a +#define mmMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_BASE_ADDR3 0x053b +#define mmMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR3 0x053c +#define mmMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_OFFSET_ADDR3 0x053d +#define mmMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_BASE_ADDR4 0x053e +#define mmMMEA2_ADDRNORM_BASE_ADDR4_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR4 0x053f +#define mmMMEA2_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_BASE_ADDR5 0x0540 +#define mmMMEA2_ADDRNORM_BASE_ADDR5_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR5 0x0541 +#define mmMMEA2_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 +#define mmMMEA2_ADDRNORM_OFFSET_ADDR5 0x0542 +#define mmMMEA2_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 +#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x0543 +#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL 0x0544 +#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0545 +#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0546 +#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA2_ADDRDEC_BANK_CFG 0x0547 +#define mmMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 1 +#define mmMMEA2_ADDRDEC_MISC_CFG 0x0548 +#define mmMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 0x0549 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 0x054a +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 0x054b +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 0x054c +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 0x054d +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 0x054e +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC 0x054f +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2 0x0550 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0 0x0551 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1 0x0552 +#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x0553 +#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0 0x0554 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1 0x0555 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2 0x0556 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3 0x0557 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4 0x0558 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5 0x0559 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC 0x055a +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2 0x055b +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0 0x055c +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1 0x055d +#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x055e +#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x055f +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x0560 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x0561 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x0562 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x0563 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x0564 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x0565 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x0566 +#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x0567 +#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x0568 +#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x0569 +#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x056a +#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x056b +#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x056c +#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x056d +#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x056e +#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x056f +#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x0570 +#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x0571 +#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x0572 +#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x0573 +#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x0574 +#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_RM_SEL_CS01 0x0575 +#define mmMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_RM_SEL_CS23 0x0576 +#define mmMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x0577 +#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x0578 +#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x0579 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x057a +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x057b +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x057c +#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x057d +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x057e +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x057f +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0580 +#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0581 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0582 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0583 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0584 +#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0585 +#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0586 +#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0587 +#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0588 +#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0589 +#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x058a +#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x058b +#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x058c +#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x058d +#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x058e +#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_RM_SEL_CS01 0x058f +#define mmMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_RM_SEL_CS23 0x0590 +#define mmMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0591 +#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0592 +#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0593 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0594 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0595 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0596 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0597 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0598 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0599 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x059a +#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x059b +#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x059c +#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x059d +#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x059e +#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x059f +#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x05a0 +#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x05a1 +#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x05a2 +#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x05a3 +#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x05a4 +#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x05a5 +#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x05a6 +#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x05a7 +#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x05a8 +#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_RM_SEL_CS01 0x05a9 +#define mmMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_RM_SEL_CS23 0x05aa +#define mmMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x05ab +#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x05ac +#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x05ad +#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x05ae +#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA2_IO_RD_CLI2GRP_MAP0 0x05d5 +#define mmMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA2_IO_RD_CLI2GRP_MAP1 0x05d6 +#define mmMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA2_IO_WR_CLI2GRP_MAP0 0x05d7 +#define mmMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA2_IO_WR_CLI2GRP_MAP1 0x05d8 +#define mmMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA2_IO_RD_COMBINE_FLUSH 0x05d9 +#define mmMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA2_IO_WR_COMBINE_FLUSH 0x05da +#define mmMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA2_IO_GROUP_BURST 0x05db +#define mmMMEA2_IO_GROUP_BURST_BASE_IDX 1 +#define mmMMEA2_IO_RD_PRI_AGE 0x05dc +#define mmMMEA2_IO_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA2_IO_WR_PRI_AGE 0x05dd +#define mmMMEA2_IO_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA2_IO_RD_PRI_QUEUING 0x05de +#define mmMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA2_IO_WR_PRI_QUEUING 0x05df +#define mmMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA2_IO_RD_PRI_FIXED 0x05e0 +#define mmMMEA2_IO_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA2_IO_WR_PRI_FIXED 0x05e1 +#define mmMMEA2_IO_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA2_IO_RD_PRI_URGENCY 0x05e2 +#define mmMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA2_IO_WR_PRI_URGENCY 0x05e3 +#define mmMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA2_IO_RD_PRI_URGENCY_MASKING 0x05e4 +#define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA2_IO_WR_PRI_URGENCY_MASKING 0x05e5 +#define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA2_IO_RD_PRI_QUANT_PRI1 0x05e6 +#define mmMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA2_IO_RD_PRI_QUANT_PRI2 0x05e7 +#define mmMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA2_IO_RD_PRI_QUANT_PRI3 0x05e8 +#define mmMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA2_IO_WR_PRI_QUANT_PRI1 0x05e9 +#define mmMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA2_IO_WR_PRI_QUANT_PRI2 0x05ea +#define mmMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA2_IO_WR_PRI_QUANT_PRI3 0x05eb +#define mmMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA2_SDP_ARB_DRAM 0x05ec +#define mmMMEA2_SDP_ARB_DRAM_BASE_IDX 1 +#define mmMMEA2_SDP_ARB_GMI 0x05ed +#define mmMMEA2_SDP_ARB_GMI_BASE_IDX 1 +#define mmMMEA2_SDP_ARB_FINAL 0x05ee +#define mmMMEA2_SDP_ARB_FINAL_BASE_IDX 1 +#define mmMMEA2_SDP_DRAM_PRIORITY 0x05ef +#define mmMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 1 +#define mmMMEA2_SDP_GMI_PRIORITY 0x05f0 +#define mmMMEA2_SDP_GMI_PRIORITY_BASE_IDX 1 +#define mmMMEA2_SDP_IO_PRIORITY 0x05f1 +#define mmMMEA2_SDP_IO_PRIORITY_BASE_IDX 1 +#define mmMMEA2_SDP_CREDITS 0x05f2 +#define mmMMEA2_SDP_CREDITS_BASE_IDX 1 +#define mmMMEA2_SDP_TAG_RESERVE0 0x05f3 +#define mmMMEA2_SDP_TAG_RESERVE0_BASE_IDX 1 +#define mmMMEA2_SDP_TAG_RESERVE1 0x05f4 +#define mmMMEA2_SDP_TAG_RESERVE1_BASE_IDX 1 +#define mmMMEA2_SDP_VCC_RESERVE0 0x05f5 +#define mmMMEA2_SDP_VCC_RESERVE0_BASE_IDX 1 +#define mmMMEA2_SDP_VCC_RESERVE1 0x05f6 +#define mmMMEA2_SDP_VCC_RESERVE1_BASE_IDX 1 +#define mmMMEA2_SDP_VCD_RESERVE0 0x05f7 +#define mmMMEA2_SDP_VCD_RESERVE0_BASE_IDX 1 +#define mmMMEA2_SDP_VCD_RESERVE1 0x05f8 +#define mmMMEA2_SDP_VCD_RESERVE1_BASE_IDX 1 +#define mmMMEA2_SDP_REQ_CNTL 0x05f9 +#define mmMMEA2_SDP_REQ_CNTL_BASE_IDX 1 +#define mmMMEA2_MISC 0x05fa +#define mmMMEA2_MISC_BASE_IDX 1 +#define mmMMEA2_LATENCY_SAMPLING 0x05fb +#define mmMMEA2_LATENCY_SAMPLING_BASE_IDX 1 +#define mmMMEA2_PERFCOUNTER_LO 0x05fc +#define mmMMEA2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMMEA2_PERFCOUNTER_HI 0x05fd +#define mmMMEA2_PERFCOUNTER_HI_BASE_IDX 1 +#define mmMMEA2_PERFCOUNTER0_CFG 0x05fe +#define mmMMEA2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMMEA2_PERFCOUNTER1_CFG 0x05ff +#define mmMMEA2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMMEA2_PERFCOUNTER_RSLT_CNTL 0x0600 +#define mmMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmMMEA2_EDC_CNT 0x0606 +#define mmMMEA2_EDC_CNT_BASE_IDX 1 +#define mmMMEA2_EDC_CNT2 0x0607 +#define mmMMEA2_EDC_CNT2_BASE_IDX 1 +#define mmMMEA2_DSM_CNTL 0x0608 +#define mmMMEA2_DSM_CNTL_BASE_IDX 1 +#define mmMMEA2_DSM_CNTLA 0x0609 +#define mmMMEA2_DSM_CNTLA_BASE_IDX 1 +#define mmMMEA2_DSM_CNTLB 0x060a +#define mmMMEA2_DSM_CNTLB_BASE_IDX 1 +#define mmMMEA2_DSM_CNTL2 0x060b +#define mmMMEA2_DSM_CNTL2_BASE_IDX 1 +#define mmMMEA2_DSM_CNTL2A 0x060c +#define mmMMEA2_DSM_CNTL2A_BASE_IDX 1 +#define mmMMEA2_DSM_CNTL2B 0x060d +#define mmMMEA2_DSM_CNTL2B_BASE_IDX 1 +#define mmMMEA2_CGTT_CLK_CTRL 0x060f +#define mmMMEA2_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmMMEA2_EDC_MODE 0x0610 +#define mmMMEA2_EDC_MODE_BASE_IDX 1 +#define mmMMEA2_ERR_STATUS 0x0611 +#define mmMMEA2_ERR_STATUS_BASE_IDX 1 +#define mmMMEA2_MISC2 0x0612 +#define mmMMEA2_MISC2_BASE_IDX 1 +#define mmMMEA2_ADDRDEC_SELECT 0x0613 +#define mmMMEA2_ADDRDEC_SELECT_BASE_IDX 1 +#define mmMMEA2_EDC_CNT3 0x0614 +#define mmMMEA2_EDC_CNT3_BASE_IDX 1 + + +// addressBlock: mmhub_ea_mmeadec3 +// base address: 0x69900 +#define mmMMEA3_DRAM_RD_CLI2GRP_MAP0 0x0640 +#define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_CLI2GRP_MAP1 0x0641 +#define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_CLI2GRP_MAP0 0x0642 +#define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_CLI2GRP_MAP1 0x0643 +#define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_GRP2VC_MAP 0x0644 +#define mmMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_GRP2VC_MAP 0x0645 +#define mmMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_LAZY 0x0646 +#define mmMMEA3_DRAM_RD_LAZY_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_LAZY 0x0647 +#define mmMMEA3_DRAM_WR_LAZY_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_CAM_CNTL 0x0648 +#define mmMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_CAM_CNTL 0x0649 +#define mmMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA3_DRAM_PAGE_BURST 0x064a +#define mmMMEA3_DRAM_PAGE_BURST_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_PRI_AGE 0x064b +#define mmMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_PRI_AGE 0x064c +#define mmMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_PRI_QUEUING 0x064d +#define mmMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_PRI_QUEUING 0x064e +#define mmMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_PRI_FIXED 0x064f +#define mmMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_PRI_FIXED 0x0650 +#define mmMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_PRI_URGENCY 0x0651 +#define mmMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_PRI_URGENCY 0x0652 +#define mmMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x0653 +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x0654 +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x0655 +#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x0656 +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x0657 +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x0658 +#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA3_GMI_RD_CLI2GRP_MAP0 0x0659 +#define mmMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA3_GMI_RD_CLI2GRP_MAP1 0x065a +#define mmMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA3_GMI_WR_CLI2GRP_MAP0 0x065b +#define mmMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA3_GMI_WR_CLI2GRP_MAP1 0x065c +#define mmMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA3_GMI_RD_GRP2VC_MAP 0x065d +#define mmMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA3_GMI_WR_GRP2VC_MAP 0x065e +#define mmMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA3_GMI_RD_LAZY 0x065f +#define mmMMEA3_GMI_RD_LAZY_BASE_IDX 1 +#define mmMMEA3_GMI_WR_LAZY 0x0660 +#define mmMMEA3_GMI_WR_LAZY_BASE_IDX 1 +#define mmMMEA3_GMI_RD_CAM_CNTL 0x0661 +#define mmMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA3_GMI_WR_CAM_CNTL 0x0662 +#define mmMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA3_GMI_PAGE_BURST 0x0663 +#define mmMMEA3_GMI_PAGE_BURST_BASE_IDX 1 +#define mmMMEA3_GMI_RD_PRI_AGE 0x0664 +#define mmMMEA3_GMI_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA3_GMI_WR_PRI_AGE 0x0665 +#define mmMMEA3_GMI_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA3_GMI_RD_PRI_QUEUING 0x0666 +#define mmMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA3_GMI_WR_PRI_QUEUING 0x0667 +#define mmMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA3_GMI_RD_PRI_FIXED 0x0668 +#define mmMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA3_GMI_WR_PRI_FIXED 0x0669 +#define mmMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA3_GMI_RD_PRI_URGENCY 0x066a +#define mmMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA3_GMI_WR_PRI_URGENCY 0x066b +#define mmMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x066c +#define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x066d +#define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI1 0x066e +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI2 0x066f +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI3 0x0670 +#define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI1 0x0671 +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI2 0x0672 +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI3 0x0673 +#define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_BASE_ADDR0 0x0674 +#define mmMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR0 0x0675 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_BASE_ADDR1 0x0676 +#define mmMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR1 0x0677 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_OFFSET_ADDR1 0x0678 +#define mmMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_BASE_ADDR2 0x0679 +#define mmMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR2 0x067a +#define mmMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_BASE_ADDR3 0x067b +#define mmMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR3 0x067c +#define mmMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_OFFSET_ADDR3 0x067d +#define mmMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_BASE_ADDR4 0x067e +#define mmMMEA3_ADDRNORM_BASE_ADDR4_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR4 0x067f +#define mmMMEA3_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_BASE_ADDR5 0x0680 +#define mmMMEA3_ADDRNORM_BASE_ADDR5_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR5 0x0681 +#define mmMMEA3_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 +#define mmMMEA3_ADDRNORM_OFFSET_ADDR5 0x0682 +#define mmMMEA3_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 +#define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL 0x0683 +#define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA3_ADDRNORMGMI_HOLE_CNTL 0x0684 +#define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0685 +#define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0686 +#define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA3_ADDRDEC_BANK_CFG 0x0687 +#define mmMMEA3_ADDRDEC_BANK_CFG_BASE_IDX 1 +#define mmMMEA3_ADDRDEC_MISC_CFG 0x0688 +#define mmMMEA3_ADDRDEC_MISC_CFG_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0 0x0689 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1 0x068a +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2 0x068b +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3 0x068c +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4 0x068d +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5 0x068e +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC 0x068f +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2 0x0690 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0 0x0691 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1 0x0692 +#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0x0693 +#define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0 0x0694 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1 0x0695 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2 0x0696 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3 0x0697 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4 0x0698 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5 0x0699 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC 0x069a +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2 0x069b +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0 0x069c +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1 0x069d +#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE 0x069e +#define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0 0x069f +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1 0x06a0 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2 0x06a1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3 0x06a2 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0x06a3 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0x06a4 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0x06a5 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0x06a6 +#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01 0x06a7 +#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23 0x06a8 +#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0x06a9 +#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0x06aa +#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01 0x06ab +#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23 0x06ac +#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01 0x06ad +#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23 0x06ae +#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0x06af +#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0x06b0 +#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0x06b1 +#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0x06b2 +#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0x06b3 +#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0x06b4 +#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_RM_SEL_CS01 0x06b5 +#define mmMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_RM_SEL_CS23 0x06b6 +#define mmMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01 0x06b7 +#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23 0x06b8 +#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0 0x06b9 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1 0x06ba +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2 0x06bb +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3 0x06bc +#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0x06bd +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0x06be +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0x06bf +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0x06c0 +#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01 0x06c1 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23 0x06c2 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0x06c3 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0x06c4 +#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01 0x06c5 +#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23 0x06c6 +#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01 0x06c7 +#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23 0x06c8 +#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0x06c9 +#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0x06ca +#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0x06cb +#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0x06cc +#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0x06cd +#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0x06ce +#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_RM_SEL_CS01 0x06cf +#define mmMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_RM_SEL_CS23 0x06d0 +#define mmMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01 0x06d1 +#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23 0x06d2 +#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0 0x06d3 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1 0x06d4 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2 0x06d5 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3 0x06d6 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0x06d7 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0x06d8 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0x06d9 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0x06da +#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01 0x06db +#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23 0x06dc +#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0x06dd +#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0x06de +#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01 0x06df +#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23 0x06e0 +#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01 0x06e1 +#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23 0x06e2 +#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0x06e3 +#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0x06e4 +#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0x06e5 +#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0x06e6 +#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0x06e7 +#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0x06e8 +#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_RM_SEL_CS01 0x06e9 +#define mmMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_RM_SEL_CS23 0x06ea +#define mmMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01 0x06eb +#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23 0x06ec +#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0x06ed +#define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0x06ee +#define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA3_IO_RD_CLI2GRP_MAP0 0x0715 +#define mmMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA3_IO_RD_CLI2GRP_MAP1 0x0716 +#define mmMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA3_IO_WR_CLI2GRP_MAP0 0x0717 +#define mmMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA3_IO_WR_CLI2GRP_MAP1 0x0718 +#define mmMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA3_IO_RD_COMBINE_FLUSH 0x0719 +#define mmMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA3_IO_WR_COMBINE_FLUSH 0x071a +#define mmMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA3_IO_GROUP_BURST 0x071b +#define mmMMEA3_IO_GROUP_BURST_BASE_IDX 1 +#define mmMMEA3_IO_RD_PRI_AGE 0x071c +#define mmMMEA3_IO_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA3_IO_WR_PRI_AGE 0x071d +#define mmMMEA3_IO_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA3_IO_RD_PRI_QUEUING 0x071e +#define mmMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA3_IO_WR_PRI_QUEUING 0x071f +#define mmMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA3_IO_RD_PRI_FIXED 0x0720 +#define mmMMEA3_IO_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA3_IO_WR_PRI_FIXED 0x0721 +#define mmMMEA3_IO_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA3_IO_RD_PRI_URGENCY 0x0722 +#define mmMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA3_IO_WR_PRI_URGENCY 0x0723 +#define mmMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA3_IO_RD_PRI_URGENCY_MASKING 0x0724 +#define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA3_IO_WR_PRI_URGENCY_MASKING 0x0725 +#define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA3_IO_RD_PRI_QUANT_PRI1 0x0726 +#define mmMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA3_IO_RD_PRI_QUANT_PRI2 0x0727 +#define mmMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA3_IO_RD_PRI_QUANT_PRI3 0x0728 +#define mmMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA3_IO_WR_PRI_QUANT_PRI1 0x0729 +#define mmMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA3_IO_WR_PRI_QUANT_PRI2 0x072a +#define mmMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA3_IO_WR_PRI_QUANT_PRI3 0x072b +#define mmMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA3_SDP_ARB_DRAM 0x072c +#define mmMMEA3_SDP_ARB_DRAM_BASE_IDX 1 +#define mmMMEA3_SDP_ARB_GMI 0x072d +#define mmMMEA3_SDP_ARB_GMI_BASE_IDX 1 +#define mmMMEA3_SDP_ARB_FINAL 0x072e +#define mmMMEA3_SDP_ARB_FINAL_BASE_IDX 1 +#define mmMMEA3_SDP_DRAM_PRIORITY 0x072f +#define mmMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 1 +#define mmMMEA3_SDP_GMI_PRIORITY 0x0730 +#define mmMMEA3_SDP_GMI_PRIORITY_BASE_IDX 1 +#define mmMMEA3_SDP_IO_PRIORITY 0x0731 +#define mmMMEA3_SDP_IO_PRIORITY_BASE_IDX 1 +#define mmMMEA3_SDP_CREDITS 0x0732 +#define mmMMEA3_SDP_CREDITS_BASE_IDX 1 +#define mmMMEA3_SDP_TAG_RESERVE0 0x0733 +#define mmMMEA3_SDP_TAG_RESERVE0_BASE_IDX 1 +#define mmMMEA3_SDP_TAG_RESERVE1 0x0734 +#define mmMMEA3_SDP_TAG_RESERVE1_BASE_IDX 1 +#define mmMMEA3_SDP_VCC_RESERVE0 0x0735 +#define mmMMEA3_SDP_VCC_RESERVE0_BASE_IDX 1 +#define mmMMEA3_SDP_VCC_RESERVE1 0x0736 +#define mmMMEA3_SDP_VCC_RESERVE1_BASE_IDX 1 +#define mmMMEA3_SDP_VCD_RESERVE0 0x0737 +#define mmMMEA3_SDP_VCD_RESERVE0_BASE_IDX 1 +#define mmMMEA3_SDP_VCD_RESERVE1 0x0738 +#define mmMMEA3_SDP_VCD_RESERVE1_BASE_IDX 1 +#define mmMMEA3_SDP_REQ_CNTL 0x0739 +#define mmMMEA3_SDP_REQ_CNTL_BASE_IDX 1 +#define mmMMEA3_MISC 0x073a +#define mmMMEA3_MISC_BASE_IDX 1 +#define mmMMEA3_LATENCY_SAMPLING 0x073b +#define mmMMEA3_LATENCY_SAMPLING_BASE_IDX 1 +#define mmMMEA3_PERFCOUNTER_LO 0x073c +#define mmMMEA3_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMMEA3_PERFCOUNTER_HI 0x073d +#define mmMMEA3_PERFCOUNTER_HI_BASE_IDX 1 +#define mmMMEA3_PERFCOUNTER0_CFG 0x073e +#define mmMMEA3_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMMEA3_PERFCOUNTER1_CFG 0x073f +#define mmMMEA3_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMMEA3_PERFCOUNTER_RSLT_CNTL 0x0740 +#define mmMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmMMEA3_EDC_CNT 0x0746 +#define mmMMEA3_EDC_CNT_BASE_IDX 1 +#define mmMMEA3_EDC_CNT2 0x0747 +#define mmMMEA3_EDC_CNT2_BASE_IDX 1 +#define mmMMEA3_DSM_CNTL 0x0748 +#define mmMMEA3_DSM_CNTL_BASE_IDX 1 +#define mmMMEA3_DSM_CNTLA 0x0749 +#define mmMMEA3_DSM_CNTLA_BASE_IDX 1 +#define mmMMEA3_DSM_CNTLB 0x074a +#define mmMMEA3_DSM_CNTLB_BASE_IDX 1 +#define mmMMEA3_DSM_CNTL2 0x074b +#define mmMMEA3_DSM_CNTL2_BASE_IDX 1 +#define mmMMEA3_DSM_CNTL2A 0x074c +#define mmMMEA3_DSM_CNTL2A_BASE_IDX 1 +#define mmMMEA3_DSM_CNTL2B 0x074d +#define mmMMEA3_DSM_CNTL2B_BASE_IDX 1 +#define mmMMEA3_CGTT_CLK_CTRL 0x074f +#define mmMMEA3_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmMMEA3_EDC_MODE 0x0750 +#define mmMMEA3_EDC_MODE_BASE_IDX 1 +#define mmMMEA3_ERR_STATUS 0x0751 +#define mmMMEA3_ERR_STATUS_BASE_IDX 1 +#define mmMMEA3_MISC2 0x0752 +#define mmMMEA3_MISC2_BASE_IDX 1 +#define mmMMEA3_ADDRDEC_SELECT 0x0753 +#define mmMMEA3_ADDRDEC_SELECT_BASE_IDX 1 +#define mmMMEA3_EDC_CNT3 0x0754 +#define mmMMEA3_EDC_CNT3_BASE_IDX 1 + + +// addressBlock: mmhub_ea_mmeadec4 +// base address: 0x69e00 +#define mmMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0780 +#define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0781 +#define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0782 +#define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0783 +#define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_GRP2VC_MAP 0x0784 +#define mmMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_GRP2VC_MAP 0x0785 +#define mmMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_LAZY 0x0786 +#define mmMMEA4_DRAM_RD_LAZY_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_LAZY 0x0787 +#define mmMMEA4_DRAM_WR_LAZY_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_CAM_CNTL 0x0788 +#define mmMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_CAM_CNTL 0x0789 +#define mmMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA4_DRAM_PAGE_BURST 0x078a +#define mmMMEA4_DRAM_PAGE_BURST_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_PRI_AGE 0x078b +#define mmMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_PRI_AGE 0x078c +#define mmMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_PRI_QUEUING 0x078d +#define mmMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_PRI_QUEUING 0x078e +#define mmMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_PRI_FIXED 0x078f +#define mmMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_PRI_FIXED 0x0790 +#define mmMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_PRI_URGENCY 0x0791 +#define mmMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_PRI_URGENCY 0x0792 +#define mmMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0793 +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0794 +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0795 +#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0796 +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0797 +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0798 +#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA4_GMI_RD_CLI2GRP_MAP0 0x0799 +#define mmMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA4_GMI_RD_CLI2GRP_MAP1 0x079a +#define mmMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA4_GMI_WR_CLI2GRP_MAP0 0x079b +#define mmMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA4_GMI_WR_CLI2GRP_MAP1 0x079c +#define mmMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA4_GMI_RD_GRP2VC_MAP 0x079d +#define mmMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA4_GMI_WR_GRP2VC_MAP 0x079e +#define mmMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA4_GMI_RD_LAZY 0x079f +#define mmMMEA4_GMI_RD_LAZY_BASE_IDX 1 +#define mmMMEA4_GMI_WR_LAZY 0x07a0 +#define mmMMEA4_GMI_WR_LAZY_BASE_IDX 1 +#define mmMMEA4_GMI_RD_CAM_CNTL 0x07a1 +#define mmMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA4_GMI_WR_CAM_CNTL 0x07a2 +#define mmMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA4_GMI_PAGE_BURST 0x07a3 +#define mmMMEA4_GMI_PAGE_BURST_BASE_IDX 1 +#define mmMMEA4_GMI_RD_PRI_AGE 0x07a4 +#define mmMMEA4_GMI_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA4_GMI_WR_PRI_AGE 0x07a5 +#define mmMMEA4_GMI_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA4_GMI_RD_PRI_QUEUING 0x07a6 +#define mmMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA4_GMI_WR_PRI_QUEUING 0x07a7 +#define mmMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA4_GMI_RD_PRI_FIXED 0x07a8 +#define mmMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA4_GMI_WR_PRI_FIXED 0x07a9 +#define mmMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA4_GMI_RD_PRI_URGENCY 0x07aa +#define mmMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA4_GMI_WR_PRI_URGENCY 0x07ab +#define mmMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x07ac +#define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x07ad +#define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI1 0x07ae +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI2 0x07af +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI3 0x07b0 +#define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI1 0x07b1 +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI2 0x07b2 +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI3 0x07b3 +#define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_BASE_ADDR0 0x07b4 +#define mmMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR0 0x07b5 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_BASE_ADDR1 0x07b6 +#define mmMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR1 0x07b7 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_OFFSET_ADDR1 0x07b8 +#define mmMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_BASE_ADDR2 0x07b9 +#define mmMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR2 0x07ba +#define mmMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_BASE_ADDR3 0x07bb +#define mmMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR3 0x07bc +#define mmMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_OFFSET_ADDR3 0x07bd +#define mmMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_BASE_ADDR4 0x07be +#define mmMMEA4_ADDRNORM_BASE_ADDR4_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR4 0x07bf +#define mmMMEA4_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_BASE_ADDR5 0x07c0 +#define mmMMEA4_ADDRNORM_BASE_ADDR5_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR5 0x07c1 +#define mmMMEA4_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 +#define mmMMEA4_ADDRNORM_OFFSET_ADDR5 0x07c2 +#define mmMMEA4_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 +#define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL 0x07c3 +#define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA4_ADDRNORMGMI_HOLE_CNTL 0x07c4 +#define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x07c5 +#define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0x07c6 +#define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA4_ADDRDEC_BANK_CFG 0x07c7 +#define mmMMEA4_ADDRDEC_BANK_CFG_BASE_IDX 1 +#define mmMMEA4_ADDRDEC_MISC_CFG 0x07c8 +#define mmMMEA4_ADDRDEC_MISC_CFG_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0 0x07c9 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1 0x07ca +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2 0x07cb +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3 0x07cc +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4 0x07cd +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5 0x07ce +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC 0x07cf +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2 0x07d0 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0 0x07d1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1 0x07d2 +#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0x07d3 +#define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0 0x07d4 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1 0x07d5 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2 0x07d6 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3 0x07d7 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4 0x07d8 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5 0x07d9 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC 0x07da +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2 0x07db +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0 0x07dc +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1 0x07dd +#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE 0x07de +#define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0 0x07df +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1 0x07e0 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2 0x07e1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3 0x07e2 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0x07e3 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0x07e4 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0x07e5 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0x07e6 +#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01 0x07e7 +#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23 0x07e8 +#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0x07e9 +#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0x07ea +#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01 0x07eb +#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23 0x07ec +#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01 0x07ed +#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23 0x07ee +#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0x07ef +#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0x07f0 +#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0x07f1 +#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0x07f2 +#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0x07f3 +#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0x07f4 +#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_RM_SEL_CS01 0x07f5 +#define mmMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_RM_SEL_CS23 0x07f6 +#define mmMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01 0x07f7 +#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23 0x07f8 +#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0 0x07f9 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1 0x07fa +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2 0x07fb +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3 0x07fc +#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0x07fd +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0x07fe +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0x07ff +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0x0800 +#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01 0x0801 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23 0x0802 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0x0803 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0x0804 +#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01 0x0805 +#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23 0x0806 +#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01 0x0807 +#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23 0x0808 +#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0x0809 +#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0x080a +#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0x080b +#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0x080c +#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0x080d +#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0x080e +#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_RM_SEL_CS01 0x080f +#define mmMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_RM_SEL_CS23 0x0810 +#define mmMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01 0x0811 +#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23 0x0812 +#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0 0x0813 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1 0x0814 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2 0x0815 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3 0x0816 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0x0817 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0x0818 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0x0819 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0x081a +#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01 0x081b +#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23 0x081c +#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0x081d +#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0x081e +#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01 0x081f +#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23 0x0820 +#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01 0x0821 +#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23 0x0822 +#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0x0823 +#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0x0824 +#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0x0825 +#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0x0826 +#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0x0827 +#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0x0828 +#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_RM_SEL_CS01 0x0829 +#define mmMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_RM_SEL_CS23 0x082a +#define mmMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01 0x082b +#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23 0x082c +#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0x082d +#define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0x082e +#define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA4_IO_RD_CLI2GRP_MAP0 0x0855 +#define mmMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA4_IO_RD_CLI2GRP_MAP1 0x0856 +#define mmMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA4_IO_WR_CLI2GRP_MAP0 0x0857 +#define mmMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA4_IO_WR_CLI2GRP_MAP1 0x0858 +#define mmMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA4_IO_RD_COMBINE_FLUSH 0x0859 +#define mmMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA4_IO_WR_COMBINE_FLUSH 0x085a +#define mmMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA4_IO_GROUP_BURST 0x085b +#define mmMMEA4_IO_GROUP_BURST_BASE_IDX 1 +#define mmMMEA4_IO_RD_PRI_AGE 0x085c +#define mmMMEA4_IO_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA4_IO_WR_PRI_AGE 0x085d +#define mmMMEA4_IO_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA4_IO_RD_PRI_QUEUING 0x085e +#define mmMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA4_IO_WR_PRI_QUEUING 0x085f +#define mmMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA4_IO_RD_PRI_FIXED 0x0860 +#define mmMMEA4_IO_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA4_IO_WR_PRI_FIXED 0x0861 +#define mmMMEA4_IO_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA4_IO_RD_PRI_URGENCY 0x0862 +#define mmMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA4_IO_WR_PRI_URGENCY 0x0863 +#define mmMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA4_IO_RD_PRI_URGENCY_MASKING 0x0864 +#define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA4_IO_WR_PRI_URGENCY_MASKING 0x0865 +#define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA4_IO_RD_PRI_QUANT_PRI1 0x0866 +#define mmMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA4_IO_RD_PRI_QUANT_PRI2 0x0867 +#define mmMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA4_IO_RD_PRI_QUANT_PRI3 0x0868 +#define mmMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA4_IO_WR_PRI_QUANT_PRI1 0x0869 +#define mmMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA4_IO_WR_PRI_QUANT_PRI2 0x086a +#define mmMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA4_IO_WR_PRI_QUANT_PRI3 0x086b +#define mmMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA4_SDP_ARB_DRAM 0x086c +#define mmMMEA4_SDP_ARB_DRAM_BASE_IDX 1 +#define mmMMEA4_SDP_ARB_GMI 0x086d +#define mmMMEA4_SDP_ARB_GMI_BASE_IDX 1 +#define mmMMEA4_SDP_ARB_FINAL 0x086e +#define mmMMEA4_SDP_ARB_FINAL_BASE_IDX 1 +#define mmMMEA4_SDP_DRAM_PRIORITY 0x086f +#define mmMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 1 +#define mmMMEA4_SDP_GMI_PRIORITY 0x0870 +#define mmMMEA4_SDP_GMI_PRIORITY_BASE_IDX 1 +#define mmMMEA4_SDP_IO_PRIORITY 0x0871 +#define mmMMEA4_SDP_IO_PRIORITY_BASE_IDX 1 +#define mmMMEA4_SDP_CREDITS 0x0872 +#define mmMMEA4_SDP_CREDITS_BASE_IDX 1 +#define mmMMEA4_SDP_TAG_RESERVE0 0x0873 +#define mmMMEA4_SDP_TAG_RESERVE0_BASE_IDX 1 +#define mmMMEA4_SDP_TAG_RESERVE1 0x0874 +#define mmMMEA4_SDP_TAG_RESERVE1_BASE_IDX 1 +#define mmMMEA4_SDP_VCC_RESERVE0 0x0875 +#define mmMMEA4_SDP_VCC_RESERVE0_BASE_IDX 1 +#define mmMMEA4_SDP_VCC_RESERVE1 0x0876 +#define mmMMEA4_SDP_VCC_RESERVE1_BASE_IDX 1 +#define mmMMEA4_SDP_VCD_RESERVE0 0x0877 +#define mmMMEA4_SDP_VCD_RESERVE0_BASE_IDX 1 +#define mmMMEA4_SDP_VCD_RESERVE1 0x0878 +#define mmMMEA4_SDP_VCD_RESERVE1_BASE_IDX 1 +#define mmMMEA4_SDP_REQ_CNTL 0x0879 +#define mmMMEA4_SDP_REQ_CNTL_BASE_IDX 1 +#define mmMMEA4_MISC 0x087a +#define mmMMEA4_MISC_BASE_IDX 1 +#define mmMMEA4_LATENCY_SAMPLING 0x087b +#define mmMMEA4_LATENCY_SAMPLING_BASE_IDX 1 +#define mmMMEA4_PERFCOUNTER_LO 0x087c +#define mmMMEA4_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMMEA4_PERFCOUNTER_HI 0x087d +#define mmMMEA4_PERFCOUNTER_HI_BASE_IDX 1 +#define mmMMEA4_PERFCOUNTER0_CFG 0x087e +#define mmMMEA4_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMMEA4_PERFCOUNTER1_CFG 0x087f +#define mmMMEA4_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMMEA4_PERFCOUNTER_RSLT_CNTL 0x0880 +#define mmMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmMMEA4_EDC_CNT 0x0886 +#define mmMMEA4_EDC_CNT_BASE_IDX 1 +#define mmMMEA4_EDC_CNT2 0x0887 +#define mmMMEA4_EDC_CNT2_BASE_IDX 1 +#define mmMMEA4_DSM_CNTL 0x0888 +#define mmMMEA4_DSM_CNTL_BASE_IDX 1 +#define mmMMEA4_DSM_CNTLA 0x0889 +#define mmMMEA4_DSM_CNTLA_BASE_IDX 1 +#define mmMMEA4_DSM_CNTLB 0x088a +#define mmMMEA4_DSM_CNTLB_BASE_IDX 1 +#define mmMMEA4_DSM_CNTL2 0x088b +#define mmMMEA4_DSM_CNTL2_BASE_IDX 1 +#define mmMMEA4_DSM_CNTL2A 0x088c +#define mmMMEA4_DSM_CNTL2A_BASE_IDX 1 +#define mmMMEA4_DSM_CNTL2B 0x088d +#define mmMMEA4_DSM_CNTL2B_BASE_IDX 1 +#define mmMMEA4_CGTT_CLK_CTRL 0x088f +#define mmMMEA4_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmMMEA4_EDC_MODE 0x0890 +#define mmMMEA4_EDC_MODE_BASE_IDX 1 +#define mmMMEA4_ERR_STATUS 0x0891 +#define mmMMEA4_ERR_STATUS_BASE_IDX 1 +#define mmMMEA4_MISC2 0x0892 +#define mmMMEA4_MISC2_BASE_IDX 1 +#define mmMMEA4_ADDRDEC_SELECT 0x0893 +#define mmMMEA4_ADDRDEC_SELECT_BASE_IDX 1 +#define mmMMEA4_EDC_CNT3 0x0894 +#define mmMMEA4_EDC_CNT3_BASE_IDX 1 + + +// addressBlock: mmhub_pctldec0 +// base address: 0x6a300 +#define mmPCTL0_CTRL 0x08c0 +#define mmPCTL0_CTRL_BASE_IDX 1 +#define mmPCTL0_MMHUB_DEEPSLEEP_IB 0x08c1 +#define mmPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 +#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x08c2 +#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 +#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x08c3 +#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 +#define mmPCTL0_PG_IGNORE_DEEPSLEEP 0x08c4 +#define mmPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 +#define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x08c5 +#define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 +#define mmPCTL0_SLICE0_CFG_DAGB_BUSY 0x08c6 +#define mmPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL0_SLICE0_CFG_DS_ALLOW 0x08c7 +#define mmPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x08c8 +#define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL0_SLICE1_CFG_DAGB_BUSY 0x08c9 +#define mmPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL0_SLICE1_CFG_DS_ALLOW 0x08ca +#define mmPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x08cb +#define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL0_SLICE2_CFG_DAGB_BUSY 0x08cc +#define mmPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL0_SLICE2_CFG_DS_ALLOW 0x08cd +#define mmPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x08ce +#define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL0_SLICE3_CFG_DAGB_BUSY 0x08cf +#define mmPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL0_SLICE3_CFG_DS_ALLOW 0x08d0 +#define mmPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x08d1 +#define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL0_SLICE4_CFG_DAGB_BUSY 0x08d2 +#define mmPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL0_SLICE4_CFG_DS_ALLOW 0x08d3 +#define mmPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x08d4 +#define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL0_UTCL2_MISC 0x08d5 +#define mmPCTL0_UTCL2_MISC_BASE_IDX 1 +#define mmPCTL0_SLICE0_MISC 0x08d6 +#define mmPCTL0_SLICE0_MISC_BASE_IDX 1 +#define mmPCTL0_SLICE1_MISC 0x08d7 +#define mmPCTL0_SLICE1_MISC_BASE_IDX 1 +#define mmPCTL0_SLICE2_MISC 0x08d8 +#define mmPCTL0_SLICE2_MISC_BASE_IDX 1 +#define mmPCTL0_SLICE3_MISC 0x08d9 +#define mmPCTL0_SLICE3_MISC_BASE_IDX 1 +#define mmPCTL0_SLICE4_MISC 0x08da +#define mmPCTL0_SLICE4_MISC_BASE_IDX 1 +#define mmPCTL0_UTCL2_RENG_EXECUTE 0x08db +#define mmPCTL0_UTCL2_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL0_SLICE0_RENG_EXECUTE 0x08dc +#define mmPCTL0_SLICE0_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL0_SLICE1_RENG_EXECUTE 0x08dd +#define mmPCTL0_SLICE1_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL0_SLICE2_RENG_EXECUTE 0x08de +#define mmPCTL0_SLICE2_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL0_SLICE3_RENG_EXECUTE 0x08df +#define mmPCTL0_SLICE3_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL0_SLICE4_RENG_EXECUTE 0x08e0 +#define mmPCTL0_SLICE4_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL0_UTCL2_RENG_RAM_INDEX 0x08e1 +#define mmPCTL0_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL0_UTCL2_RENG_RAM_DATA 0x08e2 +#define mmPCTL0_UTCL2_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL0_SLICE0_RENG_RAM_INDEX 0x08e3 +#define mmPCTL0_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL0_SLICE0_RENG_RAM_DATA 0x08e4 +#define mmPCTL0_SLICE0_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL0_SLICE1_RENG_RAM_INDEX 0x08e5 +#define mmPCTL0_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL0_SLICE1_RENG_RAM_DATA 0x08e6 +#define mmPCTL0_SLICE1_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL0_SLICE2_RENG_RAM_INDEX 0x08e7 +#define mmPCTL0_SLICE2_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL0_SLICE2_RENG_RAM_DATA 0x08e8 +#define mmPCTL0_SLICE2_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL0_SLICE3_RENG_RAM_INDEX 0x08e9 +#define mmPCTL0_SLICE3_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL0_SLICE3_RENG_RAM_DATA 0x08ea +#define mmPCTL0_SLICE3_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL0_SLICE4_RENG_RAM_INDEX 0x08eb +#define mmPCTL0_SLICE4_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL0_SLICE4_RENG_RAM_DATA 0x08ec +#define mmPCTL0_SLICE4_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x08ed +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x08ee +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x08ef +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x08f0 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x08f1 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x08f2 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x08f3 +#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x08f4 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x08f5 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x08f6 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x08f7 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x08f8 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x08f9 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x08fa +#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x08fb +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x08fc +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x08fd +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x08fe +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x08ff +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0900 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0901 +#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0x0902 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0x0903 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0x0904 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0x0905 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0x0906 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0907 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0908 +#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0x0909 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0x090a +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0x090b +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0x090c +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0x090d +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0x090e +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0x090f +#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0x0910 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0x0911 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0x0912 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0x0913 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0x0914 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0915 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0916 +#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_vml1dec +// base address: 0x6a500 +#define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS 0x0948 +#define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 +#define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS 0x0949 +#define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 +#define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS 0x094a +#define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 +#define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS 0x094b +#define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 +#define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS 0x094c +#define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 +#define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS 0x094d +#define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 +#define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS 0x094e +#define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 +#define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS 0x094f +#define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_vml1pldec +// base address: 0x6a580 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG 0x0960 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG 0x0961 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG 0x0962 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG 0x0963 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0964 +#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_vml1prdec +// base address: 0x6a5c0 +#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO 0x0970 +#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 +#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI 0x0971 +#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_atcl2dec +// base address: 0x6a600 +#define mmATCL2_0_ATC_L2_CNTL 0x0980 +#define mmATCL2_0_ATC_L2_CNTL_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CNTL2 0x0981 +#define mmATCL2_0_ATC_L2_CNTL2_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CACHE_DATA0 0x0984 +#define mmATCL2_0_ATC_L2_CACHE_DATA0_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CACHE_DATA1 0x0985 +#define mmATCL2_0_ATC_L2_CACHE_DATA1_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CACHE_DATA2 0x0986 +#define mmATCL2_0_ATC_L2_CACHE_DATA2_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CNTL3 0x0987 +#define mmATCL2_0_ATC_L2_CNTL3_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_STATUS 0x0988 +#define mmATCL2_0_ATC_L2_STATUS_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_STATUS2 0x0989 +#define mmATCL2_0_ATC_L2_STATUS2_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_STATUS3 0x098a +#define mmATCL2_0_ATC_L2_STATUS3_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_MISC_CG 0x098b +#define mmATCL2_0_ATC_L2_MISC_CG_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_MEM_POWER_LS 0x098c +#define mmATCL2_0_ATC_L2_MEM_POWER_LS_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL 0x098d +#define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX 0x098e +#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX 0x098f +#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL 0x0990 +#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL 0x0991 +#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_CNTL4 0x0992 +#define mmATCL2_0_ATC_L2_CNTL4_BASE_IDX 1 +#define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES 0x0993 +#define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vml2pfdec +// base address: 0x6a700 +#define mmVML2PF0_VM_L2_CNTL 0x09c0 +#define mmVML2PF0_VM_L2_CNTL_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CNTL2 0x09c1 +#define mmVML2PF0_VM_L2_CNTL2_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CNTL3 0x09c2 +#define mmVML2PF0_VM_L2_CNTL3_BASE_IDX 1 +#define mmVML2PF0_VM_L2_STATUS 0x09c3 +#define mmVML2PF0_VM_L2_STATUS_BASE_IDX 1 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL 0x09c4 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0x09c5 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0x09c6 +#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL 0x09c7 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2 0x09c8 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3 0x09c9 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4 0x09ca +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS 0x09cb +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32 0x09cc +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32 0x09cd +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x09ce +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x09cf +#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x09d1 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x09d2 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x09d3 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x09d4 +#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x09d5 +#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x09d6 +#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CNTL4 0x09d7 +#define mmVML2PF0_VM_L2_CNTL4_BASE_IDX 1 +#define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES 0x09d8 +#define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 +#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID 0x09d9 +#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 +#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2 0x09da +#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL 0x09db +#define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 +#define mmVML2PF0_VM_L2_CGTT_CLK_CTRL 0x09de +#define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vml2vcdec +// base address: 0x6a800 +#define mmVML2VC0_VM_CONTEXT0_CNTL 0x0a00 +#define mmVML2VC0_VM_CONTEXT0_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT1_CNTL 0x0a01 +#define mmVML2VC0_VM_CONTEXT1_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT2_CNTL 0x0a02 +#define mmVML2VC0_VM_CONTEXT2_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT3_CNTL 0x0a03 +#define mmVML2VC0_VM_CONTEXT3_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT4_CNTL 0x0a04 +#define mmVML2VC0_VM_CONTEXT4_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT5_CNTL 0x0a05 +#define mmVML2VC0_VM_CONTEXT5_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT6_CNTL 0x0a06 +#define mmVML2VC0_VM_CONTEXT6_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT7_CNTL 0x0a07 +#define mmVML2VC0_VM_CONTEXT7_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT8_CNTL 0x0a08 +#define mmVML2VC0_VM_CONTEXT8_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT9_CNTL 0x0a09 +#define mmVML2VC0_VM_CONTEXT9_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT10_CNTL 0x0a0a +#define mmVML2VC0_VM_CONTEXT10_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT11_CNTL 0x0a0b +#define mmVML2VC0_VM_CONTEXT11_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT12_CNTL 0x0a0c +#define mmVML2VC0_VM_CONTEXT12_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT13_CNTL 0x0a0d +#define mmVML2VC0_VM_CONTEXT13_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT14_CNTL 0x0a0e +#define mmVML2VC0_VM_CONTEXT14_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT15_CNTL 0x0a0f +#define mmVML2VC0_VM_CONTEXT15_CNTL_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXTS_DISABLE 0x0a10 +#define mmVML2VC0_VM_CONTEXTS_DISABLE_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG0_SEM 0x0a11 +#define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG1_SEM 0x0a12 +#define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG2_SEM 0x0a13 +#define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG3_SEM 0x0a14 +#define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG4_SEM 0x0a15 +#define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG5_SEM 0x0a16 +#define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG6_SEM 0x0a17 +#define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG7_SEM 0x0a18 +#define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG8_SEM 0x0a19 +#define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG9_SEM 0x0a1a +#define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG10_SEM 0x0a1b +#define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG11_SEM 0x0a1c +#define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG12_SEM 0x0a1d +#define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG13_SEM 0x0a1e +#define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG14_SEM 0x0a1f +#define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG15_SEM 0x0a20 +#define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG16_SEM 0x0a21 +#define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG17_SEM 0x0a22 +#define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG0_REQ 0x0a23 +#define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG1_REQ 0x0a24 +#define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG2_REQ 0x0a25 +#define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG3_REQ 0x0a26 +#define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG4_REQ 0x0a27 +#define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG5_REQ 0x0a28 +#define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG6_REQ 0x0a29 +#define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG7_REQ 0x0a2a +#define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG8_REQ 0x0a2b +#define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG9_REQ 0x0a2c +#define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG10_REQ 0x0a2d +#define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG11_REQ 0x0a2e +#define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG12_REQ 0x0a2f +#define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG13_REQ 0x0a30 +#define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG14_REQ 0x0a31 +#define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG15_REQ 0x0a32 +#define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG16_REQ 0x0a33 +#define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG17_REQ 0x0a34 +#define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ACK 0x0a35 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG1_ACK 0x0a36 +#define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG2_ACK 0x0a37 +#define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG3_ACK 0x0a38 +#define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG4_ACK 0x0a39 +#define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG5_ACK 0x0a3a +#define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG6_ACK 0x0a3b +#define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG7_ACK 0x0a3c +#define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG8_ACK 0x0a3d +#define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG9_ACK 0x0a3e +#define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG10_ACK 0x0a3f +#define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG11_ACK 0x0a40 +#define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG12_ACK 0x0a41 +#define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ACK 0x0a42 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ACK 0x0a43 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ACK 0x0a44 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ACK 0x0a45 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG17_ACK 0x0a46 +#define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0a47 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0a48 +#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0a49 +#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0a4a +#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0a4b +#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0a4c +#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0a4d +#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0a4e +#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0a4f +#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0a50 +#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0a51 +#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0a52 +#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0a53 +#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0a54 +#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0a55 +#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0a56 +#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0a57 +#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0a58 +#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0a59 +#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0a5a +#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0a5b +#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0a5c +#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0a5d +#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0a5e +#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0a5f +#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0a60 +#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0a61 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0a62 +#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0a63 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0a64 +#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0a65 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0a66 +#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0a67 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0a68 +#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0a69 +#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0a6a +#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0a6b +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0a6c +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0a6d +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0a6e +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0a6f +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0a70 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0a71 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0a72 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0a73 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0a74 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0a75 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0a76 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0a77 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0a78 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0a79 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0a7a +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0a7b +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0a7c +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0a7d +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0a7e +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0a7f +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0a80 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0a81 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0a82 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0a83 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0a84 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0a85 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0a86 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0a87 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0a88 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0a89 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0a8a +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0a8b +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0a8c +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0a8d +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0a8e +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0a8f +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0a90 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0a91 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0a92 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0a93 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0a94 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0a95 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0a96 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0a97 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0a98 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0a99 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0a9a +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0a9b +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0a9c +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0a9d +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0a9e +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0a9f +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0aa0 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0aa1 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0aa2 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0aa3 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0aa4 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0aa5 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0aa6 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0aa7 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0aa8 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0aa9 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0aaa +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0aab +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0aac +#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0aad +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0aae +#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0aaf +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0ab0 +#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0ab1 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0ab2 +#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0ab3 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0ab4 +#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0ab5 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0ab6 +#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0ab7 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0ab8 +#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0ab9 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0aba +#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0abb +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0abc +#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0abd +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0abe +#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0abf +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0ac0 +#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0ac1 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0ac2 +#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0ac3 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0ac4 +#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0ac5 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0ac6 +#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0ac7 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0ac8 +#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0ac9 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0aca +#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vmsharedpfdec +// base address: 0x6ab90 +#define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE 0x0ae4 +#define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT 0x0ae5 +#define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL 0x0ae6 +#define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB 0x0ae7 +#define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1 0x0ae8 +#define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2 0x0ae9 +#define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2 0x0aea +#define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_FB_OFFSET 0x0aeb +#define mmVMSHAREDPF0_MC_VM_FB_OFFSET_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0aec +#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0aed +#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_STEERING 0x0aee +#define mmVMSHAREDPF0_MC_VM_STEERING_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ 0x0aef +#define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_MEM_POWER_LS 0x0af0 +#define mmVMSHAREDPF0_MC_MEM_POWER_LS_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0af1 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0af2 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_APT_CNTL 0x0af3 +#define mmVMSHAREDPF0_MC_VM_APT_CNTL_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START 0x0af4 +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END 0x0af5 +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0af6 +#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL 0x0af7 +#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE 0x0af8 +#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL 0x0af9 +#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vmsharedvcdec +// base address: 0x6ac00 +#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE 0x0b00 +#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_BASE_IDX 1 +#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP 0x0b01 +#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_BASE_IDX 1 +#define mmVMSHAREDVC0_MC_VM_AGP_TOP 0x0b02 +#define mmVMSHAREDVC0_MC_VM_AGP_TOP_BASE_IDX 1 +#define mmVMSHAREDVC0_MC_VM_AGP_BOT 0x0b03 +#define mmVMSHAREDVC0_MC_VM_AGP_BOT_BASE_IDX 1 +#define mmVMSHAREDVC0_MC_VM_AGP_BASE 0x0b04 +#define mmVMSHAREDVC0_MC_VM_AGP_BASE_BASE_IDX 1 +#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0b05 +#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 +#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0b06 +#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 +#define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL 0x0b07 +#define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vmsharedhvdec +// base address: 0x6ac80 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0 0x0b20 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1 0x0b21 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2 0x0b22 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3 0x0b23 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4 0x0b24 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5 0x0b25 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6 0x0b26 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7 0x0b27 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8 0x0b28 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9 0x0b29 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10 0x0b2a +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11 0x0b2b +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12 0x0b2c +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13 0x0b2d +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14 0x0b2e +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15 0x0b2f +#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1 0x0b30 +#define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0 0x0b31 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1 0x0b32 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2 0x0b33 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3 0x0b34 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0 0x0b35 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1 0x0b36 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2 0x0b37 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3 0x0b38 +#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0 0x0b39 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1 0x0b3a +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2 0x0b3b +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3 0x0b3c +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0 0x0b3d +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1 0x0b3e +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2 0x0b3f +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3 0x0b40 +#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0 0x0b41 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1 0x0b42 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2 0x0b43 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3 0x0b44 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0 0x0b45 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1 0x0b46 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2 0x0b47 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3 0x0b48 +#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER 0x0b49 +#define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0b4a +#define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL 0x0b4b +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0 0x0b4c +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1 0x0b4d +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2 0x0b4e +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3 0x0b4f +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4 0x0b50 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5 0x0b51 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6 0x0b52 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7 0x0b53 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8 0x0b54 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9 0x0b55 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10 0x0b56 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11 0x0b57 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12 0x0b58 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13 0x0b59 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14 0x0b5a +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15 0x0b5b +#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 +#define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL 0x0b5c +#define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID 0x0b5d +#define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE 0x0b5e +#define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec +// base address: 0x6adc0 +#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO 0x0b70 +#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI 0x0b71 +#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec +// base address: 0x6add0 +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG 0x0b74 +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG 0x0b75 +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x0b76 +#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vml2pldec +// base address: 0x6ae00 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG 0x0b80 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG 0x0b81 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG 0x0b82 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG 0x0b83 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG 0x0b84 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG 0x0b85 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG 0x0b86 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG 0x0b87 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0b88 +#define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vml2prdec +// base address: 0x6ae40 +#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO 0x0b90 +#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI 0x0b91 +#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_dagb_dagbdec5 +// base address: 0x74000 +#define mmDAGB5_RDCLI0 0x3000 +#define mmDAGB5_RDCLI0_BASE_IDX 1 +#define mmDAGB5_RDCLI1 0x3001 +#define mmDAGB5_RDCLI1_BASE_IDX 1 +#define mmDAGB5_RDCLI2 0x3002 +#define mmDAGB5_RDCLI2_BASE_IDX 1 +#define mmDAGB5_RDCLI3 0x3003 +#define mmDAGB5_RDCLI3_BASE_IDX 1 +#define mmDAGB5_RDCLI4 0x3004 +#define mmDAGB5_RDCLI4_BASE_IDX 1 +#define mmDAGB5_RDCLI5 0x3005 +#define mmDAGB5_RDCLI5_BASE_IDX 1 +#define mmDAGB5_RDCLI6 0x3006 +#define mmDAGB5_RDCLI6_BASE_IDX 1 +#define mmDAGB5_RDCLI7 0x3007 +#define mmDAGB5_RDCLI7_BASE_IDX 1 +#define mmDAGB5_RDCLI8 0x3008 +#define mmDAGB5_RDCLI8_BASE_IDX 1 +#define mmDAGB5_RDCLI9 0x3009 +#define mmDAGB5_RDCLI9_BASE_IDX 1 +#define mmDAGB5_RDCLI10 0x300a +#define mmDAGB5_RDCLI10_BASE_IDX 1 +#define mmDAGB5_RDCLI11 0x300b +#define mmDAGB5_RDCLI11_BASE_IDX 1 +#define mmDAGB5_RDCLI12 0x300c +#define mmDAGB5_RDCLI12_BASE_IDX 1 +#define mmDAGB5_RDCLI13 0x300d +#define mmDAGB5_RDCLI13_BASE_IDX 1 +#define mmDAGB5_RDCLI14 0x300e +#define mmDAGB5_RDCLI14_BASE_IDX 1 +#define mmDAGB5_RDCLI15 0x300f +#define mmDAGB5_RDCLI15_BASE_IDX 1 +#define mmDAGB5_RD_CNTL 0x3010 +#define mmDAGB5_RD_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_GMI_CNTL 0x3011 +#define mmDAGB5_RD_GMI_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_ADDR_DAGB 0x3012 +#define mmDAGB5_RD_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x3013 +#define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x3014 +#define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB5_RD_CGTT_CLK_CTRL 0x3015 +#define mmDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x3016 +#define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x3017 +#define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x3018 +#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x3019 +#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x301a +#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x301b +#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB5_RD_VC0_CNTL 0x301c +#define mmDAGB5_RD_VC0_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_VC1_CNTL 0x301d +#define mmDAGB5_RD_VC1_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_VC2_CNTL 0x301e +#define mmDAGB5_RD_VC2_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_VC3_CNTL 0x301f +#define mmDAGB5_RD_VC3_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_VC4_CNTL 0x3020 +#define mmDAGB5_RD_VC4_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_VC5_CNTL 0x3021 +#define mmDAGB5_RD_VC5_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_VC6_CNTL 0x3022 +#define mmDAGB5_RD_VC6_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_VC7_CNTL 0x3023 +#define mmDAGB5_RD_VC7_CNTL_BASE_IDX 1 +#define mmDAGB5_RD_CNTL_MISC 0x3024 +#define mmDAGB5_RD_CNTL_MISC_BASE_IDX 1 +#define mmDAGB5_RD_TLB_CREDIT 0x3025 +#define mmDAGB5_RD_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB5_RDCLI_ASK_PENDING 0x3026 +#define mmDAGB5_RDCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB5_RDCLI_GO_PENDING 0x3027 +#define mmDAGB5_RDCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB5_RDCLI_GBLSEND_PENDING 0x3028 +#define mmDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB5_RDCLI_TLB_PENDING 0x3029 +#define mmDAGB5_RDCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB5_RDCLI_OARB_PENDING 0x302a +#define mmDAGB5_RDCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB5_RDCLI_OSD_PENDING 0x302b +#define mmDAGB5_RDCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB5_WRCLI0 0x302c +#define mmDAGB5_WRCLI0_BASE_IDX 1 +#define mmDAGB5_WRCLI1 0x302d +#define mmDAGB5_WRCLI1_BASE_IDX 1 +#define mmDAGB5_WRCLI2 0x302e +#define mmDAGB5_WRCLI2_BASE_IDX 1 +#define mmDAGB5_WRCLI3 0x302f +#define mmDAGB5_WRCLI3_BASE_IDX 1 +#define mmDAGB5_WRCLI4 0x3030 +#define mmDAGB5_WRCLI4_BASE_IDX 1 +#define mmDAGB5_WRCLI5 0x3031 +#define mmDAGB5_WRCLI5_BASE_IDX 1 +#define mmDAGB5_WRCLI6 0x3032 +#define mmDAGB5_WRCLI6_BASE_IDX 1 +#define mmDAGB5_WRCLI7 0x3033 +#define mmDAGB5_WRCLI7_BASE_IDX 1 +#define mmDAGB5_WRCLI8 0x3034 +#define mmDAGB5_WRCLI8_BASE_IDX 1 +#define mmDAGB5_WRCLI9 0x3035 +#define mmDAGB5_WRCLI9_BASE_IDX 1 +#define mmDAGB5_WRCLI10 0x3036 +#define mmDAGB5_WRCLI10_BASE_IDX 1 +#define mmDAGB5_WRCLI11 0x3037 +#define mmDAGB5_WRCLI11_BASE_IDX 1 +#define mmDAGB5_WRCLI12 0x3038 +#define mmDAGB5_WRCLI12_BASE_IDX 1 +#define mmDAGB5_WRCLI13 0x3039 +#define mmDAGB5_WRCLI13_BASE_IDX 1 +#define mmDAGB5_WRCLI14 0x303a +#define mmDAGB5_WRCLI14_BASE_IDX 1 +#define mmDAGB5_WRCLI15 0x303b +#define mmDAGB5_WRCLI15_BASE_IDX 1 +#define mmDAGB5_WR_CNTL 0x303c +#define mmDAGB5_WR_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_GMI_CNTL 0x303d +#define mmDAGB5_WR_GMI_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_ADDR_DAGB 0x303e +#define mmDAGB5_WR_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x303f +#define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x3040 +#define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB5_WR_CGTT_CLK_CTRL 0x3041 +#define mmDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x3042 +#define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x3043 +#define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x3044 +#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x3045 +#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x3046 +#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x3047 +#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB5_WR_DATA_DAGB 0x3048 +#define mmDAGB5_WR_DATA_DAGB_BASE_IDX 1 +#define mmDAGB5_WR_DATA_DAGB_MAX_BURST0 0x3049 +#define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x304a +#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB5_WR_DATA_DAGB_MAX_BURST1 0x304b +#define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x304c +#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB5_WR_VC0_CNTL 0x304d +#define mmDAGB5_WR_VC0_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_VC1_CNTL 0x304e +#define mmDAGB5_WR_VC1_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_VC2_CNTL 0x304f +#define mmDAGB5_WR_VC2_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_VC3_CNTL 0x3050 +#define mmDAGB5_WR_VC3_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_VC4_CNTL 0x3051 +#define mmDAGB5_WR_VC4_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_VC5_CNTL 0x3052 +#define mmDAGB5_WR_VC5_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_VC6_CNTL 0x3053 +#define mmDAGB5_WR_VC6_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_VC7_CNTL 0x3054 +#define mmDAGB5_WR_VC7_CNTL_BASE_IDX 1 +#define mmDAGB5_WR_CNTL_MISC 0x3055 +#define mmDAGB5_WR_CNTL_MISC_BASE_IDX 1 +#define mmDAGB5_WR_TLB_CREDIT 0x3056 +#define mmDAGB5_WR_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB5_WR_DATA_CREDIT 0x3057 +#define mmDAGB5_WR_DATA_CREDIT_BASE_IDX 1 +#define mmDAGB5_WR_MISC_CREDIT 0x3058 +#define mmDAGB5_WR_MISC_CREDIT_BASE_IDX 1 +#define mmDAGB5_WRCLI_ASK_PENDING 0x305d +#define mmDAGB5_WRCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB5_WRCLI_GO_PENDING 0x305e +#define mmDAGB5_WRCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB5_WRCLI_GBLSEND_PENDING 0x305f +#define mmDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB5_WRCLI_TLB_PENDING 0x3060 +#define mmDAGB5_WRCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB5_WRCLI_OARB_PENDING 0x3061 +#define mmDAGB5_WRCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB5_WRCLI_OSD_PENDING 0x3062 +#define mmDAGB5_WRCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB5_WRCLI_DBUS_ASK_PENDING 0x3063 +#define mmDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define mmDAGB5_WRCLI_DBUS_GO_PENDING 0x3064 +#define mmDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define mmDAGB5_DAGB_DLY 0x3065 +#define mmDAGB5_DAGB_DLY_BASE_IDX 1 +#define mmDAGB5_CNTL_MISC 0x3066 +#define mmDAGB5_CNTL_MISC_BASE_IDX 1 +#define mmDAGB5_CNTL_MISC2 0x3067 +#define mmDAGB5_CNTL_MISC2_BASE_IDX 1 +#define mmDAGB5_FIFO_EMPTY 0x3068 +#define mmDAGB5_FIFO_EMPTY_BASE_IDX 1 +#define mmDAGB5_FIFO_FULL 0x3069 +#define mmDAGB5_FIFO_FULL_BASE_IDX 1 +#define mmDAGB5_WR_CREDITS_FULL 0x306a +#define mmDAGB5_WR_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB5_RD_CREDITS_FULL 0x306b +#define mmDAGB5_RD_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB5_PERFCOUNTER_LO 0x306c +#define mmDAGB5_PERFCOUNTER_LO_BASE_IDX 1 +#define mmDAGB5_PERFCOUNTER_HI 0x306d +#define mmDAGB5_PERFCOUNTER_HI_BASE_IDX 1 +#define mmDAGB5_PERFCOUNTER0_CFG 0x306e +#define mmDAGB5_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmDAGB5_PERFCOUNTER1_CFG 0x306f +#define mmDAGB5_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmDAGB5_PERFCOUNTER2_CFG 0x3070 +#define mmDAGB5_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmDAGB5_PERFCOUNTER_RSLT_CNTL 0x3071 +#define mmDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmDAGB5_RESERVE0 0x3072 +#define mmDAGB5_RESERVE0_BASE_IDX 1 +#define mmDAGB5_RESERVE1 0x3073 +#define mmDAGB5_RESERVE1_BASE_IDX 1 +#define mmDAGB5_RESERVE2 0x3074 +#define mmDAGB5_RESERVE2_BASE_IDX 1 +#define mmDAGB5_RESERVE3 0x3075 +#define mmDAGB5_RESERVE3_BASE_IDX 1 +#define mmDAGB5_RESERVE4 0x3076 +#define mmDAGB5_RESERVE4_BASE_IDX 1 +#define mmDAGB5_RESERVE5 0x3077 +#define mmDAGB5_RESERVE5_BASE_IDX 1 +#define mmDAGB5_RESERVE6 0x3078 +#define mmDAGB5_RESERVE6_BASE_IDX 1 +#define mmDAGB5_RESERVE7 0x3079 +#define mmDAGB5_RESERVE7_BASE_IDX 1 +#define mmDAGB5_RESERVE8 0x307a +#define mmDAGB5_RESERVE8_BASE_IDX 1 +#define mmDAGB5_RESERVE9 0x307b +#define mmDAGB5_RESERVE9_BASE_IDX 1 +#define mmDAGB5_RESERVE10 0x307c +#define mmDAGB5_RESERVE10_BASE_IDX 1 +#define mmDAGB5_RESERVE11 0x307d +#define mmDAGB5_RESERVE11_BASE_IDX 1 +#define mmDAGB5_RESERVE12 0x307e +#define mmDAGB5_RESERVE12_BASE_IDX 1 +#define mmDAGB5_RESERVE13 0x307f +#define mmDAGB5_RESERVE13_BASE_IDX 1 + + +// addressBlock: mmhub_dagb_dagbdec6 +// base address: 0x74200 +#define mmDAGB6_RDCLI0 0x3080 +#define mmDAGB6_RDCLI0_BASE_IDX 1 +#define mmDAGB6_RDCLI1 0x3081 +#define mmDAGB6_RDCLI1_BASE_IDX 1 +#define mmDAGB6_RDCLI2 0x3082 +#define mmDAGB6_RDCLI2_BASE_IDX 1 +#define mmDAGB6_RDCLI3 0x3083 +#define mmDAGB6_RDCLI3_BASE_IDX 1 +#define mmDAGB6_RDCLI4 0x3084 +#define mmDAGB6_RDCLI4_BASE_IDX 1 +#define mmDAGB6_RDCLI5 0x3085 +#define mmDAGB6_RDCLI5_BASE_IDX 1 +#define mmDAGB6_RDCLI6 0x3086 +#define mmDAGB6_RDCLI6_BASE_IDX 1 +#define mmDAGB6_RDCLI7 0x3087 +#define mmDAGB6_RDCLI7_BASE_IDX 1 +#define mmDAGB6_RDCLI8 0x3088 +#define mmDAGB6_RDCLI8_BASE_IDX 1 +#define mmDAGB6_RDCLI9 0x3089 +#define mmDAGB6_RDCLI9_BASE_IDX 1 +#define mmDAGB6_RDCLI10 0x308a +#define mmDAGB6_RDCLI10_BASE_IDX 1 +#define mmDAGB6_RDCLI11 0x308b +#define mmDAGB6_RDCLI11_BASE_IDX 1 +#define mmDAGB6_RDCLI12 0x308c +#define mmDAGB6_RDCLI12_BASE_IDX 1 +#define mmDAGB6_RDCLI13 0x308d +#define mmDAGB6_RDCLI13_BASE_IDX 1 +#define mmDAGB6_RDCLI14 0x308e +#define mmDAGB6_RDCLI14_BASE_IDX 1 +#define mmDAGB6_RDCLI15 0x308f +#define mmDAGB6_RDCLI15_BASE_IDX 1 +#define mmDAGB6_RD_CNTL 0x3090 +#define mmDAGB6_RD_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_GMI_CNTL 0x3091 +#define mmDAGB6_RD_GMI_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_ADDR_DAGB 0x3092 +#define mmDAGB6_RD_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST 0x3093 +#define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER 0x3094 +#define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB6_RD_CGTT_CLK_CTRL 0x3095 +#define mmDAGB6_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL 0x3096 +#define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL 0x3097 +#define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0 0x3098 +#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0 0x3099 +#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1 0x309a +#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1 0x309b +#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB6_RD_VC0_CNTL 0x309c +#define mmDAGB6_RD_VC0_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_VC1_CNTL 0x309d +#define mmDAGB6_RD_VC1_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_VC2_CNTL 0x309e +#define mmDAGB6_RD_VC2_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_VC3_CNTL 0x309f +#define mmDAGB6_RD_VC3_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_VC4_CNTL 0x30a0 +#define mmDAGB6_RD_VC4_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_VC5_CNTL 0x30a1 +#define mmDAGB6_RD_VC5_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_VC6_CNTL 0x30a2 +#define mmDAGB6_RD_VC6_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_VC7_CNTL 0x30a3 +#define mmDAGB6_RD_VC7_CNTL_BASE_IDX 1 +#define mmDAGB6_RD_CNTL_MISC 0x30a4 +#define mmDAGB6_RD_CNTL_MISC_BASE_IDX 1 +#define mmDAGB6_RD_TLB_CREDIT 0x30a5 +#define mmDAGB6_RD_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB6_RDCLI_ASK_PENDING 0x30a6 +#define mmDAGB6_RDCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB6_RDCLI_GO_PENDING 0x30a7 +#define mmDAGB6_RDCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB6_RDCLI_GBLSEND_PENDING 0x30a8 +#define mmDAGB6_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB6_RDCLI_TLB_PENDING 0x30a9 +#define mmDAGB6_RDCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB6_RDCLI_OARB_PENDING 0x30aa +#define mmDAGB6_RDCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB6_RDCLI_OSD_PENDING 0x30ab +#define mmDAGB6_RDCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB6_WRCLI0 0x30ac +#define mmDAGB6_WRCLI0_BASE_IDX 1 +#define mmDAGB6_WRCLI1 0x30ad +#define mmDAGB6_WRCLI1_BASE_IDX 1 +#define mmDAGB6_WRCLI2 0x30ae +#define mmDAGB6_WRCLI2_BASE_IDX 1 +#define mmDAGB6_WRCLI3 0x30af +#define mmDAGB6_WRCLI3_BASE_IDX 1 +#define mmDAGB6_WRCLI4 0x30b0 +#define mmDAGB6_WRCLI4_BASE_IDX 1 +#define mmDAGB6_WRCLI5 0x30b1 +#define mmDAGB6_WRCLI5_BASE_IDX 1 +#define mmDAGB6_WRCLI6 0x30b2 +#define mmDAGB6_WRCLI6_BASE_IDX 1 +#define mmDAGB6_WRCLI7 0x30b3 +#define mmDAGB6_WRCLI7_BASE_IDX 1 +#define mmDAGB6_WRCLI8 0x30b4 +#define mmDAGB6_WRCLI8_BASE_IDX 1 +#define mmDAGB6_WRCLI9 0x30b5 +#define mmDAGB6_WRCLI9_BASE_IDX 1 +#define mmDAGB6_WRCLI10 0x30b6 +#define mmDAGB6_WRCLI10_BASE_IDX 1 +#define mmDAGB6_WRCLI11 0x30b7 +#define mmDAGB6_WRCLI11_BASE_IDX 1 +#define mmDAGB6_WRCLI12 0x30b8 +#define mmDAGB6_WRCLI12_BASE_IDX 1 +#define mmDAGB6_WRCLI13 0x30b9 +#define mmDAGB6_WRCLI13_BASE_IDX 1 +#define mmDAGB6_WRCLI14 0x30ba +#define mmDAGB6_WRCLI14_BASE_IDX 1 +#define mmDAGB6_WRCLI15 0x30bb +#define mmDAGB6_WRCLI15_BASE_IDX 1 +#define mmDAGB6_WR_CNTL 0x30bc +#define mmDAGB6_WR_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_GMI_CNTL 0x30bd +#define mmDAGB6_WR_GMI_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_ADDR_DAGB 0x30be +#define mmDAGB6_WR_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST 0x30bf +#define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER 0x30c0 +#define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB6_WR_CGTT_CLK_CTRL 0x30c1 +#define mmDAGB6_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL 0x30c2 +#define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL 0x30c3 +#define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0 0x30c4 +#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0 0x30c5 +#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1 0x30c6 +#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1 0x30c7 +#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB6_WR_DATA_DAGB 0x30c8 +#define mmDAGB6_WR_DATA_DAGB_BASE_IDX 1 +#define mmDAGB6_WR_DATA_DAGB_MAX_BURST0 0x30c9 +#define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0 0x30ca +#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB6_WR_DATA_DAGB_MAX_BURST1 0x30cb +#define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1 0x30cc +#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB6_WR_VC0_CNTL 0x30cd +#define mmDAGB6_WR_VC0_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_VC1_CNTL 0x30ce +#define mmDAGB6_WR_VC1_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_VC2_CNTL 0x30cf +#define mmDAGB6_WR_VC2_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_VC3_CNTL 0x30d0 +#define mmDAGB6_WR_VC3_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_VC4_CNTL 0x30d1 +#define mmDAGB6_WR_VC4_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_VC5_CNTL 0x30d2 +#define mmDAGB6_WR_VC5_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_VC6_CNTL 0x30d3 +#define mmDAGB6_WR_VC6_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_VC7_CNTL 0x30d4 +#define mmDAGB6_WR_VC7_CNTL_BASE_IDX 1 +#define mmDAGB6_WR_CNTL_MISC 0x30d5 +#define mmDAGB6_WR_CNTL_MISC_BASE_IDX 1 +#define mmDAGB6_WR_TLB_CREDIT 0x30d6 +#define mmDAGB6_WR_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB6_WR_DATA_CREDIT 0x30d7 +#define mmDAGB6_WR_DATA_CREDIT_BASE_IDX 1 +#define mmDAGB6_WR_MISC_CREDIT 0x30d8 +#define mmDAGB6_WR_MISC_CREDIT_BASE_IDX 1 +#define mmDAGB6_WRCLI_ASK_PENDING 0x30dd +#define mmDAGB6_WRCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB6_WRCLI_GO_PENDING 0x30de +#define mmDAGB6_WRCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB6_WRCLI_GBLSEND_PENDING 0x30df +#define mmDAGB6_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB6_WRCLI_TLB_PENDING 0x30e0 +#define mmDAGB6_WRCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB6_WRCLI_OARB_PENDING 0x30e1 +#define mmDAGB6_WRCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB6_WRCLI_OSD_PENDING 0x30e2 +#define mmDAGB6_WRCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB6_WRCLI_DBUS_ASK_PENDING 0x30e3 +#define mmDAGB6_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define mmDAGB6_WRCLI_DBUS_GO_PENDING 0x30e4 +#define mmDAGB6_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define mmDAGB6_DAGB_DLY 0x30e5 +#define mmDAGB6_DAGB_DLY_BASE_IDX 1 +#define mmDAGB6_CNTL_MISC 0x30e6 +#define mmDAGB6_CNTL_MISC_BASE_IDX 1 +#define mmDAGB6_CNTL_MISC2 0x30e7 +#define mmDAGB6_CNTL_MISC2_BASE_IDX 1 +#define mmDAGB6_FIFO_EMPTY 0x30e8 +#define mmDAGB6_FIFO_EMPTY_BASE_IDX 1 +#define mmDAGB6_FIFO_FULL 0x30e9 +#define mmDAGB6_FIFO_FULL_BASE_IDX 1 +#define mmDAGB6_WR_CREDITS_FULL 0x30ea +#define mmDAGB6_WR_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB6_RD_CREDITS_FULL 0x30eb +#define mmDAGB6_RD_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB6_PERFCOUNTER_LO 0x30ec +#define mmDAGB6_PERFCOUNTER_LO_BASE_IDX 1 +#define mmDAGB6_PERFCOUNTER_HI 0x30ed +#define mmDAGB6_PERFCOUNTER_HI_BASE_IDX 1 +#define mmDAGB6_PERFCOUNTER0_CFG 0x30ee +#define mmDAGB6_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmDAGB6_PERFCOUNTER1_CFG 0x30ef +#define mmDAGB6_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmDAGB6_PERFCOUNTER2_CFG 0x30f0 +#define mmDAGB6_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmDAGB6_PERFCOUNTER_RSLT_CNTL 0x30f1 +#define mmDAGB6_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmDAGB6_RESERVE0 0x30f2 +#define mmDAGB6_RESERVE0_BASE_IDX 1 +#define mmDAGB6_RESERVE1 0x30f3 +#define mmDAGB6_RESERVE1_BASE_IDX 1 +#define mmDAGB6_RESERVE2 0x30f4 +#define mmDAGB6_RESERVE2_BASE_IDX 1 +#define mmDAGB6_RESERVE3 0x30f5 +#define mmDAGB6_RESERVE3_BASE_IDX 1 +#define mmDAGB6_RESERVE4 0x30f6 +#define mmDAGB6_RESERVE4_BASE_IDX 1 +#define mmDAGB6_RESERVE5 0x30f7 +#define mmDAGB6_RESERVE5_BASE_IDX 1 +#define mmDAGB6_RESERVE6 0x30f8 +#define mmDAGB6_RESERVE6_BASE_IDX 1 +#define mmDAGB6_RESERVE7 0x30f9 +#define mmDAGB6_RESERVE7_BASE_IDX 1 +#define mmDAGB6_RESERVE8 0x30fa +#define mmDAGB6_RESERVE8_BASE_IDX 1 +#define mmDAGB6_RESERVE9 0x30fb +#define mmDAGB6_RESERVE9_BASE_IDX 1 +#define mmDAGB6_RESERVE10 0x30fc +#define mmDAGB6_RESERVE10_BASE_IDX 1 +#define mmDAGB6_RESERVE11 0x30fd +#define mmDAGB6_RESERVE11_BASE_IDX 1 +#define mmDAGB6_RESERVE12 0x30fe +#define mmDAGB6_RESERVE12_BASE_IDX 1 +#define mmDAGB6_RESERVE13 0x30ff +#define mmDAGB6_RESERVE13_BASE_IDX 1 + + +// addressBlock: mmhub_dagb_dagbdec7 +// base address: 0x74400 +#define mmDAGB7_RDCLI0 0x3100 +#define mmDAGB7_RDCLI0_BASE_IDX 1 +#define mmDAGB7_RDCLI1 0x3101 +#define mmDAGB7_RDCLI1_BASE_IDX 1 +#define mmDAGB7_RDCLI2 0x3102 +#define mmDAGB7_RDCLI2_BASE_IDX 1 +#define mmDAGB7_RDCLI3 0x3103 +#define mmDAGB7_RDCLI3_BASE_IDX 1 +#define mmDAGB7_RDCLI4 0x3104 +#define mmDAGB7_RDCLI4_BASE_IDX 1 +#define mmDAGB7_RDCLI5 0x3105 +#define mmDAGB7_RDCLI5_BASE_IDX 1 +#define mmDAGB7_RDCLI6 0x3106 +#define mmDAGB7_RDCLI6_BASE_IDX 1 +#define mmDAGB7_RDCLI7 0x3107 +#define mmDAGB7_RDCLI7_BASE_IDX 1 +#define mmDAGB7_RDCLI8 0x3108 +#define mmDAGB7_RDCLI8_BASE_IDX 1 +#define mmDAGB7_RDCLI9 0x3109 +#define mmDAGB7_RDCLI9_BASE_IDX 1 +#define mmDAGB7_RDCLI10 0x310a +#define mmDAGB7_RDCLI10_BASE_IDX 1 +#define mmDAGB7_RDCLI11 0x310b +#define mmDAGB7_RDCLI11_BASE_IDX 1 +#define mmDAGB7_RDCLI12 0x310c +#define mmDAGB7_RDCLI12_BASE_IDX 1 +#define mmDAGB7_RDCLI13 0x310d +#define mmDAGB7_RDCLI13_BASE_IDX 1 +#define mmDAGB7_RDCLI14 0x310e +#define mmDAGB7_RDCLI14_BASE_IDX 1 +#define mmDAGB7_RDCLI15 0x310f +#define mmDAGB7_RDCLI15_BASE_IDX 1 +#define mmDAGB7_RD_CNTL 0x3110 +#define mmDAGB7_RD_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_GMI_CNTL 0x3111 +#define mmDAGB7_RD_GMI_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_ADDR_DAGB 0x3112 +#define mmDAGB7_RD_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST 0x3113 +#define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER 0x3114 +#define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB7_RD_CGTT_CLK_CTRL 0x3115 +#define mmDAGB7_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL 0x3116 +#define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL 0x3117 +#define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0 0x3118 +#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0 0x3119 +#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1 0x311a +#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1 0x311b +#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB7_RD_VC0_CNTL 0x311c +#define mmDAGB7_RD_VC0_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_VC1_CNTL 0x311d +#define mmDAGB7_RD_VC1_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_VC2_CNTL 0x311e +#define mmDAGB7_RD_VC2_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_VC3_CNTL 0x311f +#define mmDAGB7_RD_VC3_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_VC4_CNTL 0x3120 +#define mmDAGB7_RD_VC4_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_VC5_CNTL 0x3121 +#define mmDAGB7_RD_VC5_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_VC6_CNTL 0x3122 +#define mmDAGB7_RD_VC6_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_VC7_CNTL 0x3123 +#define mmDAGB7_RD_VC7_CNTL_BASE_IDX 1 +#define mmDAGB7_RD_CNTL_MISC 0x3124 +#define mmDAGB7_RD_CNTL_MISC_BASE_IDX 1 +#define mmDAGB7_RD_TLB_CREDIT 0x3125 +#define mmDAGB7_RD_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB7_RDCLI_ASK_PENDING 0x3126 +#define mmDAGB7_RDCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB7_RDCLI_GO_PENDING 0x3127 +#define mmDAGB7_RDCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB7_RDCLI_GBLSEND_PENDING 0x3128 +#define mmDAGB7_RDCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB7_RDCLI_TLB_PENDING 0x3129 +#define mmDAGB7_RDCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB7_RDCLI_OARB_PENDING 0x312a +#define mmDAGB7_RDCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB7_RDCLI_OSD_PENDING 0x312b +#define mmDAGB7_RDCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB7_WRCLI0 0x312c +#define mmDAGB7_WRCLI0_BASE_IDX 1 +#define mmDAGB7_WRCLI1 0x312d +#define mmDAGB7_WRCLI1_BASE_IDX 1 +#define mmDAGB7_WRCLI2 0x312e +#define mmDAGB7_WRCLI2_BASE_IDX 1 +#define mmDAGB7_WRCLI3 0x312f +#define mmDAGB7_WRCLI3_BASE_IDX 1 +#define mmDAGB7_WRCLI4 0x3130 +#define mmDAGB7_WRCLI4_BASE_IDX 1 +#define mmDAGB7_WRCLI5 0x3131 +#define mmDAGB7_WRCLI5_BASE_IDX 1 +#define mmDAGB7_WRCLI6 0x3132 +#define mmDAGB7_WRCLI6_BASE_IDX 1 +#define mmDAGB7_WRCLI7 0x3133 +#define mmDAGB7_WRCLI7_BASE_IDX 1 +#define mmDAGB7_WRCLI8 0x3134 +#define mmDAGB7_WRCLI8_BASE_IDX 1 +#define mmDAGB7_WRCLI9 0x3135 +#define mmDAGB7_WRCLI9_BASE_IDX 1 +#define mmDAGB7_WRCLI10 0x3136 +#define mmDAGB7_WRCLI10_BASE_IDX 1 +#define mmDAGB7_WRCLI11 0x3137 +#define mmDAGB7_WRCLI11_BASE_IDX 1 +#define mmDAGB7_WRCLI12 0x3138 +#define mmDAGB7_WRCLI12_BASE_IDX 1 +#define mmDAGB7_WRCLI13 0x3139 +#define mmDAGB7_WRCLI13_BASE_IDX 1 +#define mmDAGB7_WRCLI14 0x313a +#define mmDAGB7_WRCLI14_BASE_IDX 1 +#define mmDAGB7_WRCLI15 0x313b +#define mmDAGB7_WRCLI15_BASE_IDX 1 +#define mmDAGB7_WR_CNTL 0x313c +#define mmDAGB7_WR_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_GMI_CNTL 0x313d +#define mmDAGB7_WR_GMI_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_ADDR_DAGB 0x313e +#define mmDAGB7_WR_ADDR_DAGB_BASE_IDX 1 +#define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST 0x313f +#define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1 +#define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER 0x3140 +#define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1 +#define mmDAGB7_WR_CGTT_CLK_CTRL 0x3141 +#define mmDAGB7_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL 0x3142 +#define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL 0x3143 +#define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0 0x3144 +#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0 0x3145 +#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1 0x3146 +#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1 0x3147 +#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB7_WR_DATA_DAGB 0x3148 +#define mmDAGB7_WR_DATA_DAGB_BASE_IDX 1 +#define mmDAGB7_WR_DATA_DAGB_MAX_BURST0 0x3149 +#define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 +#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0 0x314a +#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 +#define mmDAGB7_WR_DATA_DAGB_MAX_BURST1 0x314b +#define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 +#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1 0x314c +#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 +#define mmDAGB7_WR_VC0_CNTL 0x314d +#define mmDAGB7_WR_VC0_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_VC1_CNTL 0x314e +#define mmDAGB7_WR_VC1_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_VC2_CNTL 0x314f +#define mmDAGB7_WR_VC2_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_VC3_CNTL 0x3150 +#define mmDAGB7_WR_VC3_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_VC4_CNTL 0x3151 +#define mmDAGB7_WR_VC4_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_VC5_CNTL 0x3152 +#define mmDAGB7_WR_VC5_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_VC6_CNTL 0x3153 +#define mmDAGB7_WR_VC6_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_VC7_CNTL 0x3154 +#define mmDAGB7_WR_VC7_CNTL_BASE_IDX 1 +#define mmDAGB7_WR_CNTL_MISC 0x3155 +#define mmDAGB7_WR_CNTL_MISC_BASE_IDX 1 +#define mmDAGB7_WR_TLB_CREDIT 0x3156 +#define mmDAGB7_WR_TLB_CREDIT_BASE_IDX 1 +#define mmDAGB7_WR_DATA_CREDIT 0x3157 +#define mmDAGB7_WR_DATA_CREDIT_BASE_IDX 1 +#define mmDAGB7_WR_MISC_CREDIT 0x3158 +#define mmDAGB7_WR_MISC_CREDIT_BASE_IDX 1 +#define mmDAGB7_WRCLI_ASK_PENDING 0x315d +#define mmDAGB7_WRCLI_ASK_PENDING_BASE_IDX 1 +#define mmDAGB7_WRCLI_GO_PENDING 0x315e +#define mmDAGB7_WRCLI_GO_PENDING_BASE_IDX 1 +#define mmDAGB7_WRCLI_GBLSEND_PENDING 0x315f +#define mmDAGB7_WRCLI_GBLSEND_PENDING_BASE_IDX 1 +#define mmDAGB7_WRCLI_TLB_PENDING 0x3160 +#define mmDAGB7_WRCLI_TLB_PENDING_BASE_IDX 1 +#define mmDAGB7_WRCLI_OARB_PENDING 0x3161 +#define mmDAGB7_WRCLI_OARB_PENDING_BASE_IDX 1 +#define mmDAGB7_WRCLI_OSD_PENDING 0x3162 +#define mmDAGB7_WRCLI_OSD_PENDING_BASE_IDX 1 +#define mmDAGB7_WRCLI_DBUS_ASK_PENDING 0x3163 +#define mmDAGB7_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 +#define mmDAGB7_WRCLI_DBUS_GO_PENDING 0x3164 +#define mmDAGB7_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 +#define mmDAGB7_DAGB_DLY 0x3165 +#define mmDAGB7_DAGB_DLY_BASE_IDX 1 +#define mmDAGB7_CNTL_MISC 0x3166 +#define mmDAGB7_CNTL_MISC_BASE_IDX 1 +#define mmDAGB7_CNTL_MISC2 0x3167 +#define mmDAGB7_CNTL_MISC2_BASE_IDX 1 +#define mmDAGB7_FIFO_EMPTY 0x3168 +#define mmDAGB7_FIFO_EMPTY_BASE_IDX 1 +#define mmDAGB7_FIFO_FULL 0x3169 +#define mmDAGB7_FIFO_FULL_BASE_IDX 1 +#define mmDAGB7_WR_CREDITS_FULL 0x316a +#define mmDAGB7_WR_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB7_RD_CREDITS_FULL 0x316b +#define mmDAGB7_RD_CREDITS_FULL_BASE_IDX 1 +#define mmDAGB7_PERFCOUNTER_LO 0x316c +#define mmDAGB7_PERFCOUNTER_LO_BASE_IDX 1 +#define mmDAGB7_PERFCOUNTER_HI 0x316d +#define mmDAGB7_PERFCOUNTER_HI_BASE_IDX 1 +#define mmDAGB7_PERFCOUNTER0_CFG 0x316e +#define mmDAGB7_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmDAGB7_PERFCOUNTER1_CFG 0x316f +#define mmDAGB7_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmDAGB7_PERFCOUNTER2_CFG 0x3170 +#define mmDAGB7_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmDAGB7_PERFCOUNTER_RSLT_CNTL 0x3171 +#define mmDAGB7_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmDAGB7_RESERVE0 0x3172 +#define mmDAGB7_RESERVE0_BASE_IDX 1 +#define mmDAGB7_RESERVE1 0x3173 +#define mmDAGB7_RESERVE1_BASE_IDX 1 +#define mmDAGB7_RESERVE2 0x3174 +#define mmDAGB7_RESERVE2_BASE_IDX 1 +#define mmDAGB7_RESERVE3 0x3175 +#define mmDAGB7_RESERVE3_BASE_IDX 1 +#define mmDAGB7_RESERVE4 0x3176 +#define mmDAGB7_RESERVE4_BASE_IDX 1 +#define mmDAGB7_RESERVE5 0x3177 +#define mmDAGB7_RESERVE5_BASE_IDX 1 +#define mmDAGB7_RESERVE6 0x3178 +#define mmDAGB7_RESERVE6_BASE_IDX 1 +#define mmDAGB7_RESERVE7 0x3179 +#define mmDAGB7_RESERVE7_BASE_IDX 1 +#define mmDAGB7_RESERVE8 0x317a +#define mmDAGB7_RESERVE8_BASE_IDX 1 +#define mmDAGB7_RESERVE9 0x317b +#define mmDAGB7_RESERVE9_BASE_IDX 1 +#define mmDAGB7_RESERVE10 0x317c +#define mmDAGB7_RESERVE10_BASE_IDX 1 +#define mmDAGB7_RESERVE11 0x317d +#define mmDAGB7_RESERVE11_BASE_IDX 1 +#define mmDAGB7_RESERVE12 0x317e +#define mmDAGB7_RESERVE12_BASE_IDX 1 +#define mmDAGB7_RESERVE13 0x317f +#define mmDAGB7_RESERVE13_BASE_IDX 1 + + +// addressBlock: mmhub_ea_mmeadec5 +// base address: 0x74a00 +#define mmMMEA5_DRAM_RD_CLI2GRP_MAP0 0x3280 +#define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_CLI2GRP_MAP1 0x3281 +#define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_CLI2GRP_MAP0 0x3282 +#define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_CLI2GRP_MAP1 0x3283 +#define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_GRP2VC_MAP 0x3284 +#define mmMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_GRP2VC_MAP 0x3285 +#define mmMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_LAZY 0x3286 +#define mmMMEA5_DRAM_RD_LAZY_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_LAZY 0x3287 +#define mmMMEA5_DRAM_WR_LAZY_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_CAM_CNTL 0x3288 +#define mmMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_CAM_CNTL 0x3289 +#define mmMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA5_DRAM_PAGE_BURST 0x328a +#define mmMMEA5_DRAM_PAGE_BURST_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_PRI_AGE 0x328b +#define mmMMEA5_DRAM_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_PRI_AGE 0x328c +#define mmMMEA5_DRAM_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_PRI_QUEUING 0x328d +#define mmMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_PRI_QUEUING 0x328e +#define mmMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_PRI_FIXED 0x328f +#define mmMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_PRI_FIXED 0x3290 +#define mmMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_PRI_URGENCY 0x3291 +#define mmMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_PRI_URGENCY 0x3292 +#define mmMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1 0x3293 +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2 0x3294 +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3 0x3295 +#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1 0x3296 +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2 0x3297 +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3 0x3298 +#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA5_GMI_RD_CLI2GRP_MAP0 0x3299 +#define mmMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA5_GMI_RD_CLI2GRP_MAP1 0x329a +#define mmMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA5_GMI_WR_CLI2GRP_MAP0 0x329b +#define mmMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA5_GMI_WR_CLI2GRP_MAP1 0x329c +#define mmMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA5_GMI_RD_GRP2VC_MAP 0x329d +#define mmMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA5_GMI_WR_GRP2VC_MAP 0x329e +#define mmMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA5_GMI_RD_LAZY 0x329f +#define mmMMEA5_GMI_RD_LAZY_BASE_IDX 1 +#define mmMMEA5_GMI_WR_LAZY 0x32a0 +#define mmMMEA5_GMI_WR_LAZY_BASE_IDX 1 +#define mmMMEA5_GMI_RD_CAM_CNTL 0x32a1 +#define mmMMEA5_GMI_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA5_GMI_WR_CAM_CNTL 0x32a2 +#define mmMMEA5_GMI_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA5_GMI_PAGE_BURST 0x32a3 +#define mmMMEA5_GMI_PAGE_BURST_BASE_IDX 1 +#define mmMMEA5_GMI_RD_PRI_AGE 0x32a4 +#define mmMMEA5_GMI_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA5_GMI_WR_PRI_AGE 0x32a5 +#define mmMMEA5_GMI_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA5_GMI_RD_PRI_QUEUING 0x32a6 +#define mmMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA5_GMI_WR_PRI_QUEUING 0x32a7 +#define mmMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA5_GMI_RD_PRI_FIXED 0x32a8 +#define mmMMEA5_GMI_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA5_GMI_WR_PRI_FIXED 0x32a9 +#define mmMMEA5_GMI_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA5_GMI_RD_PRI_URGENCY 0x32aa +#define mmMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA5_GMI_WR_PRI_URGENCY 0x32ab +#define mmMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING 0x32ac +#define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING 0x32ad +#define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI1 0x32ae +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI2 0x32af +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI3 0x32b0 +#define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI1 0x32b1 +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI2 0x32b2 +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI3 0x32b3 +#define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_BASE_ADDR0 0x32b4 +#define mmMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR0 0x32b5 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_BASE_ADDR1 0x32b6 +#define mmMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR1 0x32b7 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_OFFSET_ADDR1 0x32b8 +#define mmMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_BASE_ADDR2 0x32b9 +#define mmMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR2 0x32ba +#define mmMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_BASE_ADDR3 0x32bb +#define mmMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR3 0x32bc +#define mmMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_OFFSET_ADDR3 0x32bd +#define mmMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_BASE_ADDR4 0x32be +#define mmMMEA5_ADDRNORM_BASE_ADDR4_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR4 0x32bf +#define mmMMEA5_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_BASE_ADDR5 0x32c0 +#define mmMMEA5_ADDRNORM_BASE_ADDR5_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR5 0x32c1 +#define mmMMEA5_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 +#define mmMMEA5_ADDRNORM_OFFSET_ADDR5 0x32c2 +#define mmMMEA5_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 +#define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL 0x32c3 +#define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA5_ADDRNORMGMI_HOLE_CNTL 0x32c4 +#define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x32c5 +#define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0x32c6 +#define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA5_ADDRDEC_BANK_CFG 0x32c7 +#define mmMMEA5_ADDRDEC_BANK_CFG_BASE_IDX 1 +#define mmMMEA5_ADDRDEC_MISC_CFG 0x32c8 +#define mmMMEA5_ADDRDEC_MISC_CFG_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0 0x32c9 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1 0x32ca +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2 0x32cb +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3 0x32cc +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4 0x32cd +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5 0x32ce +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC 0x32cf +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2 0x32d0 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0 0x32d1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1 0x32d2 +#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0x32d3 +#define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0 0x32d4 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1 0x32d5 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2 0x32d6 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3 0x32d7 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4 0x32d8 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5 0x32d9 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC 0x32da +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2 0x32db +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0 0x32dc +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1 0x32dd +#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE 0x32de +#define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0 0x32df +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1 0x32e0 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2 0x32e1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3 0x32e2 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0x32e3 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0x32e4 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0x32e5 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0x32e6 +#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01 0x32e7 +#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23 0x32e8 +#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0x32e9 +#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0x32ea +#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01 0x32eb +#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23 0x32ec +#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01 0x32ed +#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23 0x32ee +#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0x32ef +#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0x32f0 +#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0x32f1 +#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0x32f2 +#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0x32f3 +#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0x32f4 +#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_RM_SEL_CS01 0x32f5 +#define mmMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_RM_SEL_CS23 0x32f6 +#define mmMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01 0x32f7 +#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23 0x32f8 +#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0 0x32f9 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1 0x32fa +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2 0x32fb +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3 0x32fc +#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0x32fd +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0x32fe +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0x32ff +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0x3300 +#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01 0x3301 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23 0x3302 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0x3303 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0x3304 +#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01 0x3305 +#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23 0x3306 +#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01 0x3307 +#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23 0x3308 +#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0x3309 +#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0x330a +#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0x330b +#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0x330c +#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0x330d +#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0x330e +#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_RM_SEL_CS01 0x330f +#define mmMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_RM_SEL_CS23 0x3310 +#define mmMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01 0x3311 +#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23 0x3312 +#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0 0x3313 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1 0x3314 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2 0x3315 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3 0x3316 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0x3317 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0x3318 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0x3319 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0x331a +#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01 0x331b +#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23 0x331c +#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0x331d +#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0x331e +#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01 0x331f +#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23 0x3320 +#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01 0x3321 +#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23 0x3322 +#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0x3323 +#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0x3324 +#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0x3325 +#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0x3326 +#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0x3327 +#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0x3328 +#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_RM_SEL_CS01 0x3329 +#define mmMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_RM_SEL_CS23 0x332a +#define mmMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01 0x332b +#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23 0x332c +#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0x332d +#define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0x332e +#define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA5_IO_RD_CLI2GRP_MAP0 0x3355 +#define mmMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA5_IO_RD_CLI2GRP_MAP1 0x3356 +#define mmMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA5_IO_WR_CLI2GRP_MAP0 0x3357 +#define mmMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA5_IO_WR_CLI2GRP_MAP1 0x3358 +#define mmMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA5_IO_RD_COMBINE_FLUSH 0x3359 +#define mmMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA5_IO_WR_COMBINE_FLUSH 0x335a +#define mmMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA5_IO_GROUP_BURST 0x335b +#define mmMMEA5_IO_GROUP_BURST_BASE_IDX 1 +#define mmMMEA5_IO_RD_PRI_AGE 0x335c +#define mmMMEA5_IO_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA5_IO_WR_PRI_AGE 0x335d +#define mmMMEA5_IO_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA5_IO_RD_PRI_QUEUING 0x335e +#define mmMMEA5_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA5_IO_WR_PRI_QUEUING 0x335f +#define mmMMEA5_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA5_IO_RD_PRI_FIXED 0x3360 +#define mmMMEA5_IO_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA5_IO_WR_PRI_FIXED 0x3361 +#define mmMMEA5_IO_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA5_IO_RD_PRI_URGENCY 0x3362 +#define mmMMEA5_IO_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA5_IO_WR_PRI_URGENCY 0x3363 +#define mmMMEA5_IO_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA5_IO_RD_PRI_URGENCY_MASKING 0x3364 +#define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA5_IO_WR_PRI_URGENCY_MASKING 0x3365 +#define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA5_IO_RD_PRI_QUANT_PRI1 0x3366 +#define mmMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA5_IO_RD_PRI_QUANT_PRI2 0x3367 +#define mmMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA5_IO_RD_PRI_QUANT_PRI3 0x3368 +#define mmMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA5_IO_WR_PRI_QUANT_PRI1 0x3369 +#define mmMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA5_IO_WR_PRI_QUANT_PRI2 0x336a +#define mmMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA5_IO_WR_PRI_QUANT_PRI3 0x336b +#define mmMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA5_SDP_ARB_DRAM 0x336c +#define mmMMEA5_SDP_ARB_DRAM_BASE_IDX 1 +#define mmMMEA5_SDP_ARB_GMI 0x336d +#define mmMMEA5_SDP_ARB_GMI_BASE_IDX 1 +#define mmMMEA5_SDP_ARB_FINAL 0x336e +#define mmMMEA5_SDP_ARB_FINAL_BASE_IDX 1 +#define mmMMEA5_SDP_DRAM_PRIORITY 0x336f +#define mmMMEA5_SDP_DRAM_PRIORITY_BASE_IDX 1 +#define mmMMEA5_SDP_GMI_PRIORITY 0x3370 +#define mmMMEA5_SDP_GMI_PRIORITY_BASE_IDX 1 +#define mmMMEA5_SDP_IO_PRIORITY 0x3371 +#define mmMMEA5_SDP_IO_PRIORITY_BASE_IDX 1 +#define mmMMEA5_SDP_CREDITS 0x3372 +#define mmMMEA5_SDP_CREDITS_BASE_IDX 1 +#define mmMMEA5_SDP_TAG_RESERVE0 0x3373 +#define mmMMEA5_SDP_TAG_RESERVE0_BASE_IDX 1 +#define mmMMEA5_SDP_TAG_RESERVE1 0x3374 +#define mmMMEA5_SDP_TAG_RESERVE1_BASE_IDX 1 +#define mmMMEA5_SDP_VCC_RESERVE0 0x3375 +#define mmMMEA5_SDP_VCC_RESERVE0_BASE_IDX 1 +#define mmMMEA5_SDP_VCC_RESERVE1 0x3376 +#define mmMMEA5_SDP_VCC_RESERVE1_BASE_IDX 1 +#define mmMMEA5_SDP_VCD_RESERVE0 0x3377 +#define mmMMEA5_SDP_VCD_RESERVE0_BASE_IDX 1 +#define mmMMEA5_SDP_VCD_RESERVE1 0x3378 +#define mmMMEA5_SDP_VCD_RESERVE1_BASE_IDX 1 +#define mmMMEA5_SDP_REQ_CNTL 0x3379 +#define mmMMEA5_SDP_REQ_CNTL_BASE_IDX 1 +#define mmMMEA5_MISC 0x337a +#define mmMMEA5_MISC_BASE_IDX 1 +#define mmMMEA5_LATENCY_SAMPLING 0x337b +#define mmMMEA5_LATENCY_SAMPLING_BASE_IDX 1 +#define mmMMEA5_PERFCOUNTER_LO 0x337c +#define mmMMEA5_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMMEA5_PERFCOUNTER_HI 0x337d +#define mmMMEA5_PERFCOUNTER_HI_BASE_IDX 1 +#define mmMMEA5_PERFCOUNTER0_CFG 0x337e +#define mmMMEA5_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMMEA5_PERFCOUNTER1_CFG 0x337f +#define mmMMEA5_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMMEA5_PERFCOUNTER_RSLT_CNTL 0x3380 +#define mmMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmMMEA5_EDC_CNT 0x3386 +#define mmMMEA5_EDC_CNT_BASE_IDX 1 +#define mmMMEA5_EDC_CNT2 0x3387 +#define mmMMEA5_EDC_CNT2_BASE_IDX 1 +#define mmMMEA5_DSM_CNTL 0x3388 +#define mmMMEA5_DSM_CNTL_BASE_IDX 1 +#define mmMMEA5_DSM_CNTLA 0x3389 +#define mmMMEA5_DSM_CNTLA_BASE_IDX 1 +#define mmMMEA5_DSM_CNTLB 0x338a +#define mmMMEA5_DSM_CNTLB_BASE_IDX 1 +#define mmMMEA5_DSM_CNTL2 0x338b +#define mmMMEA5_DSM_CNTL2_BASE_IDX 1 +#define mmMMEA5_DSM_CNTL2A 0x338c +#define mmMMEA5_DSM_CNTL2A_BASE_IDX 1 +#define mmMMEA5_DSM_CNTL2B 0x338d +#define mmMMEA5_DSM_CNTL2B_BASE_IDX 1 +#define mmMMEA5_CGTT_CLK_CTRL 0x338f +#define mmMMEA5_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmMMEA5_EDC_MODE 0x3390 +#define mmMMEA5_EDC_MODE_BASE_IDX 1 +#define mmMMEA5_ERR_STATUS 0x3391 +#define mmMMEA5_ERR_STATUS_BASE_IDX 1 +#define mmMMEA5_MISC2 0x3392 +#define mmMMEA5_MISC2_BASE_IDX 1 +#define mmMMEA5_ADDRDEC_SELECT 0x3393 +#define mmMMEA5_ADDRDEC_SELECT_BASE_IDX 1 +#define mmMMEA5_EDC_CNT3 0x3394 +#define mmMMEA5_EDC_CNT3_BASE_IDX 1 + + +// addressBlock: mmhub_ea_mmeadec6 +// base address: 0x74f00 +#define mmMMEA6_DRAM_RD_CLI2GRP_MAP0 0x33c0 +#define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_CLI2GRP_MAP1 0x33c1 +#define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_CLI2GRP_MAP0 0x33c2 +#define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_CLI2GRP_MAP1 0x33c3 +#define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_GRP2VC_MAP 0x33c4 +#define mmMMEA6_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_GRP2VC_MAP 0x33c5 +#define mmMMEA6_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_LAZY 0x33c6 +#define mmMMEA6_DRAM_RD_LAZY_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_LAZY 0x33c7 +#define mmMMEA6_DRAM_WR_LAZY_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_CAM_CNTL 0x33c8 +#define mmMMEA6_DRAM_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_CAM_CNTL 0x33c9 +#define mmMMEA6_DRAM_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA6_DRAM_PAGE_BURST 0x33ca +#define mmMMEA6_DRAM_PAGE_BURST_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_PRI_AGE 0x33cb +#define mmMMEA6_DRAM_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_PRI_AGE 0x33cc +#define mmMMEA6_DRAM_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_PRI_QUEUING 0x33cd +#define mmMMEA6_DRAM_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_PRI_QUEUING 0x33ce +#define mmMMEA6_DRAM_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_PRI_FIXED 0x33cf +#define mmMMEA6_DRAM_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_PRI_FIXED 0x33d0 +#define mmMMEA6_DRAM_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_PRI_URGENCY 0x33d1 +#define mmMMEA6_DRAM_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_PRI_URGENCY 0x33d2 +#define mmMMEA6_DRAM_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1 0x33d3 +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2 0x33d4 +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3 0x33d5 +#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1 0x33d6 +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2 0x33d7 +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3 0x33d8 +#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA6_GMI_RD_CLI2GRP_MAP0 0x33d9 +#define mmMMEA6_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA6_GMI_RD_CLI2GRP_MAP1 0x33da +#define mmMMEA6_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA6_GMI_WR_CLI2GRP_MAP0 0x33db +#define mmMMEA6_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA6_GMI_WR_CLI2GRP_MAP1 0x33dc +#define mmMMEA6_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA6_GMI_RD_GRP2VC_MAP 0x33dd +#define mmMMEA6_GMI_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA6_GMI_WR_GRP2VC_MAP 0x33de +#define mmMMEA6_GMI_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA6_GMI_RD_LAZY 0x33df +#define mmMMEA6_GMI_RD_LAZY_BASE_IDX 1 +#define mmMMEA6_GMI_WR_LAZY 0x33e0 +#define mmMMEA6_GMI_WR_LAZY_BASE_IDX 1 +#define mmMMEA6_GMI_RD_CAM_CNTL 0x33e1 +#define mmMMEA6_GMI_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA6_GMI_WR_CAM_CNTL 0x33e2 +#define mmMMEA6_GMI_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA6_GMI_PAGE_BURST 0x33e3 +#define mmMMEA6_GMI_PAGE_BURST_BASE_IDX 1 +#define mmMMEA6_GMI_RD_PRI_AGE 0x33e4 +#define mmMMEA6_GMI_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA6_GMI_WR_PRI_AGE 0x33e5 +#define mmMMEA6_GMI_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA6_GMI_RD_PRI_QUEUING 0x33e6 +#define mmMMEA6_GMI_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA6_GMI_WR_PRI_QUEUING 0x33e7 +#define mmMMEA6_GMI_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA6_GMI_RD_PRI_FIXED 0x33e8 +#define mmMMEA6_GMI_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA6_GMI_WR_PRI_FIXED 0x33e9 +#define mmMMEA6_GMI_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA6_GMI_RD_PRI_URGENCY 0x33ea +#define mmMMEA6_GMI_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA6_GMI_WR_PRI_URGENCY 0x33eb +#define mmMMEA6_GMI_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING 0x33ec +#define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING 0x33ed +#define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI1 0x33ee +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI2 0x33ef +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI3 0x33f0 +#define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI1 0x33f1 +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI2 0x33f2 +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI3 0x33f3 +#define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_BASE_ADDR0 0x33f4 +#define mmMMEA6_ADDRNORM_BASE_ADDR0_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR0 0x33f5 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_BASE_ADDR1 0x33f6 +#define mmMMEA6_ADDRNORM_BASE_ADDR1_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR1 0x33f7 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_OFFSET_ADDR1 0x33f8 +#define mmMMEA6_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_BASE_ADDR2 0x33f9 +#define mmMMEA6_ADDRNORM_BASE_ADDR2_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR2 0x33fa +#define mmMMEA6_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_BASE_ADDR3 0x33fb +#define mmMMEA6_ADDRNORM_BASE_ADDR3_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR3 0x33fc +#define mmMMEA6_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_OFFSET_ADDR3 0x33fd +#define mmMMEA6_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_BASE_ADDR4 0x33fe +#define mmMMEA6_ADDRNORM_BASE_ADDR4_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR4 0x33ff +#define mmMMEA6_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_BASE_ADDR5 0x3400 +#define mmMMEA6_ADDRNORM_BASE_ADDR5_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR5 0x3401 +#define mmMMEA6_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 +#define mmMMEA6_ADDRNORM_OFFSET_ADDR5 0x3402 +#define mmMMEA6_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 +#define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL 0x3403 +#define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA6_ADDRNORMGMI_HOLE_CNTL 0x3404 +#define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x3405 +#define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG 0x3406 +#define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA6_ADDRDEC_BANK_CFG 0x3407 +#define mmMMEA6_ADDRDEC_BANK_CFG_BASE_IDX 1 +#define mmMMEA6_ADDRDEC_MISC_CFG 0x3408 +#define mmMMEA6_ADDRDEC_MISC_CFG_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0 0x3409 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1 0x340a +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2 0x340b +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3 0x340c +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4 0x340d +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5 0x340e +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC 0x340f +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2 0x3410 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0 0x3411 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1 0x3412 +#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE 0x3413 +#define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0 0x3414 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1 0x3415 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2 0x3416 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3 0x3417 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4 0x3418 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5 0x3419 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC 0x341a +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2 0x341b +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0 0x341c +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1 0x341d +#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE 0x341e +#define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0 0x341f +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1 0x3420 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2 0x3421 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3 0x3422 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0 0x3423 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1 0x3424 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2 0x3425 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3 0x3426 +#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01 0x3427 +#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23 0x3428 +#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01 0x3429 +#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23 0x342a +#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01 0x342b +#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23 0x342c +#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01 0x342d +#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23 0x342e +#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01 0x342f +#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23 0x3430 +#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01 0x3431 +#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23 0x3432 +#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01 0x3433 +#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23 0x3434 +#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_RM_SEL_CS01 0x3435 +#define mmMMEA6_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_RM_SEL_CS23 0x3436 +#define mmMMEA6_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01 0x3437 +#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23 0x3438 +#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0 0x3439 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1 0x343a +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2 0x343b +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3 0x343c +#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0 0x343d +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1 0x343e +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2 0x343f +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3 0x3440 +#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01 0x3441 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23 0x3442 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01 0x3443 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23 0x3444 +#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01 0x3445 +#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23 0x3446 +#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01 0x3447 +#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23 0x3448 +#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01 0x3449 +#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23 0x344a +#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01 0x344b +#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23 0x344c +#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01 0x344d +#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23 0x344e +#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_RM_SEL_CS01 0x344f +#define mmMMEA6_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_RM_SEL_CS23 0x3450 +#define mmMMEA6_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01 0x3451 +#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23 0x3452 +#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0 0x3453 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1 0x3454 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2 0x3455 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3 0x3456 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0 0x3457 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1 0x3458 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2 0x3459 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3 0x345a +#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01 0x345b +#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23 0x345c +#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01 0x345d +#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23 0x345e +#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01 0x345f +#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23 0x3460 +#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01 0x3461 +#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23 0x3462 +#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01 0x3463 +#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23 0x3464 +#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01 0x3465 +#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23 0x3466 +#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01 0x3467 +#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23 0x3468 +#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_RM_SEL_CS01 0x3469 +#define mmMMEA6_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_RM_SEL_CS23 0x346a +#define mmMMEA6_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01 0x346b +#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23 0x346c +#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL 0x346d +#define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL 0x346e +#define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA6_IO_RD_CLI2GRP_MAP0 0x3495 +#define mmMMEA6_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA6_IO_RD_CLI2GRP_MAP1 0x3496 +#define mmMMEA6_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA6_IO_WR_CLI2GRP_MAP0 0x3497 +#define mmMMEA6_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA6_IO_WR_CLI2GRP_MAP1 0x3498 +#define mmMMEA6_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA6_IO_RD_COMBINE_FLUSH 0x3499 +#define mmMMEA6_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA6_IO_WR_COMBINE_FLUSH 0x349a +#define mmMMEA6_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA6_IO_GROUP_BURST 0x349b +#define mmMMEA6_IO_GROUP_BURST_BASE_IDX 1 +#define mmMMEA6_IO_RD_PRI_AGE 0x349c +#define mmMMEA6_IO_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA6_IO_WR_PRI_AGE 0x349d +#define mmMMEA6_IO_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA6_IO_RD_PRI_QUEUING 0x349e +#define mmMMEA6_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA6_IO_WR_PRI_QUEUING 0x349f +#define mmMMEA6_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA6_IO_RD_PRI_FIXED 0x34a0 +#define mmMMEA6_IO_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA6_IO_WR_PRI_FIXED 0x34a1 +#define mmMMEA6_IO_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA6_IO_RD_PRI_URGENCY 0x34a2 +#define mmMMEA6_IO_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA6_IO_WR_PRI_URGENCY 0x34a3 +#define mmMMEA6_IO_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA6_IO_RD_PRI_URGENCY_MASKING 0x34a4 +#define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA6_IO_WR_PRI_URGENCY_MASKING 0x34a5 +#define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA6_IO_RD_PRI_QUANT_PRI1 0x34a6 +#define mmMMEA6_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA6_IO_RD_PRI_QUANT_PRI2 0x34a7 +#define mmMMEA6_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA6_IO_RD_PRI_QUANT_PRI3 0x34a8 +#define mmMMEA6_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA6_IO_WR_PRI_QUANT_PRI1 0x34a9 +#define mmMMEA6_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA6_IO_WR_PRI_QUANT_PRI2 0x34aa +#define mmMMEA6_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA6_IO_WR_PRI_QUANT_PRI3 0x34ab +#define mmMMEA6_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA6_SDP_ARB_DRAM 0x34ac +#define mmMMEA6_SDP_ARB_DRAM_BASE_IDX 1 +#define mmMMEA6_SDP_ARB_GMI 0x34ad +#define mmMMEA6_SDP_ARB_GMI_BASE_IDX 1 +#define mmMMEA6_SDP_ARB_FINAL 0x34ae +#define mmMMEA6_SDP_ARB_FINAL_BASE_IDX 1 +#define mmMMEA6_SDP_DRAM_PRIORITY 0x34af +#define mmMMEA6_SDP_DRAM_PRIORITY_BASE_IDX 1 +#define mmMMEA6_SDP_GMI_PRIORITY 0x34b0 +#define mmMMEA6_SDP_GMI_PRIORITY_BASE_IDX 1 +#define mmMMEA6_SDP_IO_PRIORITY 0x34b1 +#define mmMMEA6_SDP_IO_PRIORITY_BASE_IDX 1 +#define mmMMEA6_SDP_CREDITS 0x34b2 +#define mmMMEA6_SDP_CREDITS_BASE_IDX 1 +#define mmMMEA6_SDP_TAG_RESERVE0 0x34b3 +#define mmMMEA6_SDP_TAG_RESERVE0_BASE_IDX 1 +#define mmMMEA6_SDP_TAG_RESERVE1 0x34b4 +#define mmMMEA6_SDP_TAG_RESERVE1_BASE_IDX 1 +#define mmMMEA6_SDP_VCC_RESERVE0 0x34b5 +#define mmMMEA6_SDP_VCC_RESERVE0_BASE_IDX 1 +#define mmMMEA6_SDP_VCC_RESERVE1 0x34b6 +#define mmMMEA6_SDP_VCC_RESERVE1_BASE_IDX 1 +#define mmMMEA6_SDP_VCD_RESERVE0 0x34b7 +#define mmMMEA6_SDP_VCD_RESERVE0_BASE_IDX 1 +#define mmMMEA6_SDP_VCD_RESERVE1 0x34b8 +#define mmMMEA6_SDP_VCD_RESERVE1_BASE_IDX 1 +#define mmMMEA6_SDP_REQ_CNTL 0x34b9 +#define mmMMEA6_SDP_REQ_CNTL_BASE_IDX 1 +#define mmMMEA6_MISC 0x34ba +#define mmMMEA6_MISC_BASE_IDX 1 +#define mmMMEA6_LATENCY_SAMPLING 0x34bb +#define mmMMEA6_LATENCY_SAMPLING_BASE_IDX 1 +#define mmMMEA6_PERFCOUNTER_LO 0x34bc +#define mmMMEA6_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMMEA6_PERFCOUNTER_HI 0x34bd +#define mmMMEA6_PERFCOUNTER_HI_BASE_IDX 1 +#define mmMMEA6_PERFCOUNTER0_CFG 0x34be +#define mmMMEA6_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMMEA6_PERFCOUNTER1_CFG 0x34bf +#define mmMMEA6_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMMEA6_PERFCOUNTER_RSLT_CNTL 0x34c0 +#define mmMMEA6_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmMMEA6_EDC_CNT 0x34c6 +#define mmMMEA6_EDC_CNT_BASE_IDX 1 +#define mmMMEA6_EDC_CNT2 0x34c7 +#define mmMMEA6_EDC_CNT2_BASE_IDX 1 +#define mmMMEA6_DSM_CNTL 0x34c8 +#define mmMMEA6_DSM_CNTL_BASE_IDX 1 +#define mmMMEA6_DSM_CNTLA 0x34c9 +#define mmMMEA6_DSM_CNTLA_BASE_IDX 1 +#define mmMMEA6_DSM_CNTLB 0x34ca +#define mmMMEA6_DSM_CNTLB_BASE_IDX 1 +#define mmMMEA6_DSM_CNTL2 0x34cb +#define mmMMEA6_DSM_CNTL2_BASE_IDX 1 +#define mmMMEA6_DSM_CNTL2A 0x34cc +#define mmMMEA6_DSM_CNTL2A_BASE_IDX 1 +#define mmMMEA6_DSM_CNTL2B 0x34cd +#define mmMMEA6_DSM_CNTL2B_BASE_IDX 1 +#define mmMMEA6_CGTT_CLK_CTRL 0x34cf +#define mmMMEA6_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmMMEA6_EDC_MODE 0x34d0 +#define mmMMEA6_EDC_MODE_BASE_IDX 1 +#define mmMMEA6_ERR_STATUS 0x34d1 +#define mmMMEA6_ERR_STATUS_BASE_IDX 1 +#define mmMMEA6_MISC2 0x34d2 +#define mmMMEA6_MISC2_BASE_IDX 1 +#define mmMMEA6_ADDRDEC_SELECT 0x34d3 +#define mmMMEA6_ADDRDEC_SELECT_BASE_IDX 1 +#define mmMMEA6_EDC_CNT3 0x34d4 +#define mmMMEA6_EDC_CNT3_BASE_IDX 1 + + +// addressBlock: mmhub_ea_mmeadec7 +// base address: 0x75400 +#define mmMMEA7_DRAM_RD_CLI2GRP_MAP0 0x3500 +#define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_CLI2GRP_MAP1 0x3501 +#define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_CLI2GRP_MAP0 0x3502 +#define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_CLI2GRP_MAP1 0x3503 +#define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_GRP2VC_MAP 0x3504 +#define mmMMEA7_DRAM_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_GRP2VC_MAP 0x3505 +#define mmMMEA7_DRAM_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_LAZY 0x3506 +#define mmMMEA7_DRAM_RD_LAZY_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_LAZY 0x3507 +#define mmMMEA7_DRAM_WR_LAZY_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_CAM_CNTL 0x3508 +#define mmMMEA7_DRAM_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_CAM_CNTL 0x3509 +#define mmMMEA7_DRAM_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA7_DRAM_PAGE_BURST 0x350a +#define mmMMEA7_DRAM_PAGE_BURST_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_PRI_AGE 0x350b +#define mmMMEA7_DRAM_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_PRI_AGE 0x350c +#define mmMMEA7_DRAM_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_PRI_QUEUING 0x350d +#define mmMMEA7_DRAM_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_PRI_QUEUING 0x350e +#define mmMMEA7_DRAM_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_PRI_FIXED 0x350f +#define mmMMEA7_DRAM_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_PRI_FIXED 0x3510 +#define mmMMEA7_DRAM_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_PRI_URGENCY 0x3511 +#define mmMMEA7_DRAM_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_PRI_URGENCY 0x3512 +#define mmMMEA7_DRAM_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1 0x3513 +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2 0x3514 +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3 0x3515 +#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1 0x3516 +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2 0x3517 +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3 0x3518 +#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA7_GMI_RD_CLI2GRP_MAP0 0x3519 +#define mmMMEA7_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA7_GMI_RD_CLI2GRP_MAP1 0x351a +#define mmMMEA7_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA7_GMI_WR_CLI2GRP_MAP0 0x351b +#define mmMMEA7_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA7_GMI_WR_CLI2GRP_MAP1 0x351c +#define mmMMEA7_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA7_GMI_RD_GRP2VC_MAP 0x351d +#define mmMMEA7_GMI_RD_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA7_GMI_WR_GRP2VC_MAP 0x351e +#define mmMMEA7_GMI_WR_GRP2VC_MAP_BASE_IDX 1 +#define mmMMEA7_GMI_RD_LAZY 0x351f +#define mmMMEA7_GMI_RD_LAZY_BASE_IDX 1 +#define mmMMEA7_GMI_WR_LAZY 0x3520 +#define mmMMEA7_GMI_WR_LAZY_BASE_IDX 1 +#define mmMMEA7_GMI_RD_CAM_CNTL 0x3521 +#define mmMMEA7_GMI_RD_CAM_CNTL_BASE_IDX 1 +#define mmMMEA7_GMI_WR_CAM_CNTL 0x3522 +#define mmMMEA7_GMI_WR_CAM_CNTL_BASE_IDX 1 +#define mmMMEA7_GMI_PAGE_BURST 0x3523 +#define mmMMEA7_GMI_PAGE_BURST_BASE_IDX 1 +#define mmMMEA7_GMI_RD_PRI_AGE 0x3524 +#define mmMMEA7_GMI_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA7_GMI_WR_PRI_AGE 0x3525 +#define mmMMEA7_GMI_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA7_GMI_RD_PRI_QUEUING 0x3526 +#define mmMMEA7_GMI_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA7_GMI_WR_PRI_QUEUING 0x3527 +#define mmMMEA7_GMI_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA7_GMI_RD_PRI_FIXED 0x3528 +#define mmMMEA7_GMI_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA7_GMI_WR_PRI_FIXED 0x3529 +#define mmMMEA7_GMI_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA7_GMI_RD_PRI_URGENCY 0x352a +#define mmMMEA7_GMI_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA7_GMI_WR_PRI_URGENCY 0x352b +#define mmMMEA7_GMI_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING 0x352c +#define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING 0x352d +#define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI1 0x352e +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI2 0x352f +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI3 0x3530 +#define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI1 0x3531 +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI2 0x3532 +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI3 0x3533 +#define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_BASE_ADDR0 0x3534 +#define mmMMEA7_ADDRNORM_BASE_ADDR0_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR0 0x3535 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_BASE_ADDR1 0x3536 +#define mmMMEA7_ADDRNORM_BASE_ADDR1_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR1 0x3537 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_OFFSET_ADDR1 0x3538 +#define mmMMEA7_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_BASE_ADDR2 0x3539 +#define mmMMEA7_ADDRNORM_BASE_ADDR2_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR2 0x353a +#define mmMMEA7_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_BASE_ADDR3 0x353b +#define mmMMEA7_ADDRNORM_BASE_ADDR3_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR3 0x353c +#define mmMMEA7_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_OFFSET_ADDR3 0x353d +#define mmMMEA7_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_BASE_ADDR4 0x353e +#define mmMMEA7_ADDRNORM_BASE_ADDR4_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR4 0x353f +#define mmMMEA7_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_BASE_ADDR5 0x3540 +#define mmMMEA7_ADDRNORM_BASE_ADDR5_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR5 0x3541 +#define mmMMEA7_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1 +#define mmMMEA7_ADDRNORM_OFFSET_ADDR5 0x3542 +#define mmMMEA7_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1 +#define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL 0x3543 +#define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA7_ADDRNORMGMI_HOLE_CNTL 0x3544 +#define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1 +#define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x3545 +#define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG 0x3546 +#define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1 +#define mmMMEA7_ADDRDEC_BANK_CFG 0x3547 +#define mmMMEA7_ADDRDEC_BANK_CFG_BASE_IDX 1 +#define mmMMEA7_ADDRDEC_MISC_CFG 0x3548 +#define mmMMEA7_ADDRDEC_MISC_CFG_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0 0x3549 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1 0x354a +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2 0x354b +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3 0x354c +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4 0x354d +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5 0x354e +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC 0x354f +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2 0x3550 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0 0x3551 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1 0x3552 +#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE 0x3553 +#define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0 0x3554 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1 0x3555 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2 0x3556 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3 0x3557 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4 0x3558 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5 0x3559 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC 0x355a +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2 0x355b +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0 0x355c +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1 0x355d +#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1 +#define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE 0x355e +#define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0 0x355f +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1 0x3560 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2 0x3561 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3 0x3562 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0 0x3563 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1 0x3564 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2 0x3565 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3 0x3566 +#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01 0x3567 +#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23 0x3568 +#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01 0x3569 +#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23 0x356a +#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01 0x356b +#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23 0x356c +#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01 0x356d +#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23 0x356e +#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01 0x356f +#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23 0x3570 +#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01 0x3571 +#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23 0x3572 +#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01 0x3573 +#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23 0x3574 +#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_RM_SEL_CS01 0x3575 +#define mmMMEA7_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_RM_SEL_CS23 0x3576 +#define mmMMEA7_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01 0x3577 +#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23 0x3578 +#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0 0x3579 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1 0x357a +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2 0x357b +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3 0x357c +#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0 0x357d +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1 0x357e +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2 0x357f +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3 0x3580 +#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01 0x3581 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23 0x3582 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01 0x3583 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23 0x3584 +#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01 0x3585 +#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23 0x3586 +#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01 0x3587 +#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23 0x3588 +#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01 0x3589 +#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23 0x358a +#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01 0x358b +#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23 0x358c +#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01 0x358d +#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23 0x358e +#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_RM_SEL_CS01 0x358f +#define mmMMEA7_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_RM_SEL_CS23 0x3590 +#define mmMMEA7_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01 0x3591 +#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23 0x3592 +#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0 0x3593 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1 0x3594 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2 0x3595 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3 0x3596 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0 0x3597 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1 0x3598 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2 0x3599 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3 0x359a +#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01 0x359b +#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23 0x359c +#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01 0x359d +#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23 0x359e +#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01 0x359f +#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23 0x35a0 +#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01 0x35a1 +#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23 0x35a2 +#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01 0x35a3 +#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23 0x35a4 +#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01 0x35a5 +#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23 0x35a6 +#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01 0x35a7 +#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23 0x35a8 +#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_RM_SEL_CS01 0x35a9 +#define mmMMEA7_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_RM_SEL_CS23 0x35aa +#define mmMMEA7_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01 0x35ab +#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1 +#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23 0x35ac +#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1 +#define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL 0x35ad +#define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL 0x35ae +#define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1 +#define mmMMEA7_IO_RD_CLI2GRP_MAP0 0x35d5 +#define mmMMEA7_IO_RD_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA7_IO_RD_CLI2GRP_MAP1 0x35d6 +#define mmMMEA7_IO_RD_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA7_IO_WR_CLI2GRP_MAP0 0x35d7 +#define mmMMEA7_IO_WR_CLI2GRP_MAP0_BASE_IDX 1 +#define mmMMEA7_IO_WR_CLI2GRP_MAP1 0x35d8 +#define mmMMEA7_IO_WR_CLI2GRP_MAP1_BASE_IDX 1 +#define mmMMEA7_IO_RD_COMBINE_FLUSH 0x35d9 +#define mmMMEA7_IO_RD_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA7_IO_WR_COMBINE_FLUSH 0x35da +#define mmMMEA7_IO_WR_COMBINE_FLUSH_BASE_IDX 1 +#define mmMMEA7_IO_GROUP_BURST 0x35db +#define mmMMEA7_IO_GROUP_BURST_BASE_IDX 1 +#define mmMMEA7_IO_RD_PRI_AGE 0x35dc +#define mmMMEA7_IO_RD_PRI_AGE_BASE_IDX 1 +#define mmMMEA7_IO_WR_PRI_AGE 0x35dd +#define mmMMEA7_IO_WR_PRI_AGE_BASE_IDX 1 +#define mmMMEA7_IO_RD_PRI_QUEUING 0x35de +#define mmMMEA7_IO_RD_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA7_IO_WR_PRI_QUEUING 0x35df +#define mmMMEA7_IO_WR_PRI_QUEUING_BASE_IDX 1 +#define mmMMEA7_IO_RD_PRI_FIXED 0x35e0 +#define mmMMEA7_IO_RD_PRI_FIXED_BASE_IDX 1 +#define mmMMEA7_IO_WR_PRI_FIXED 0x35e1 +#define mmMMEA7_IO_WR_PRI_FIXED_BASE_IDX 1 +#define mmMMEA7_IO_RD_PRI_URGENCY 0x35e2 +#define mmMMEA7_IO_RD_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA7_IO_WR_PRI_URGENCY 0x35e3 +#define mmMMEA7_IO_WR_PRI_URGENCY_BASE_IDX 1 +#define mmMMEA7_IO_RD_PRI_URGENCY_MASKING 0x35e4 +#define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA7_IO_WR_PRI_URGENCY_MASKING 0x35e5 +#define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1 +#define mmMMEA7_IO_RD_PRI_QUANT_PRI1 0x35e6 +#define mmMMEA7_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA7_IO_RD_PRI_QUANT_PRI2 0x35e7 +#define mmMMEA7_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA7_IO_RD_PRI_QUANT_PRI3 0x35e8 +#define mmMMEA7_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA7_IO_WR_PRI_QUANT_PRI1 0x35e9 +#define mmMMEA7_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1 +#define mmMMEA7_IO_WR_PRI_QUANT_PRI2 0x35ea +#define mmMMEA7_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1 +#define mmMMEA7_IO_WR_PRI_QUANT_PRI3 0x35eb +#define mmMMEA7_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1 +#define mmMMEA7_SDP_ARB_DRAM 0x35ec +#define mmMMEA7_SDP_ARB_DRAM_BASE_IDX 1 +#define mmMMEA7_SDP_ARB_GMI 0x35ed +#define mmMMEA7_SDP_ARB_GMI_BASE_IDX 1 +#define mmMMEA7_SDP_ARB_FINAL 0x35ee +#define mmMMEA7_SDP_ARB_FINAL_BASE_IDX 1 +#define mmMMEA7_SDP_DRAM_PRIORITY 0x35ef +#define mmMMEA7_SDP_DRAM_PRIORITY_BASE_IDX 1 +#define mmMMEA7_SDP_GMI_PRIORITY 0x35f0 +#define mmMMEA7_SDP_GMI_PRIORITY_BASE_IDX 1 +#define mmMMEA7_SDP_IO_PRIORITY 0x35f1 +#define mmMMEA7_SDP_IO_PRIORITY_BASE_IDX 1 +#define mmMMEA7_SDP_CREDITS 0x35f2 +#define mmMMEA7_SDP_CREDITS_BASE_IDX 1 +#define mmMMEA7_SDP_TAG_RESERVE0 0x35f3 +#define mmMMEA7_SDP_TAG_RESERVE0_BASE_IDX 1 +#define mmMMEA7_SDP_TAG_RESERVE1 0x35f4 +#define mmMMEA7_SDP_TAG_RESERVE1_BASE_IDX 1 +#define mmMMEA7_SDP_VCC_RESERVE0 0x35f5 +#define mmMMEA7_SDP_VCC_RESERVE0_BASE_IDX 1 +#define mmMMEA7_SDP_VCC_RESERVE1 0x35f6 +#define mmMMEA7_SDP_VCC_RESERVE1_BASE_IDX 1 +#define mmMMEA7_SDP_VCD_RESERVE0 0x35f7 +#define mmMMEA7_SDP_VCD_RESERVE0_BASE_IDX 1 +#define mmMMEA7_SDP_VCD_RESERVE1 0x35f8 +#define mmMMEA7_SDP_VCD_RESERVE1_BASE_IDX 1 +#define mmMMEA7_SDP_REQ_CNTL 0x35f9 +#define mmMMEA7_SDP_REQ_CNTL_BASE_IDX 1 +#define mmMMEA7_MISC 0x35fa +#define mmMMEA7_MISC_BASE_IDX 1 +#define mmMMEA7_LATENCY_SAMPLING 0x35fb +#define mmMMEA7_LATENCY_SAMPLING_BASE_IDX 1 +#define mmMMEA7_PERFCOUNTER_LO 0x35fc +#define mmMMEA7_PERFCOUNTER_LO_BASE_IDX 1 +#define mmMMEA7_PERFCOUNTER_HI 0x35fd +#define mmMMEA7_PERFCOUNTER_HI_BASE_IDX 1 +#define mmMMEA7_PERFCOUNTER0_CFG 0x35fe +#define mmMMEA7_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmMMEA7_PERFCOUNTER1_CFG 0x35ff +#define mmMMEA7_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmMMEA7_PERFCOUNTER_RSLT_CNTL 0x3600 +#define mmMMEA7_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define mmMMEA7_EDC_CNT 0x3606 +#define mmMMEA7_EDC_CNT_BASE_IDX 1 +#define mmMMEA7_EDC_CNT2 0x3607 +#define mmMMEA7_EDC_CNT2_BASE_IDX 1 +#define mmMMEA7_DSM_CNTL 0x3608 +#define mmMMEA7_DSM_CNTL_BASE_IDX 1 +#define mmMMEA7_DSM_CNTLA 0x3609 +#define mmMMEA7_DSM_CNTLA_BASE_IDX 1 +#define mmMMEA7_DSM_CNTLB 0x360a +#define mmMMEA7_DSM_CNTLB_BASE_IDX 1 +#define mmMMEA7_DSM_CNTL2 0x360b +#define mmMMEA7_DSM_CNTL2_BASE_IDX 1 +#define mmMMEA7_DSM_CNTL2A 0x360c +#define mmMMEA7_DSM_CNTL2A_BASE_IDX 1 +#define mmMMEA7_DSM_CNTL2B 0x360d +#define mmMMEA7_DSM_CNTL2B_BASE_IDX 1 +#define mmMMEA7_CGTT_CLK_CTRL 0x360f +#define mmMMEA7_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmMMEA7_EDC_MODE 0x3610 +#define mmMMEA7_EDC_MODE_BASE_IDX 1 +#define mmMMEA7_ERR_STATUS 0x3611 +#define mmMMEA7_ERR_STATUS_BASE_IDX 1 +#define mmMMEA7_MISC2 0x3612 +#define mmMMEA7_MISC2_BASE_IDX 1 +#define mmMMEA7_ADDRDEC_SELECT 0x3613 +#define mmMMEA7_ADDRDEC_SELECT_BASE_IDX 1 +#define mmMMEA7_EDC_CNT3 0x3614 +#define mmMMEA7_EDC_CNT3_BASE_IDX 1 + + +// addressBlock: mmhub_pctldec1 +// base address: 0x76300 +#define mmPCTL1_CTRL 0x38c0 +#define mmPCTL1_CTRL_BASE_IDX 1 +#define mmPCTL1_MMHUB_DEEPSLEEP_IB 0x38c1 +#define mmPCTL1_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 +#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE 0x38c2 +#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 +#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x38c3 +#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 +#define mmPCTL1_PG_IGNORE_DEEPSLEEP 0x38c4 +#define mmPCTL1_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 +#define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB 0x38c5 +#define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 +#define mmPCTL1_SLICE0_CFG_DAGB_BUSY 0x38c6 +#define mmPCTL1_SLICE0_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL1_SLICE0_CFG_DS_ALLOW 0x38c7 +#define mmPCTL1_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB 0x38c8 +#define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL1_SLICE1_CFG_DAGB_BUSY 0x38c9 +#define mmPCTL1_SLICE1_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL1_SLICE1_CFG_DS_ALLOW 0x38ca +#define mmPCTL1_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB 0x38cb +#define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL1_SLICE2_CFG_DAGB_BUSY 0x38cc +#define mmPCTL1_SLICE2_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL1_SLICE2_CFG_DS_ALLOW 0x38cd +#define mmPCTL1_SLICE2_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB 0x38ce +#define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL1_SLICE3_CFG_DAGB_BUSY 0x38cf +#define mmPCTL1_SLICE3_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL1_SLICE3_CFG_DS_ALLOW 0x38d0 +#define mmPCTL1_SLICE3_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB 0x38d1 +#define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL1_SLICE4_CFG_DAGB_BUSY 0x38d2 +#define mmPCTL1_SLICE4_CFG_DAGB_BUSY_BASE_IDX 1 +#define mmPCTL1_SLICE4_CFG_DS_ALLOW 0x38d3 +#define mmPCTL1_SLICE4_CFG_DS_ALLOW_BASE_IDX 1 +#define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB 0x38d4 +#define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 1 +#define mmPCTL1_UTCL2_MISC 0x38d5 +#define mmPCTL1_UTCL2_MISC_BASE_IDX 1 +#define mmPCTL1_SLICE0_MISC 0x38d6 +#define mmPCTL1_SLICE0_MISC_BASE_IDX 1 +#define mmPCTL1_SLICE1_MISC 0x38d7 +#define mmPCTL1_SLICE1_MISC_BASE_IDX 1 +#define mmPCTL1_SLICE2_MISC 0x38d8 +#define mmPCTL1_SLICE2_MISC_BASE_IDX 1 +#define mmPCTL1_SLICE3_MISC 0x38d9 +#define mmPCTL1_SLICE3_MISC_BASE_IDX 1 +#define mmPCTL1_SLICE4_MISC 0x38da +#define mmPCTL1_SLICE4_MISC_BASE_IDX 1 +#define mmPCTL1_UTCL2_RENG_EXECUTE 0x38db +#define mmPCTL1_UTCL2_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL1_SLICE0_RENG_EXECUTE 0x38dc +#define mmPCTL1_SLICE0_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL1_SLICE1_RENG_EXECUTE 0x38dd +#define mmPCTL1_SLICE1_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL1_SLICE2_RENG_EXECUTE 0x38de +#define mmPCTL1_SLICE2_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL1_SLICE3_RENG_EXECUTE 0x38df +#define mmPCTL1_SLICE3_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL1_SLICE4_RENG_EXECUTE 0x38e0 +#define mmPCTL1_SLICE4_RENG_EXECUTE_BASE_IDX 1 +#define mmPCTL1_UTCL2_RENG_RAM_INDEX 0x38e1 +#define mmPCTL1_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL1_UTCL2_RENG_RAM_DATA 0x38e2 +#define mmPCTL1_UTCL2_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL1_SLICE0_RENG_RAM_INDEX 0x38e3 +#define mmPCTL1_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL1_SLICE0_RENG_RAM_DATA 0x38e4 +#define mmPCTL1_SLICE0_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL1_SLICE1_RENG_RAM_INDEX 0x38e5 +#define mmPCTL1_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL1_SLICE1_RENG_RAM_DATA 0x38e6 +#define mmPCTL1_SLICE1_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL1_SLICE2_RENG_RAM_INDEX 0x38e7 +#define mmPCTL1_SLICE2_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL1_SLICE2_RENG_RAM_DATA 0x38e8 +#define mmPCTL1_SLICE2_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL1_SLICE3_RENG_RAM_INDEX 0x38e9 +#define mmPCTL1_SLICE3_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL1_SLICE3_RENG_RAM_DATA 0x38ea +#define mmPCTL1_SLICE3_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL1_SLICE4_RENG_RAM_INDEX 0x38eb +#define mmPCTL1_SLICE4_RENG_RAM_INDEX_BASE_IDX 1 +#define mmPCTL1_SLICE4_RENG_RAM_DATA 0x38ec +#define mmPCTL1_SLICE4_RENG_RAM_DATA_BASE_IDX 1 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x38ed +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x38ee +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x38ef +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x38f0 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x38f1 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x38f2 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x38f3 +#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x38f4 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x38f5 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x38f6 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x38f7 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x38f8 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x38f9 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x38fa +#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x38fb +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x38fc +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x38fd +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x38fe +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x38ff +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3900 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3901 +#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0x3902 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0x3903 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0x3904 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0x3905 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0x3906 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3907 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3908 +#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0x3909 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0x390a +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0x390b +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0x390c +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0x390d +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0x390e +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0x390f +#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0x3910 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0x3911 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0x3912 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0x3913 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0x3914 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3915 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3916 +#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_vml1dec:1 +// base address: 0x76500 +#define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS 0x3948 +#define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 +#define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS 0x3949 +#define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 +#define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS 0x394a +#define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 +#define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS 0x394b +#define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 +#define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS 0x394c +#define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 +#define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS 0x394d +#define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 +#define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS 0x394e +#define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 +#define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS 0x394f +#define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_vml1pldec:1 +// base address: 0x76580 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG 0x3960 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG 0x3961 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG 0x3962 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG 0x3963 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x3964 +#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_l1tlb_vml1prdec:1 +// base address: 0x765c0 +#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO 0x3970 +#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 +#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI 0x3971 +#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_atcl2dec:1 +// base address: 0x76600 +#define mmATCL2_1_ATC_L2_CNTL 0x3980 +#define mmATCL2_1_ATC_L2_CNTL_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CNTL2 0x3981 +#define mmATCL2_1_ATC_L2_CNTL2_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CACHE_DATA0 0x3984 +#define mmATCL2_1_ATC_L2_CACHE_DATA0_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CACHE_DATA1 0x3985 +#define mmATCL2_1_ATC_L2_CACHE_DATA1_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CACHE_DATA2 0x3986 +#define mmATCL2_1_ATC_L2_CACHE_DATA2_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CNTL3 0x3987 +#define mmATCL2_1_ATC_L2_CNTL3_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_STATUS 0x3988 +#define mmATCL2_1_ATC_L2_STATUS_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_STATUS2 0x3989 +#define mmATCL2_1_ATC_L2_STATUS2_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_STATUS3 0x398a +#define mmATCL2_1_ATC_L2_STATUS3_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_MISC_CG 0x398b +#define mmATCL2_1_ATC_L2_MISC_CG_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_MEM_POWER_LS 0x398c +#define mmATCL2_1_ATC_L2_MEM_POWER_LS_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL 0x398d +#define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX 0x398e +#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX 0x398f +#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL 0x3990 +#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL 0x3991 +#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_CNTL4 0x3992 +#define mmATCL2_1_ATC_L2_CNTL4_BASE_IDX 1 +#define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES 0x3993 +#define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vml2pfdec:1 +// base address: 0x76700 +#define mmVML2PF1_VM_L2_CNTL 0x39c0 +#define mmVML2PF1_VM_L2_CNTL_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CNTL2 0x39c1 +#define mmVML2PF1_VM_L2_CNTL2_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CNTL3 0x39c2 +#define mmVML2PF1_VM_L2_CNTL3_BASE_IDX 1 +#define mmVML2PF1_VM_L2_STATUS 0x39c3 +#define mmVML2PF1_VM_L2_STATUS_BASE_IDX 1 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL 0x39c4 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0x39c5 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0x39c6 +#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL 0x39c7 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2 0x39c8 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3 0x39c9 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4 0x39ca +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS 0x39cb +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32 0x39cc +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32 0x39cd +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x39ce +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x39cf +#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x39d1 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x39d2 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x39d3 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x39d4 +#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x39d5 +#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x39d6 +#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CNTL4 0x39d7 +#define mmVML2PF1_VM_L2_CNTL4_BASE_IDX 1 +#define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES 0x39d8 +#define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 +#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID 0x39d9 +#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 +#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2 0x39da +#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL 0x39db +#define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 +#define mmVML2PF1_VM_L2_CGTT_CLK_CTRL 0x39de +#define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vml2vcdec:1 +// base address: 0x76800 +#define mmVML2VC1_VM_CONTEXT0_CNTL 0x3a00 +#define mmVML2VC1_VM_CONTEXT0_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT1_CNTL 0x3a01 +#define mmVML2VC1_VM_CONTEXT1_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT2_CNTL 0x3a02 +#define mmVML2VC1_VM_CONTEXT2_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT3_CNTL 0x3a03 +#define mmVML2VC1_VM_CONTEXT3_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT4_CNTL 0x3a04 +#define mmVML2VC1_VM_CONTEXT4_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT5_CNTL 0x3a05 +#define mmVML2VC1_VM_CONTEXT5_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT6_CNTL 0x3a06 +#define mmVML2VC1_VM_CONTEXT6_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT7_CNTL 0x3a07 +#define mmVML2VC1_VM_CONTEXT7_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT8_CNTL 0x3a08 +#define mmVML2VC1_VM_CONTEXT8_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT9_CNTL 0x3a09 +#define mmVML2VC1_VM_CONTEXT9_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT10_CNTL 0x3a0a +#define mmVML2VC1_VM_CONTEXT10_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT11_CNTL 0x3a0b +#define mmVML2VC1_VM_CONTEXT11_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT12_CNTL 0x3a0c +#define mmVML2VC1_VM_CONTEXT12_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT13_CNTL 0x3a0d +#define mmVML2VC1_VM_CONTEXT13_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT14_CNTL 0x3a0e +#define mmVML2VC1_VM_CONTEXT14_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT15_CNTL 0x3a0f +#define mmVML2VC1_VM_CONTEXT15_CNTL_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXTS_DISABLE 0x3a10 +#define mmVML2VC1_VM_CONTEXTS_DISABLE_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG0_SEM 0x3a11 +#define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG1_SEM 0x3a12 +#define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG2_SEM 0x3a13 +#define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG3_SEM 0x3a14 +#define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG4_SEM 0x3a15 +#define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG5_SEM 0x3a16 +#define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG6_SEM 0x3a17 +#define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG7_SEM 0x3a18 +#define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG8_SEM 0x3a19 +#define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG9_SEM 0x3a1a +#define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG10_SEM 0x3a1b +#define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG11_SEM 0x3a1c +#define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG12_SEM 0x3a1d +#define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG13_SEM 0x3a1e +#define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG14_SEM 0x3a1f +#define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG15_SEM 0x3a20 +#define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG16_SEM 0x3a21 +#define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG17_SEM 0x3a22 +#define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG0_REQ 0x3a23 +#define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG1_REQ 0x3a24 +#define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG2_REQ 0x3a25 +#define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG3_REQ 0x3a26 +#define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG4_REQ 0x3a27 +#define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG5_REQ 0x3a28 +#define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG6_REQ 0x3a29 +#define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG7_REQ 0x3a2a +#define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG8_REQ 0x3a2b +#define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG9_REQ 0x3a2c +#define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG10_REQ 0x3a2d +#define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG11_REQ 0x3a2e +#define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG12_REQ 0x3a2f +#define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG13_REQ 0x3a30 +#define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG14_REQ 0x3a31 +#define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG15_REQ 0x3a32 +#define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG16_REQ 0x3a33 +#define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG17_REQ 0x3a34 +#define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ACK 0x3a35 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG1_ACK 0x3a36 +#define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG2_ACK 0x3a37 +#define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG3_ACK 0x3a38 +#define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG4_ACK 0x3a39 +#define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG5_ACK 0x3a3a +#define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG6_ACK 0x3a3b +#define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG7_ACK 0x3a3c +#define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG8_ACK 0x3a3d +#define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG9_ACK 0x3a3e +#define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG10_ACK 0x3a3f +#define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG11_ACK 0x3a40 +#define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG12_ACK 0x3a41 +#define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ACK 0x3a42 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ACK 0x3a43 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ACK 0x3a44 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ACK 0x3a45 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG17_ACK 0x3a46 +#define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x3a47 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x3a48 +#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x3a49 +#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x3a4a +#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x3a4b +#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x3a4c +#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x3a4d +#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x3a4e +#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x3a4f +#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x3a50 +#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x3a51 +#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x3a52 +#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x3a53 +#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x3a54 +#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x3a55 +#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x3a56 +#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x3a57 +#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x3a58 +#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x3a59 +#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x3a5a +#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x3a5b +#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x3a5c +#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x3a5d +#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x3a5e +#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x3a5f +#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x3a60 +#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x3a61 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x3a62 +#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x3a63 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x3a64 +#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x3a65 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x3a66 +#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x3a67 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x3a68 +#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x3a69 +#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x3a6a +#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x3a6b +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x3a6c +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x3a6d +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x3a6e +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x3a6f +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x3a70 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x3a71 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x3a72 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x3a73 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x3a74 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x3a75 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x3a76 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x3a77 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x3a78 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x3a79 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x3a7a +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x3a7b +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x3a7c +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x3a7d +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x3a7e +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x3a7f +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x3a80 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x3a81 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x3a82 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x3a83 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x3a84 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x3a85 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x3a86 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x3a87 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x3a88 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x3a89 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x3a8a +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x3a8b +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x3a8c +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x3a8d +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x3a8e +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x3a8f +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x3a90 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x3a91 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x3a92 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x3a93 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x3a94 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x3a95 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x3a96 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x3a97 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x3a98 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x3a99 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x3a9a +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x3a9b +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x3a9c +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x3a9d +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x3a9e +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x3a9f +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x3aa0 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x3aa1 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x3aa2 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x3aa3 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x3aa4 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x3aa5 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x3aa6 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x3aa7 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x3aa8 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x3aa9 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x3aaa +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x3aab +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x3aac +#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x3aad +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x3aae +#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x3aaf +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x3ab0 +#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x3ab1 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x3ab2 +#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x3ab3 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x3ab4 +#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x3ab5 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x3ab6 +#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x3ab7 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x3ab8 +#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x3ab9 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x3aba +#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x3abb +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x3abc +#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x3abd +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x3abe +#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x3abf +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x3ac0 +#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x3ac1 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x3ac2 +#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x3ac3 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x3ac4 +#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x3ac5 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x3ac6 +#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x3ac7 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x3ac8 +#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x3ac9 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x3aca +#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vmsharedpfdec:1 +// base address: 0x76b90 +#define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE 0x3ae4 +#define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT 0x3ae5 +#define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL 0x3ae6 +#define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB 0x3ae7 +#define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1 0x3ae8 +#define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2 0x3ae9 +#define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2 0x3aea +#define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_FB_OFFSET 0x3aeb +#define mmVMSHAREDPF1_MC_VM_FB_OFFSET_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x3aec +#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x3aed +#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_STEERING 0x3aee +#define mmVMSHAREDPF1_MC_VM_STEERING_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ 0x3aef +#define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_MEM_POWER_LS 0x3af0 +#define mmVMSHAREDPF1_MC_MEM_POWER_LS_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0x3af1 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0x3af2 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_APT_CNTL 0x3af3 +#define mmVMSHAREDPF1_MC_VM_APT_CNTL_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START 0x3af4 +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END 0x3af5 +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x3af6 +#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL 0x3af7 +#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE 0x3af8 +#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL 0x3af9 +#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vmsharedvcdec:1 +// base address: 0x76c00 +#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE 0x3b00 +#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_BASE_IDX 1 +#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP 0x3b01 +#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_BASE_IDX 1 +#define mmVMSHAREDVC1_MC_VM_AGP_TOP 0x3b02 +#define mmVMSHAREDVC1_MC_VM_AGP_TOP_BASE_IDX 1 +#define mmVMSHAREDVC1_MC_VM_AGP_BOT 0x3b03 +#define mmVMSHAREDVC1_MC_VM_AGP_BOT_BASE_IDX 1 +#define mmVMSHAREDVC1_MC_VM_AGP_BASE 0x3b04 +#define mmVMSHAREDVC1_MC_VM_AGP_BASE_BASE_IDX 1 +#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x3b05 +#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 +#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x3b06 +#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 +#define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL 0x3b07 +#define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vmsharedhvdec:1 +// base address: 0x76c80 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0 0x3b20 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1 0x3b21 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2 0x3b22 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3 0x3b23 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4 0x3b24 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5 0x3b25 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6 0x3b26 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7 0x3b27 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8 0x3b28 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9 0x3b29 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10 0x3b2a +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11 0x3b2b +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12 0x3b2c +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13 0x3b2d +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14 0x3b2e +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15 0x3b2f +#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1 0x3b30 +#define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0 0x3b31 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1 0x3b32 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2 0x3b33 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3 0x3b34 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0 0x3b35 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1 0x3b36 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2 0x3b37 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3 0x3b38 +#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0 0x3b39 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1 0x3b3a +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2 0x3b3b +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3 0x3b3c +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0 0x3b3d +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1 0x3b3e +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2 0x3b3f +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3 0x3b40 +#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0 0x3b41 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1 0x3b42 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2 0x3b43 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3 0x3b44 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0 0x3b45 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1 0x3b46 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2 0x3b47 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3 0x3b48 +#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER 0x3b49 +#define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x3b4a +#define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL 0x3b4b +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0 0x3b4c +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1 0x3b4d +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2 0x3b4e +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3 0x3b4f +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4 0x3b50 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5 0x3b51 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6 0x3b52 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7 0x3b53 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8 0x3b54 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9 0x3b55 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10 0x3b56 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11 0x3b57 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12 0x3b58 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13 0x3b59 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14 0x3b5a +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1 +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15 0x3b5b +#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1 +#define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL 0x3b5c +#define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID 0x3b5d +#define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE 0x3b5e +#define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 +// base address: 0x76dc0 +#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO 0x3b70 +#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI 0x3b71 +#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec:1 +// base address: 0x76dd0 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG 0x3b74 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG 0x3b75 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x3b76 +#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vml2pldec:1 +// base address: 0x76e00 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG 0x3b80 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG 0x3b81 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG 0x3b82 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG 0x3b83 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG 0x3b84 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG 0x3b85 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG 0x3b86 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG 0x3b87 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3b88 +#define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: mmhub_utcl2_vml2prdec:1 +// base address: 0x76e40 +#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO 0x3b90 +#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI 0x3b91 +#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h new file mode 100644 index 000000000000..40dfbf16bd34 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h @@ -0,0 +1,44884 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mmhub_9_4_1_SH_MASK_HEADER +#define _mmhub_9_4_1_SH_MASK_HEADER + + +// addressBlock: mmhub_dagb_dagbdec0 +//DAGB0_RDCLI0 +#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI1 +#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI2 +#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI3 +#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI4 +#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI5 +#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI6 +#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI7 +#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI8 +#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI9 +#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI10 +#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI11 +#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI12 +#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI13 +#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI14 +#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_RDCLI15 +#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_RD_CNTL +#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB0_RD_GMI_CNTL +#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB0_RD_ADDR_DAGB +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB0_RD_CGTT_CLK_CTRL +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_RD_VC0_CNTL +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC1_CNTL +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC2_CNTL +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC3_CNTL +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC4_CNTL +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC5_CNTL +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC6_CNTL +#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_VC7_CNTL +#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_RD_CNTL_MISC +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB0_RD_TLB_CREDIT +#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_RDCLI_ASK_PENDING +#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GO_PENDING +#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_GBLSEND_PENDING +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_TLB_PENDING +#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OARB_PENDING +#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_RDCLI_OSD_PENDING +#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI0 +#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI1 +#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI2 +#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI3 +#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI4 +#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI5 +#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI6 +#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI7 +#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI8 +#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI9 +#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI10 +#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI11 +#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI12 +#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI13 +#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI14 +#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB0_WRCLI15 +#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB0_WR_CNTL +#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB0_WR_GMI_CNTL +#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB0_WR_ADDR_DAGB +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB0_WR_CGTT_CLK_CTRL +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB0_WR_DATA_DAGB_MAX_BURST0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_MAX_BURST1 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB0_WR_VC0_CNTL +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC1_CNTL +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC2_CNTL +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC3_CNTL +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC4_CNTL +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC5_CNTL +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC6_CNTL +#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_VC7_CNTL +#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB0_WR_CNTL_MISC +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB0_WR_TLB_CREDIT +#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB0_WR_DATA_CREDIT +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB0_WR_MISC_CREDIT +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB0_WRCLI_ASK_PENDING +#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GO_PENDING +#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_GBLSEND_PENDING +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_TLB_PENDING +#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OARB_PENDING +#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_OSD_PENDING +#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_ASK_PENDING +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_WRCLI_DBUS_GO_PENDING +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB0_DAGB_DLY +#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB0_CNTL_MISC +#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB0_CNTL_MISC2 +#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB0_FIFO_EMPTY +#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB0_FIFO_FULL +#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB0_WR_CREDITS_FULL +#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB0_RD_CREDITS_FULL +#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB0_PERFCOUNTER_LO +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB0_PERFCOUNTER_HI +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB0_PERFCOUNTER0_CFG +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER1_CFG +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER2_CFG +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB0_PERFCOUNTER_RSLT_CNTL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB0_RESERVE0 +#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE1 +#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE2 +#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE3 +#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE4 +#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE5 +#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE6 +#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE7 +#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE8 +#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE9 +#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE10 +#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE11 +#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE12 +#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB0_RESERVE13 +#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec1 +//DAGB1_RDCLI0 +#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI1 +#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI2 +#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI3 +#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI4 +#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI5 +#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI6 +#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI7 +#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI8 +#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI9 +#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI10 +#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI11 +#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI12 +#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI13 +#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI14 +#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB1_RDCLI15 +#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB1_RD_CNTL +#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB1_RD_GMI_CNTL +#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB1_RD_ADDR_DAGB +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB1_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB1_RD_CGTT_CLK_CTRL +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_RD_VC0_CNTL +#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC1_CNTL +#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC2_CNTL +#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC3_CNTL +#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC4_CNTL +#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC5_CNTL +#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC6_CNTL +#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_VC7_CNTL +#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_RD_CNTL_MISC +#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB1_RD_TLB_CREDIT +#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB1_RDCLI_ASK_PENDING +#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_GO_PENDING +#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_GBLSEND_PENDING +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_TLB_PENDING +#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_OARB_PENDING +#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_RDCLI_OSD_PENDING +#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI0 +#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI1 +#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI2 +#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI3 +#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI4 +#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI5 +#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI6 +#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI7 +#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI8 +#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI9 +#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI10 +#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI11 +#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI12 +#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI13 +#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI14 +#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB1_WRCLI15 +#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB1_WR_CNTL +#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB1_WR_GMI_CNTL +#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB1_WR_ADDR_DAGB +#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB1_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB1_WR_CGTT_CLK_CTRL +#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB1_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB +#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB1_WR_DATA_DAGB_MAX_BURST0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_MAX_BURST1 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB1_WR_VC0_CNTL +#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC1_CNTL +#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC2_CNTL +#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC3_CNTL +#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC4_CNTL +#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC5_CNTL +#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC6_CNTL +#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_VC7_CNTL +#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB1_WR_CNTL_MISC +#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB1_WR_TLB_CREDIT +#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB1_WR_DATA_CREDIT +#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB1_WR_MISC_CREDIT +#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB1_WRCLI_ASK_PENDING +#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_GO_PENDING +#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_GBLSEND_PENDING +#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_TLB_PENDING +#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_OARB_PENDING +#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_OSD_PENDING +#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_DBUS_ASK_PENDING +#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_WRCLI_DBUS_GO_PENDING +#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB1_DAGB_DLY +#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB1_CNTL_MISC +#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB1_CNTL_MISC2 +#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB1_FIFO_EMPTY +#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB1_FIFO_FULL +#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB1_WR_CREDITS_FULL +#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB1_RD_CREDITS_FULL +#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB1_PERFCOUNTER_LO +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB1_PERFCOUNTER_HI +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB1_PERFCOUNTER0_CFG +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER1_CFG +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER2_CFG +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB1_PERFCOUNTER_RSLT_CNTL +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB1_RESERVE0 +#define DAGB1_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE1 +#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE2 +#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE3 +#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE4 +#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE5 +#define DAGB1_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE6 +#define DAGB1_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE7 +#define DAGB1_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE8 +#define DAGB1_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE9 +#define DAGB1_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE10 +#define DAGB1_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE11 +#define DAGB1_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE12 +#define DAGB1_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB1_RESERVE13 +#define DAGB1_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec2 +//DAGB2_RDCLI0 +#define DAGB2_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI1 +#define DAGB2_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI2 +#define DAGB2_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI3 +#define DAGB2_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI4 +#define DAGB2_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI5 +#define DAGB2_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI6 +#define DAGB2_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI7 +#define DAGB2_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI8 +#define DAGB2_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI9 +#define DAGB2_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI10 +#define DAGB2_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI11 +#define DAGB2_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI12 +#define DAGB2_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI13 +#define DAGB2_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI14 +#define DAGB2_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB2_RDCLI15 +#define DAGB2_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB2_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB2_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB2_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB2_RD_CNTL +#define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB2_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB2_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB2_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB2_RD_GMI_CNTL +#define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB2_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB2_RD_ADDR_DAGB +#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB2_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB2_RD_CGTT_CLK_CTRL +#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB2_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB2_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB2_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB2_RD_VC0_CNTL +#define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC1_CNTL +#define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC2_CNTL +#define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC3_CNTL +#define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC4_CNTL +#define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC5_CNTL +#define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC6_CNTL +#define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_VC7_CNTL +#define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_RD_CNTL_MISC +#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB2_RD_TLB_CREDIT +#define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB2_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB2_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB2_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB2_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB2_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB2_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB2_RDCLI_ASK_PENDING +#define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_GO_PENDING +#define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_GBLSEND_PENDING +#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_TLB_PENDING +#define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_OARB_PENDING +#define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_RDCLI_OSD_PENDING +#define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI0 +#define DAGB2_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI1 +#define DAGB2_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI2 +#define DAGB2_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI3 +#define DAGB2_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI4 +#define DAGB2_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI5 +#define DAGB2_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI6 +#define DAGB2_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI7 +#define DAGB2_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI8 +#define DAGB2_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI9 +#define DAGB2_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI10 +#define DAGB2_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI11 +#define DAGB2_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI12 +#define DAGB2_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI13 +#define DAGB2_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI14 +#define DAGB2_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB2_WRCLI15 +#define DAGB2_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB2_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB2_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB2_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB2_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB2_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB2_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB2_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB2_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB2_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB2_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB2_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB2_WR_CNTL +#define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB2_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB2_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB2_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB2_WR_GMI_CNTL +#define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB2_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB2_WR_ADDR_DAGB +#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB2_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB2_WR_CGTT_CLK_CTRL +#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB2_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB2_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB2_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB2_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB2_WR_DATA_DAGB +#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB2_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB2_WR_DATA_DAGB_MAX_BURST0 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB2_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB2_WR_DATA_DAGB_MAX_BURST1 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB2_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB2_WR_VC0_CNTL +#define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC1_CNTL +#define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC2_CNTL +#define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC3_CNTL +#define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC4_CNTL +#define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC5_CNTL +#define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC6_CNTL +#define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_VC7_CNTL +#define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB2_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB2_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB2_WR_CNTL_MISC +#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB2_WR_TLB_CREDIT +#define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB2_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB2_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB2_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB2_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB2_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB2_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB2_WR_DATA_CREDIT +#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB2_WR_MISC_CREDIT +#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB2_WRCLI_ASK_PENDING +#define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_GO_PENDING +#define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_GBLSEND_PENDING +#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_TLB_PENDING +#define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_OARB_PENDING +#define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_OSD_PENDING +#define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_DBUS_ASK_PENDING +#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_WRCLI_DBUS_GO_PENDING +#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB2_DAGB_DLY +#define DAGB2_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB2_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB2_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB2_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB2_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB2_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB2_CNTL_MISC +#define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB2_CNTL_MISC2 +#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB2_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB2_FIFO_EMPTY +#define DAGB2_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB2_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB2_FIFO_FULL +#define DAGB2_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB2_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB2_WR_CREDITS_FULL +#define DAGB2_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB2_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB2_RD_CREDITS_FULL +#define DAGB2_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB2_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB2_PERFCOUNTER_LO +#define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB2_PERFCOUNTER_HI +#define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB2_PERFCOUNTER0_CFG +#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB2_PERFCOUNTER1_CFG +#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB2_PERFCOUNTER2_CFG +#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB2_PERFCOUNTER_RSLT_CNTL +#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB2_RESERVE0 +#define DAGB2_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE1 +#define DAGB2_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE2 +#define DAGB2_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE3 +#define DAGB2_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE4 +#define DAGB2_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE5 +#define DAGB2_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE6 +#define DAGB2_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE7 +#define DAGB2_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE8 +#define DAGB2_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE9 +#define DAGB2_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE10 +#define DAGB2_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE11 +#define DAGB2_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE12 +#define DAGB2_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB2_RESERVE13 +#define DAGB2_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB2_RESERVE13__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec3 +//DAGB3_RDCLI0 +#define DAGB3_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI1 +#define DAGB3_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI2 +#define DAGB3_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI3 +#define DAGB3_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI4 +#define DAGB3_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI5 +#define DAGB3_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI6 +#define DAGB3_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI7 +#define DAGB3_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI8 +#define DAGB3_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI9 +#define DAGB3_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI10 +#define DAGB3_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI11 +#define DAGB3_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI12 +#define DAGB3_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI13 +#define DAGB3_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI14 +#define DAGB3_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB3_RDCLI15 +#define DAGB3_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB3_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB3_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB3_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB3_RD_CNTL +#define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB3_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB3_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB3_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB3_RD_GMI_CNTL +#define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB3_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB3_RD_ADDR_DAGB +#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB3_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB3_RD_CGTT_CLK_CTRL +#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB3_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB3_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB3_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB3_RD_VC0_CNTL +#define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC1_CNTL +#define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC2_CNTL +#define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC3_CNTL +#define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC4_CNTL +#define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC5_CNTL +#define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC6_CNTL +#define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_VC7_CNTL +#define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_RD_CNTL_MISC +#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB3_RD_TLB_CREDIT +#define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB3_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB3_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB3_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB3_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB3_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB3_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB3_RDCLI_ASK_PENDING +#define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_GO_PENDING +#define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_GBLSEND_PENDING +#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_TLB_PENDING +#define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_OARB_PENDING +#define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_RDCLI_OSD_PENDING +#define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI0 +#define DAGB3_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI1 +#define DAGB3_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI2 +#define DAGB3_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI3 +#define DAGB3_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI4 +#define DAGB3_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI5 +#define DAGB3_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI6 +#define DAGB3_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI7 +#define DAGB3_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI8 +#define DAGB3_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI9 +#define DAGB3_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI10 +#define DAGB3_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI11 +#define DAGB3_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI12 +#define DAGB3_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI13 +#define DAGB3_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI14 +#define DAGB3_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB3_WRCLI15 +#define DAGB3_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB3_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB3_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB3_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB3_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB3_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB3_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB3_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB3_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB3_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB3_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB3_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB3_WR_CNTL +#define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB3_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB3_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB3_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB3_WR_GMI_CNTL +#define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB3_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB3_WR_ADDR_DAGB +#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB3_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB3_WR_CGTT_CLK_CTRL +#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB3_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB3_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB3_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB3_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB3_WR_DATA_DAGB +#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB3_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB3_WR_DATA_DAGB_MAX_BURST0 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB3_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB3_WR_DATA_DAGB_MAX_BURST1 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB3_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB3_WR_VC0_CNTL +#define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC1_CNTL +#define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC2_CNTL +#define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC3_CNTL +#define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC4_CNTL +#define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC5_CNTL +#define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC6_CNTL +#define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_VC7_CNTL +#define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB3_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB3_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB3_WR_CNTL_MISC +#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB3_WR_TLB_CREDIT +#define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB3_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB3_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB3_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB3_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB3_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB3_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB3_WR_DATA_CREDIT +#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB3_WR_MISC_CREDIT +#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB3_WRCLI_ASK_PENDING +#define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_GO_PENDING +#define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_GBLSEND_PENDING +#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_TLB_PENDING +#define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_OARB_PENDING +#define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_OSD_PENDING +#define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_DBUS_ASK_PENDING +#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_WRCLI_DBUS_GO_PENDING +#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB3_DAGB_DLY +#define DAGB3_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB3_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB3_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB3_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB3_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB3_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB3_CNTL_MISC +#define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB3_CNTL_MISC2 +#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB3_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB3_FIFO_EMPTY +#define DAGB3_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB3_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB3_FIFO_FULL +#define DAGB3_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB3_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB3_WR_CREDITS_FULL +#define DAGB3_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB3_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB3_RD_CREDITS_FULL +#define DAGB3_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB3_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB3_PERFCOUNTER_LO +#define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB3_PERFCOUNTER_HI +#define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB3_PERFCOUNTER0_CFG +#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB3_PERFCOUNTER1_CFG +#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB3_PERFCOUNTER2_CFG +#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB3_PERFCOUNTER_RSLT_CNTL +#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB3_RESERVE0 +#define DAGB3_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE1 +#define DAGB3_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE2 +#define DAGB3_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE3 +#define DAGB3_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE4 +#define DAGB3_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE5 +#define DAGB3_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE6 +#define DAGB3_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE7 +#define DAGB3_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE8 +#define DAGB3_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE9 +#define DAGB3_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE10 +#define DAGB3_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE11 +#define DAGB3_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE12 +#define DAGB3_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB3_RESERVE13 +#define DAGB3_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB3_RESERVE13__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec4 +//DAGB4_RDCLI0 +#define DAGB4_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI1 +#define DAGB4_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI2 +#define DAGB4_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI3 +#define DAGB4_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI4 +#define DAGB4_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI5 +#define DAGB4_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI6 +#define DAGB4_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI7 +#define DAGB4_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI8 +#define DAGB4_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI9 +#define DAGB4_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI10 +#define DAGB4_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI11 +#define DAGB4_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI12 +#define DAGB4_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI13 +#define DAGB4_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI14 +#define DAGB4_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB4_RDCLI15 +#define DAGB4_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB4_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB4_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB4_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB4_RD_CNTL +#define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB4_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB4_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB4_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB4_RD_GMI_CNTL +#define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB4_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB4_RD_ADDR_DAGB +#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB4_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB4_RD_CGTT_CLK_CTRL +#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB4_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB4_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB4_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB4_RD_VC0_CNTL +#define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC1_CNTL +#define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC2_CNTL +#define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC3_CNTL +#define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC4_CNTL +#define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC5_CNTL +#define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC6_CNTL +#define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_VC7_CNTL +#define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_RD_CNTL_MISC +#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB4_RD_TLB_CREDIT +#define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB4_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB4_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB4_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB4_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB4_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB4_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB4_RDCLI_ASK_PENDING +#define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_GO_PENDING +#define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_GBLSEND_PENDING +#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_TLB_PENDING +#define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_OARB_PENDING +#define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_RDCLI_OSD_PENDING +#define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI0 +#define DAGB4_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI1 +#define DAGB4_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI2 +#define DAGB4_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI3 +#define DAGB4_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI4 +#define DAGB4_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI5 +#define DAGB4_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI6 +#define DAGB4_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI7 +#define DAGB4_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI8 +#define DAGB4_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI9 +#define DAGB4_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI10 +#define DAGB4_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI11 +#define DAGB4_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI12 +#define DAGB4_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI13 +#define DAGB4_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI14 +#define DAGB4_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB4_WRCLI15 +#define DAGB4_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB4_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB4_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB4_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB4_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB4_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB4_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB4_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB4_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB4_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB4_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB4_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB4_WR_CNTL +#define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB4_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB4_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB4_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB4_WR_GMI_CNTL +#define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB4_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB4_WR_ADDR_DAGB +#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB4_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB4_WR_CGTT_CLK_CTRL +#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB4_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB4_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB4_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB4_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB4_WR_DATA_DAGB +#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB4_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB4_WR_DATA_DAGB_MAX_BURST0 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB4_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB4_WR_DATA_DAGB_MAX_BURST1 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB4_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB4_WR_VC0_CNTL +#define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC1_CNTL +#define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC2_CNTL +#define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC3_CNTL +#define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC4_CNTL +#define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC5_CNTL +#define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC6_CNTL +#define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_VC7_CNTL +#define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB4_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB4_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB4_WR_CNTL_MISC +#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB4_WR_TLB_CREDIT +#define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB4_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB4_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB4_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB4_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB4_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB4_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB4_WR_DATA_CREDIT +#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB4_WR_MISC_CREDIT +#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB4_WRCLI_ASK_PENDING +#define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_GO_PENDING +#define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_GBLSEND_PENDING +#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_TLB_PENDING +#define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_OARB_PENDING +#define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_OSD_PENDING +#define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_DBUS_ASK_PENDING +#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_WRCLI_DBUS_GO_PENDING +#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB4_DAGB_DLY +#define DAGB4_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB4_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB4_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB4_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB4_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB4_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB4_CNTL_MISC +#define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB4_CNTL_MISC2 +#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB4_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB4_FIFO_EMPTY +#define DAGB4_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB4_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB4_FIFO_FULL +#define DAGB4_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB4_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB4_WR_CREDITS_FULL +#define DAGB4_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB4_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB4_RD_CREDITS_FULL +#define DAGB4_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB4_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB4_PERFCOUNTER_LO +#define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB4_PERFCOUNTER_HI +#define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB4_PERFCOUNTER0_CFG +#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB4_PERFCOUNTER1_CFG +#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB4_PERFCOUNTER2_CFG +#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB4_PERFCOUNTER_RSLT_CNTL +#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB4_RESERVE0 +#define DAGB4_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE1 +#define DAGB4_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE2 +#define DAGB4_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE3 +#define DAGB4_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE4 +#define DAGB4_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE5 +#define DAGB4_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE6 +#define DAGB4_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE7 +#define DAGB4_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE8 +#define DAGB4_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE9 +#define DAGB4_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE10 +#define DAGB4_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE11 +#define DAGB4_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE12 +#define DAGB4_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB4_RESERVE13 +#define DAGB4_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB4_RESERVE13__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_ea_mmeadec0 +//MMEA0_DRAM_RD_CLI2GRP_MAP0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_RD_CLI2GRP_MAP1 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_WR_CLI2GRP_MAP0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_WR_CLI2GRP_MAP1 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_DRAM_RD_GRP2VC_MAP +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_DRAM_WR_GRP2VC_MAP +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_DRAM_RD_LAZY +#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA0_DRAM_WR_LAZY +#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA0_DRAM_RD_CAM_CNTL +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA0_DRAM_WR_CAM_CNTL +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA0_DRAM_PAGE_BURST +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_AGE +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_DRAM_WR_PRI_AGE +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_DRAM_RD_PRI_QUEUING +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_WR_PRI_QUEUING +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_RD_PRI_FIXED +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_WR_PRI_FIXED +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_DRAM_RD_PRI_URGENCY +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_DRAM_WR_PRI_URGENCY +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_RD_CLI2GRP_MAP0 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_GMI_RD_CLI2GRP_MAP1 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_GMI_WR_CLI2GRP_MAP0 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_GMI_WR_CLI2GRP_MAP1 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_GMI_RD_GRP2VC_MAP +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_GMI_WR_GRP2VC_MAP +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA0_GMI_RD_LAZY +#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA0_GMI_WR_LAZY +#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA0_GMI_RD_CAM_CNTL +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA0_GMI_WR_CAM_CNTL +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA0_GMI_PAGE_BURST +#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA0_GMI_RD_PRI_AGE +#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_GMI_WR_PRI_AGE +#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_GMI_RD_PRI_QUEUING +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_GMI_WR_PRI_QUEUING +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_GMI_RD_PRI_FIXED +#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_GMI_WR_PRI_FIXED +#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_GMI_RD_PRI_URGENCY +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_GMI_WR_PRI_URGENCY +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_GMI_RD_PRI_URGENCY_MASKING +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA0_GMI_WR_PRI_URGENCY_MASKING +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA0_GMI_RD_PRI_QUANT_PRI1 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_RD_PRI_QUANT_PRI2 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_RD_PRI_QUANT_PRI3 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_WR_PRI_QUANT_PRI1 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_WR_PRI_QUANT_PRI2 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_GMI_WR_PRI_QUANT_PRI3 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_ADDRNORM_BASE_ADDR0 +#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR0 +#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_BASE_ADDR1 +#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR1 +#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_OFFSET_ADDR1 +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA0_ADDRNORM_BASE_ADDR2 +#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR2 +#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_BASE_ADDR3 +#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR3 +#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_OFFSET_ADDR3 +#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA0_ADDRNORM_BASE_ADDR4 +#define MMEA0_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR4 +#define MMEA0_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_BASE_ADDR5 +#define MMEA0_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA0_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA0_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA0_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA0_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_LIMIT_ADDR5 +#define MMEA0_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA0_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc +#define MMEA0_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA0_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA0_ADDRNORM_OFFSET_ADDR5 +#define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA0_ADDRNORMDRAM_HOLE_CNTL +#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA0_ADDRNORMGMI_HOLE_CNTL +#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA0_ADDRDEC_BANK_CFG +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA0_ADDRDEC_MISC_CFG +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA0_ADDRDECGMI_ADDR_HASH_BANK0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECGMI_ADDR_HASH_BANK1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECGMI_ADDR_HASH_BANK2 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECGMI_ADDR_HASH_BANK3 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECGMI_ADDR_HASH_BANK4 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECGMI_ADDR_HASH_BANK5 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECGMI_ADDR_HASH_PC +#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA0_ADDRDECGMI_ADDR_HASH_PC2 +#define MMEA0_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA0_ADDRDECGMI_ADDR_HASH_CS0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDECGMI_ADDR_HASH_CS1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDECGMI_HARVEST_ENABLE +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA0_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA0_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA0_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC0_RM_SEL_CS01 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_CS23 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA0_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA0_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC1_RM_SEL_CS01 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_CS23 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA0_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA0_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA0_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA0_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA0_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA0_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA0_ADDRDEC2_RM_SEL_CS01 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC2_RM_SEL_CS23 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA0_ADDRNORMDRAM_GLOBAL_CNTL +#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA0_ADDRNORMGMI_GLOBAL_CNTL +#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA0_IO_RD_CLI2GRP_MAP0 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_IO_RD_CLI2GRP_MAP1 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_IO_WR_CLI2GRP_MAP0 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA0_IO_WR_CLI2GRP_MAP1 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA0_IO_RD_COMBINE_FLUSH +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA0_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA0_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA0_IO_WR_COMBINE_FLUSH +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA0_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA0_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA0_IO_GROUP_BURST +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_AGE +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_IO_WR_PRI_AGE +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA0_IO_RD_PRI_QUEUING +#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_WR_PRI_QUEUING +#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_RD_PRI_FIXED +#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_WR_PRI_FIXED +#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA0_IO_RD_PRI_URGENCY +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_IO_WR_PRI_URGENCY +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA0_IO_RD_PRI_URGENCY_MASKING +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA0_IO_WR_PRI_URGENCY_MASKING +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA0_IO_RD_PRI_QUANT_PRI1 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_QUANT_PRI2 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_RD_PRI_QUANT_PRI3 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI1 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI2 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_IO_WR_PRI_QUANT_PRI3 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA0_SDP_ARB_DRAM +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA0_SDP_ARB_GMI +#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA0_SDP_ARB_FINAL +#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +//MMEA0_SDP_DRAM_PRIORITY +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA0_SDP_GMI_PRIORITY +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA0_SDP_IO_PRIORITY +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA0_SDP_CREDITS +#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA0_SDP_TAG_RESERVE0 +#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA0_SDP_TAG_RESERVE1 +#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA0_SDP_VCC_RESERVE0 +#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA0_SDP_VCC_RESERVE1 +#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA0_SDP_VCD_RESERVE0 +#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA0_SDP_VCD_RESERVE1 +#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA0_SDP_REQ_CNTL +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +//MMEA0_MISC +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA0_LATENCY_SAMPLING +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA0_PERFCOUNTER_LO +#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA0_PERFCOUNTER_HI +#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA0_PERFCOUNTER0_CFG +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA0_PERFCOUNTER1_CFG +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA0_PERFCOUNTER_RSLT_CNTL +#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA0_EDC_CNT +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA0_EDC_CNT2 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA0_DSM_CNTL +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA0_DSM_CNTLA +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA0_DSM_CNTL2 +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA0_DSM_CNTL2A +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA0_CGTT_CLK_CTRL +#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA0_EDC_MODE +#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA0_ERR_STATUS +#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA0_MISC2 +#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +//MMEA0_ADDRDEC_SELECT +#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA0_EDC_CNT3 +#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA0_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 +#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc +#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA0_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L +#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L + + +// addressBlock: mmhub_ea_mmeadec1 +//MMEA1_DRAM_RD_CLI2GRP_MAP0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_RD_CLI2GRP_MAP1 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_WR_CLI2GRP_MAP0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_WR_CLI2GRP_MAP1 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_DRAM_RD_GRP2VC_MAP +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_DRAM_WR_GRP2VC_MAP +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_DRAM_RD_LAZY +#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA1_DRAM_WR_LAZY +#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA1_DRAM_RD_CAM_CNTL +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA1_DRAM_WR_CAM_CNTL +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA1_DRAM_PAGE_BURST +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_AGE +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_DRAM_WR_PRI_AGE +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_DRAM_RD_PRI_QUEUING +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_WR_PRI_QUEUING +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_RD_PRI_FIXED +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_WR_PRI_FIXED +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_DRAM_RD_PRI_URGENCY +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_DRAM_WR_PRI_URGENCY +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_RD_CLI2GRP_MAP0 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_GMI_RD_CLI2GRP_MAP1 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_GMI_WR_CLI2GRP_MAP0 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_GMI_WR_CLI2GRP_MAP1 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_GMI_RD_GRP2VC_MAP +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_GMI_WR_GRP2VC_MAP +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA1_GMI_RD_LAZY +#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA1_GMI_WR_LAZY +#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA1_GMI_RD_CAM_CNTL +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA1_GMI_WR_CAM_CNTL +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA1_GMI_PAGE_BURST +#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA1_GMI_RD_PRI_AGE +#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_GMI_WR_PRI_AGE +#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_GMI_RD_PRI_QUEUING +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_GMI_WR_PRI_QUEUING +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_GMI_RD_PRI_FIXED +#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_GMI_WR_PRI_FIXED +#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_GMI_RD_PRI_URGENCY +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_GMI_WR_PRI_URGENCY +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_GMI_RD_PRI_URGENCY_MASKING +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA1_GMI_WR_PRI_URGENCY_MASKING +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA1_GMI_RD_PRI_QUANT_PRI1 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_RD_PRI_QUANT_PRI2 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_RD_PRI_QUANT_PRI3 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_WR_PRI_QUANT_PRI1 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_WR_PRI_QUANT_PRI2 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_GMI_WR_PRI_QUANT_PRI3 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_ADDRNORM_BASE_ADDR0 +#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR0 +#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_BASE_ADDR1 +#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR1 +#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_OFFSET_ADDR1 +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA1_ADDRNORM_BASE_ADDR2 +#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR2 +#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_BASE_ADDR3 +#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR3 +#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_OFFSET_ADDR3 +#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA1_ADDRNORM_BASE_ADDR4 +#define MMEA1_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR4 +#define MMEA1_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_BASE_ADDR5 +#define MMEA1_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA1_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA1_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA1_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA1_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_LIMIT_ADDR5 +#define MMEA1_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA1_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc +#define MMEA1_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA1_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA1_ADDRNORM_OFFSET_ADDR5 +#define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA1_ADDRNORMDRAM_HOLE_CNTL +#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA1_ADDRNORMGMI_HOLE_CNTL +#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA1_ADDRDEC_BANK_CFG +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA1_ADDRDEC_MISC_CFG +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA1_ADDRDECGMI_ADDR_HASH_BANK0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECGMI_ADDR_HASH_BANK1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECGMI_ADDR_HASH_BANK2 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECGMI_ADDR_HASH_BANK3 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECGMI_ADDR_HASH_BANK4 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECGMI_ADDR_HASH_BANK5 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECGMI_ADDR_HASH_PC +#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA1_ADDRDECGMI_ADDR_HASH_PC2 +#define MMEA1_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA1_ADDRDECGMI_ADDR_HASH_CS0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDECGMI_ADDR_HASH_CS1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDECGMI_HARVEST_ENABLE +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA1_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA1_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA1_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC0_RM_SEL_CS01 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_CS23 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA1_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA1_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC1_RM_SEL_CS01 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_CS23 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA1_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA1_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA1_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA1_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA1_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA1_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA1_ADDRDEC2_RM_SEL_CS01 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC2_RM_SEL_CS23 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA1_ADDRNORMDRAM_GLOBAL_CNTL +#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA1_ADDRNORMGMI_GLOBAL_CNTL +#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA1_IO_RD_CLI2GRP_MAP0 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_IO_RD_CLI2GRP_MAP1 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_IO_WR_CLI2GRP_MAP0 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA1_IO_WR_CLI2GRP_MAP1 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA1_IO_RD_COMBINE_FLUSH +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA1_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA1_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA1_IO_WR_COMBINE_FLUSH +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA1_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA1_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA1_IO_GROUP_BURST +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_AGE +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_IO_WR_PRI_AGE +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA1_IO_RD_PRI_QUEUING +#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_WR_PRI_QUEUING +#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_RD_PRI_FIXED +#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_WR_PRI_FIXED +#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA1_IO_RD_PRI_URGENCY +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_IO_WR_PRI_URGENCY +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA1_IO_RD_PRI_URGENCY_MASKING +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA1_IO_WR_PRI_URGENCY_MASKING +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA1_IO_RD_PRI_QUANT_PRI1 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_QUANT_PRI2 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_RD_PRI_QUANT_PRI3 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI1 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI2 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_IO_WR_PRI_QUANT_PRI3 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA1_SDP_ARB_DRAM +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA1_SDP_ARB_GMI +#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA1_SDP_ARB_FINAL +#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +//MMEA1_SDP_DRAM_PRIORITY +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA1_SDP_GMI_PRIORITY +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA1_SDP_IO_PRIORITY +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA1_SDP_CREDITS +#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA1_SDP_TAG_RESERVE0 +#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA1_SDP_TAG_RESERVE1 +#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA1_SDP_VCC_RESERVE0 +#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA1_SDP_VCC_RESERVE1 +#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA1_SDP_VCD_RESERVE0 +#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA1_SDP_VCD_RESERVE1 +#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA1_SDP_REQ_CNTL +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +//MMEA1_MISC +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA1_LATENCY_SAMPLING +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA1_PERFCOUNTER_LO +#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA1_PERFCOUNTER_HI +#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA1_PERFCOUNTER0_CFG +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA1_PERFCOUNTER1_CFG +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA1_PERFCOUNTER_RSLT_CNTL +#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA1_EDC_CNT +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA1_EDC_CNT2 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA1_DSM_CNTL +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA1_DSM_CNTLA +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA1_DSM_CNTL2 +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA1_DSM_CNTL2A +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA1_CGTT_CLK_CTRL +#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA1_EDC_MODE +#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA1_ERR_STATUS +#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA1_MISC2 +#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA1_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +//MMEA1_ADDRDEC_SELECT +#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA1_EDC_CNT3 +#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA1_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 +#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc +#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA1_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L +#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L + + +// addressBlock: mmhub_ea_mmeadec2 +//MMEA2_DRAM_RD_CLI2GRP_MAP0 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_DRAM_RD_CLI2GRP_MAP1 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_DRAM_WR_CLI2GRP_MAP0 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_DRAM_WR_CLI2GRP_MAP1 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_DRAM_RD_GRP2VC_MAP +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA2_DRAM_WR_GRP2VC_MAP +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA2_DRAM_RD_LAZY +#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA2_DRAM_WR_LAZY +#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA2_DRAM_RD_CAM_CNTL +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA2_DRAM_WR_CAM_CNTL +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA2_DRAM_PAGE_BURST +#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA2_DRAM_RD_PRI_AGE +#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_DRAM_WR_PRI_AGE +#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_DRAM_RD_PRI_QUEUING +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_DRAM_WR_PRI_QUEUING +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_DRAM_RD_PRI_FIXED +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_DRAM_WR_PRI_FIXED +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_DRAM_RD_PRI_URGENCY +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_DRAM_WR_PRI_URGENCY +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_RD_CLI2GRP_MAP0 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_GMI_RD_CLI2GRP_MAP1 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_GMI_WR_CLI2GRP_MAP0 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_GMI_WR_CLI2GRP_MAP1 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_GMI_RD_GRP2VC_MAP +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA2_GMI_WR_GRP2VC_MAP +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA2_GMI_RD_LAZY +#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA2_GMI_WR_LAZY +#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA2_GMI_RD_CAM_CNTL +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA2_GMI_WR_CAM_CNTL +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA2_GMI_PAGE_BURST +#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA2_GMI_RD_PRI_AGE +#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_GMI_WR_PRI_AGE +#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_GMI_RD_PRI_QUEUING +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_GMI_WR_PRI_QUEUING +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_GMI_RD_PRI_FIXED +#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_GMI_WR_PRI_FIXED +#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_GMI_RD_PRI_URGENCY +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_GMI_WR_PRI_URGENCY +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_GMI_RD_PRI_URGENCY_MASKING +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA2_GMI_WR_PRI_URGENCY_MASKING +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA2_GMI_RD_PRI_QUANT_PRI1 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_RD_PRI_QUANT_PRI2 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_RD_PRI_QUANT_PRI3 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_WR_PRI_QUANT_PRI1 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_WR_PRI_QUANT_PRI2 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_GMI_WR_PRI_QUANT_PRI3 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_ADDRNORM_BASE_ADDR0 +#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR0 +#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_BASE_ADDR1 +#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR1 +#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_OFFSET_ADDR1 +#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA2_ADDRNORM_BASE_ADDR2 +#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR2 +#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_BASE_ADDR3 +#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR3 +#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_OFFSET_ADDR3 +#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA2_ADDRNORM_BASE_ADDR4 +#define MMEA2_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR4 +#define MMEA2_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_BASE_ADDR5 +#define MMEA2_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA2_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA2_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA2_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA2_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_LIMIT_ADDR5 +#define MMEA2_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA2_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc +#define MMEA2_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA2_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA2_ADDRNORM_OFFSET_ADDR5 +#define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA2_ADDRNORMDRAM_HOLE_CNTL +#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA2_ADDRNORMGMI_HOLE_CNTL +#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA2_ADDRDEC_BANK_CFG +#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA2_ADDRDEC_MISC_CFG +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA2_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA2_ADDRDECGMI_ADDR_HASH_BANK0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECGMI_ADDR_HASH_BANK1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECGMI_ADDR_HASH_BANK2 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECGMI_ADDR_HASH_BANK3 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECGMI_ADDR_HASH_BANK4 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECGMI_ADDR_HASH_BANK5 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECGMI_ADDR_HASH_PC +#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA2_ADDRDECGMI_ADDR_HASH_PC2 +#define MMEA2_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA2_ADDRDECGMI_ADDR_HASH_CS0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDECGMI_ADDR_HASH_CS1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDECGMI_HARVEST_ENABLE +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA2_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA2_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA2_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC0_RM_SEL_CS01 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC0_RM_SEL_CS23 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA2_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA2_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC1_RM_SEL_CS01 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC1_RM_SEL_CS23 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA2_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA2_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA2_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA2_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA2_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA2_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA2_ADDRDEC2_RM_SEL_CS01 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC2_RM_SEL_CS23 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA2_ADDRNORMDRAM_GLOBAL_CNTL +#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA2_ADDRNORMGMI_GLOBAL_CNTL +#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA2_IO_RD_CLI2GRP_MAP0 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_IO_RD_CLI2GRP_MAP1 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_IO_WR_CLI2GRP_MAP0 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA2_IO_WR_CLI2GRP_MAP1 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA2_IO_RD_COMBINE_FLUSH +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA2_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA2_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA2_IO_WR_COMBINE_FLUSH +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA2_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA2_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA2_IO_GROUP_BURST +#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA2_IO_RD_PRI_AGE +#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_IO_WR_PRI_AGE +#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA2_IO_RD_PRI_QUEUING +#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_IO_WR_PRI_QUEUING +#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA2_IO_RD_PRI_FIXED +#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_IO_WR_PRI_FIXED +#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA2_IO_RD_PRI_URGENCY +#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_IO_WR_PRI_URGENCY +#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA2_IO_RD_PRI_URGENCY_MASKING +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA2_IO_WR_PRI_URGENCY_MASKING +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA2_IO_RD_PRI_QUANT_PRI1 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_RD_PRI_QUANT_PRI2 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_RD_PRI_QUANT_PRI3 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_WR_PRI_QUANT_PRI1 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_WR_PRI_QUANT_PRI2 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_IO_WR_PRI_QUANT_PRI3 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA2_SDP_ARB_DRAM +#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA2_SDP_ARB_GMI +#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA2_SDP_ARB_FINAL +#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +//MMEA2_SDP_DRAM_PRIORITY +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA2_SDP_GMI_PRIORITY +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA2_SDP_IO_PRIORITY +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA2_SDP_CREDITS +#define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA2_SDP_TAG_RESERVE0 +#define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA2_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA2_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA2_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA2_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA2_SDP_TAG_RESERVE1 +#define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA2_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA2_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA2_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA2_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA2_SDP_VCC_RESERVE0 +#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA2_SDP_VCC_RESERVE1 +#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA2_SDP_VCD_RESERVE0 +#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA2_SDP_VCD_RESERVE1 +#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA2_SDP_REQ_CNTL +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +//MMEA2_MISC +#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA2_LATENCY_SAMPLING +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA2_PERFCOUNTER_LO +#define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA2_PERFCOUNTER_HI +#define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA2_PERFCOUNTER0_CFG +#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA2_PERFCOUNTER1_CFG +#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA2_PERFCOUNTER_RSLT_CNTL +#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA2_EDC_CNT +#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA2_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA2_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA2_EDC_CNT2 +#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA2_DSM_CNTL +#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA2_DSM_CNTLA +#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA2_DSM_CNTL2 +#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA2_DSM_CNTL2A +#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA2_CGTT_CLK_CTRL +#define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA2_EDC_MODE +#define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA2_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA2_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA2_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA2_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA2_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA2_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA2_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA2_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA2_ERR_STATUS +#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA2_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA2_MISC2 +#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA2_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +//MMEA2_ADDRDEC_SELECT +#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA2_EDC_CNT3 +#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA2_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 +#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc +#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA2_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L +#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L + + +// addressBlock: mmhub_ea_mmeadec3 +//MMEA3_DRAM_RD_CLI2GRP_MAP0 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_DRAM_RD_CLI2GRP_MAP1 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_DRAM_WR_CLI2GRP_MAP0 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_DRAM_WR_CLI2GRP_MAP1 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_DRAM_RD_GRP2VC_MAP +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA3_DRAM_WR_GRP2VC_MAP +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA3_DRAM_RD_LAZY +#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA3_DRAM_WR_LAZY +#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA3_DRAM_RD_CAM_CNTL +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA3_DRAM_WR_CAM_CNTL +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA3_DRAM_PAGE_BURST +#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA3_DRAM_RD_PRI_AGE +#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_DRAM_WR_PRI_AGE +#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_DRAM_RD_PRI_QUEUING +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_DRAM_WR_PRI_QUEUING +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_DRAM_RD_PRI_FIXED +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_DRAM_WR_PRI_FIXED +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_DRAM_RD_PRI_URGENCY +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_DRAM_WR_PRI_URGENCY +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_RD_CLI2GRP_MAP0 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_GMI_RD_CLI2GRP_MAP1 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_GMI_WR_CLI2GRP_MAP0 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_GMI_WR_CLI2GRP_MAP1 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_GMI_RD_GRP2VC_MAP +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA3_GMI_WR_GRP2VC_MAP +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA3_GMI_RD_LAZY +#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA3_GMI_WR_LAZY +#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA3_GMI_RD_CAM_CNTL +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA3_GMI_WR_CAM_CNTL +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA3_GMI_PAGE_BURST +#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA3_GMI_RD_PRI_AGE +#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_GMI_WR_PRI_AGE +#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_GMI_RD_PRI_QUEUING +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_GMI_WR_PRI_QUEUING +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_GMI_RD_PRI_FIXED +#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_GMI_WR_PRI_FIXED +#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_GMI_RD_PRI_URGENCY +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_GMI_WR_PRI_URGENCY +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_GMI_RD_PRI_URGENCY_MASKING +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA3_GMI_WR_PRI_URGENCY_MASKING +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA3_GMI_RD_PRI_QUANT_PRI1 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_RD_PRI_QUANT_PRI2 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_RD_PRI_QUANT_PRI3 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_WR_PRI_QUANT_PRI1 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_WR_PRI_QUANT_PRI2 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_GMI_WR_PRI_QUANT_PRI3 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_ADDRNORM_BASE_ADDR0 +#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR0 +#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_BASE_ADDR1 +#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR1 +#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_OFFSET_ADDR1 +#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA3_ADDRNORM_BASE_ADDR2 +#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR2 +#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_BASE_ADDR3 +#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR3 +#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_OFFSET_ADDR3 +#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA3_ADDRNORM_BASE_ADDR4 +#define MMEA3_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR4 +#define MMEA3_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_BASE_ADDR5 +#define MMEA3_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA3_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA3_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA3_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA3_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_LIMIT_ADDR5 +#define MMEA3_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA3_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc +#define MMEA3_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA3_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA3_ADDRNORM_OFFSET_ADDR5 +#define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA3_ADDRNORMDRAM_HOLE_CNTL +#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA3_ADDRNORMGMI_HOLE_CNTL +#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA3_ADDRDEC_BANK_CFG +#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA3_ADDRDEC_MISC_CFG +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA3_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA3_ADDRDECGMI_ADDR_HASH_BANK0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECGMI_ADDR_HASH_BANK1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECGMI_ADDR_HASH_BANK2 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECGMI_ADDR_HASH_BANK3 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECGMI_ADDR_HASH_BANK4 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECGMI_ADDR_HASH_BANK5 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECGMI_ADDR_HASH_PC +#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA3_ADDRDECGMI_ADDR_HASH_PC2 +#define MMEA3_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA3_ADDRDECGMI_ADDR_HASH_CS0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDECGMI_ADDR_HASH_CS1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDECGMI_HARVEST_ENABLE +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA3_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA3_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA3_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC0_RM_SEL_CS01 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC0_RM_SEL_CS23 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA3_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA3_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC1_RM_SEL_CS01 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC1_RM_SEL_CS23 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA3_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA3_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA3_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA3_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA3_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA3_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA3_ADDRDEC2_RM_SEL_CS01 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC2_RM_SEL_CS23 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA3_ADDRNORMDRAM_GLOBAL_CNTL +#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA3_ADDRNORMGMI_GLOBAL_CNTL +#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA3_IO_RD_CLI2GRP_MAP0 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_IO_RD_CLI2GRP_MAP1 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_IO_WR_CLI2GRP_MAP0 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA3_IO_WR_CLI2GRP_MAP1 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA3_IO_RD_COMBINE_FLUSH +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA3_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA3_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA3_IO_WR_COMBINE_FLUSH +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA3_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA3_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA3_IO_GROUP_BURST +#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA3_IO_RD_PRI_AGE +#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_IO_WR_PRI_AGE +#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA3_IO_RD_PRI_QUEUING +#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_IO_WR_PRI_QUEUING +#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA3_IO_RD_PRI_FIXED +#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_IO_WR_PRI_FIXED +#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA3_IO_RD_PRI_URGENCY +#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_IO_WR_PRI_URGENCY +#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA3_IO_RD_PRI_URGENCY_MASKING +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA3_IO_WR_PRI_URGENCY_MASKING +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA3_IO_RD_PRI_QUANT_PRI1 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_RD_PRI_QUANT_PRI2 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_RD_PRI_QUANT_PRI3 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_WR_PRI_QUANT_PRI1 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_WR_PRI_QUANT_PRI2 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_IO_WR_PRI_QUANT_PRI3 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA3_SDP_ARB_DRAM +#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA3_SDP_ARB_GMI +#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA3_SDP_ARB_FINAL +#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +//MMEA3_SDP_DRAM_PRIORITY +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA3_SDP_GMI_PRIORITY +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA3_SDP_IO_PRIORITY +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA3_SDP_CREDITS +#define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA3_SDP_TAG_RESERVE0 +#define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA3_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA3_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA3_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA3_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA3_SDP_TAG_RESERVE1 +#define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA3_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA3_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA3_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA3_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA3_SDP_VCC_RESERVE0 +#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA3_SDP_VCC_RESERVE1 +#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA3_SDP_VCD_RESERVE0 +#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA3_SDP_VCD_RESERVE1 +#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA3_SDP_REQ_CNTL +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +//MMEA3_MISC +#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA3_LATENCY_SAMPLING +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA3_PERFCOUNTER_LO +#define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA3_PERFCOUNTER_HI +#define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA3_PERFCOUNTER0_CFG +#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA3_PERFCOUNTER1_CFG +#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA3_PERFCOUNTER_RSLT_CNTL +#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA3_EDC_CNT +#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA3_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA3_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA3_EDC_CNT2 +#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA3_DSM_CNTL +#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA3_DSM_CNTLA +#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA3_DSM_CNTL2 +#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA3_DSM_CNTL2A +#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA3_CGTT_CLK_CTRL +#define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA3_EDC_MODE +#define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA3_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA3_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA3_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA3_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA3_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA3_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA3_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA3_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA3_ERR_STATUS +#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA3_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA3_MISC2 +#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA3_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +//MMEA3_ADDRDEC_SELECT +#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA3_EDC_CNT3 +#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA3_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 +#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc +#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA3_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L +#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L + + +// addressBlock: mmhub_ea_mmeadec4 +//MMEA4_DRAM_RD_CLI2GRP_MAP0 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_DRAM_RD_CLI2GRP_MAP1 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_DRAM_WR_CLI2GRP_MAP0 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_DRAM_WR_CLI2GRP_MAP1 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_DRAM_RD_GRP2VC_MAP +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA4_DRAM_WR_GRP2VC_MAP +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA4_DRAM_RD_LAZY +#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA4_DRAM_WR_LAZY +#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA4_DRAM_RD_CAM_CNTL +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA4_DRAM_WR_CAM_CNTL +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA4_DRAM_PAGE_BURST +#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA4_DRAM_RD_PRI_AGE +#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_DRAM_WR_PRI_AGE +#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_DRAM_RD_PRI_QUEUING +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_DRAM_WR_PRI_QUEUING +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_DRAM_RD_PRI_FIXED +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_DRAM_WR_PRI_FIXED +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_DRAM_RD_PRI_URGENCY +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_DRAM_WR_PRI_URGENCY +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_RD_CLI2GRP_MAP0 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_GMI_RD_CLI2GRP_MAP1 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_GMI_WR_CLI2GRP_MAP0 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_GMI_WR_CLI2GRP_MAP1 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_GMI_RD_GRP2VC_MAP +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA4_GMI_WR_GRP2VC_MAP +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA4_GMI_RD_LAZY +#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA4_GMI_WR_LAZY +#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA4_GMI_RD_CAM_CNTL +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA4_GMI_WR_CAM_CNTL +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA4_GMI_PAGE_BURST +#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA4_GMI_RD_PRI_AGE +#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_GMI_WR_PRI_AGE +#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_GMI_RD_PRI_QUEUING +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_GMI_WR_PRI_QUEUING +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_GMI_RD_PRI_FIXED +#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_GMI_WR_PRI_FIXED +#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_GMI_RD_PRI_URGENCY +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_GMI_WR_PRI_URGENCY +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_GMI_RD_PRI_URGENCY_MASKING +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA4_GMI_WR_PRI_URGENCY_MASKING +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA4_GMI_RD_PRI_QUANT_PRI1 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_RD_PRI_QUANT_PRI2 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_RD_PRI_QUANT_PRI3 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_WR_PRI_QUANT_PRI1 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_WR_PRI_QUANT_PRI2 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_GMI_WR_PRI_QUANT_PRI3 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_ADDRNORM_BASE_ADDR0 +#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR0 +#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_BASE_ADDR1 +#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR1 +#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_OFFSET_ADDR1 +#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA4_ADDRNORM_BASE_ADDR2 +#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR2 +#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_BASE_ADDR3 +#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR3 +#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_OFFSET_ADDR3 +#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA4_ADDRNORM_BASE_ADDR4 +#define MMEA4_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR4 +#define MMEA4_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_BASE_ADDR5 +#define MMEA4_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA4_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA4_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA4_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA4_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_LIMIT_ADDR5 +#define MMEA4_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA4_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc +#define MMEA4_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA4_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA4_ADDRNORM_OFFSET_ADDR5 +#define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA4_ADDRNORMDRAM_HOLE_CNTL +#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA4_ADDRNORMGMI_HOLE_CNTL +#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA4_ADDRDEC_BANK_CFG +#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA4_ADDRDEC_MISC_CFG +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA4_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA4_ADDRDECGMI_ADDR_HASH_BANK0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECGMI_ADDR_HASH_BANK1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECGMI_ADDR_HASH_BANK2 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECGMI_ADDR_HASH_BANK3 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECGMI_ADDR_HASH_BANK4 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECGMI_ADDR_HASH_BANK5 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECGMI_ADDR_HASH_PC +#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA4_ADDRDECGMI_ADDR_HASH_PC2 +#define MMEA4_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA4_ADDRDECGMI_ADDR_HASH_CS0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDECGMI_ADDR_HASH_CS1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDECGMI_HARVEST_ENABLE +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA4_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA4_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA4_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC0_RM_SEL_CS01 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC0_RM_SEL_CS23 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA4_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA4_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC1_RM_SEL_CS01 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC1_RM_SEL_CS23 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA4_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA4_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA4_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA4_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA4_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA4_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA4_ADDRDEC2_RM_SEL_CS01 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC2_RM_SEL_CS23 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA4_ADDRNORMDRAM_GLOBAL_CNTL +#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA4_ADDRNORMGMI_GLOBAL_CNTL +#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA4_IO_RD_CLI2GRP_MAP0 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_IO_RD_CLI2GRP_MAP1 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_IO_WR_CLI2GRP_MAP0 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA4_IO_WR_CLI2GRP_MAP1 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA4_IO_RD_COMBINE_FLUSH +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA4_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA4_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA4_IO_WR_COMBINE_FLUSH +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA4_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA4_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA4_IO_GROUP_BURST +#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA4_IO_RD_PRI_AGE +#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_IO_WR_PRI_AGE +#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA4_IO_RD_PRI_QUEUING +#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_IO_WR_PRI_QUEUING +#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA4_IO_RD_PRI_FIXED +#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_IO_WR_PRI_FIXED +#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA4_IO_RD_PRI_URGENCY +#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_IO_WR_PRI_URGENCY +#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA4_IO_RD_PRI_URGENCY_MASKING +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA4_IO_WR_PRI_URGENCY_MASKING +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA4_IO_RD_PRI_QUANT_PRI1 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_RD_PRI_QUANT_PRI2 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_RD_PRI_QUANT_PRI3 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_WR_PRI_QUANT_PRI1 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_WR_PRI_QUANT_PRI2 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_IO_WR_PRI_QUANT_PRI3 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA4_SDP_ARB_DRAM +#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA4_SDP_ARB_GMI +#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA4_SDP_ARB_FINAL +#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +//MMEA4_SDP_DRAM_PRIORITY +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA4_SDP_GMI_PRIORITY +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA4_SDP_IO_PRIORITY +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA4_SDP_CREDITS +#define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA4_SDP_TAG_RESERVE0 +#define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA4_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA4_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA4_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA4_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA4_SDP_TAG_RESERVE1 +#define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA4_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA4_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA4_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA4_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA4_SDP_VCC_RESERVE0 +#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA4_SDP_VCC_RESERVE1 +#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA4_SDP_VCD_RESERVE0 +#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA4_SDP_VCD_RESERVE1 +#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA4_SDP_REQ_CNTL +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +//MMEA4_MISC +#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA4_LATENCY_SAMPLING +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA4_PERFCOUNTER_LO +#define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA4_PERFCOUNTER_HI +#define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA4_PERFCOUNTER0_CFG +#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA4_PERFCOUNTER1_CFG +#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA4_PERFCOUNTER_RSLT_CNTL +#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA4_EDC_CNT +#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA4_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA4_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA4_EDC_CNT2 +#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA4_DSM_CNTL +#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA4_DSM_CNTLA +#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA4_DSM_CNTL2 +#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA4_DSM_CNTL2A +#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA4_CGTT_CLK_CTRL +#define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA4_EDC_MODE +#define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA4_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA4_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA4_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA4_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA4_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA4_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA4_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA4_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA4_ERR_STATUS +#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA4_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA4_MISC2 +#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA4_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +//MMEA4_ADDRDEC_SELECT +#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA4_EDC_CNT3 +#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA4_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 +#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc +#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA4_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L +#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L + + +// addressBlock: mmhub_pctldec0 +//PCTL0_CTRL +#define PCTL0_CTRL__PG_ENABLE__SHIFT 0x0 +#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 +#define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x4 +#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x10 +#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT 0x11 +#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT 0x12 +#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT 0x13 +#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT 0x14 +#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT 0x15 +#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT 0x16 +#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT 0x17 +#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT 0x18 +#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT 0x19 +#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT 0x1a +#define PCTL0_CTRL__PGFSM_CMD_STATUS__SHIFT 0x1b +#define PCTL0_CTRL__PG_ENABLE_MASK 0x00000001L +#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL +#define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x000007F0L +#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0000F800L +#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00010000L +#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK 0x00020000L +#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK 0x00040000L +#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK 0x00080000L +#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK 0x00100000L +#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK 0x00200000L +#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK 0x00400000L +#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK 0x00800000L +#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK 0x01000000L +#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK 0x02000000L +#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK 0x04000000L +#define PCTL0_CTRL__PGFSM_CMD_STATUS_MASK 0x18000000L +//PCTL0_MMHUB_DEEPSLEEP_IB +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L +//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L +//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L +#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L +//PCTL0_PG_IGNORE_DEEPSLEEP +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 +#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L +#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L +//PCTL0_PG_IGNORE_DEEPSLEEP_IB +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L +//PCTL0_SLICE0_CFG_DAGB_BUSY +#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE0_CFG_DS_ALLOW +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE0_CFG_DS_ALLOW_IB +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE1_CFG_DAGB_BUSY +#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE1_CFG_DS_ALLOW +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE1_CFG_DS_ALLOW_IB +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE2_CFG_DAGB_BUSY +#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE2_CFG_DS_ALLOW +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE2_CFG_DS_ALLOW_IB +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE3_CFG_DAGB_BUSY +#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE3_CFG_DS_ALLOW +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE3_CFG_DS_ALLOW_IB +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_SLICE4_CFG_DAGB_BUSY +#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL0_SLICE4_CFG_DS_ALLOW +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL0_SLICE4_CFG_DS_ALLOW_IB +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL0_UTCL2_MISC +#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb +#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc +#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf +#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L +#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L +#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L +#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L +#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE0_MISC +#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE1_MISC +#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE2_MISC +#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE3_MISC +#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_SLICE4_MISC +#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL0_UTCL2_RENG_EXECUTE +#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd +#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL +#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L +//PCTL0_SLICE0_RENG_EXECUTE +#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL0_SLICE1_RENG_EXECUTE +#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL0_SLICE2_RENG_EXECUTE +#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL0_SLICE3_RENG_EXECUTE +#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL0_SLICE4_RENG_EXECUTE +#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL0_UTCL2_RENG_RAM_INDEX +#define PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL +//PCTL0_UTCL2_RENG_RAM_DATA +#define PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL0_SLICE0_RENG_RAM_INDEX +#define PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL0_SLICE0_RENG_RAM_DATA +#define PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL0_SLICE1_RENG_RAM_INDEX +#define PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL0_SLICE1_RENG_RAM_DATA +#define PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL0_SLICE2_RENG_RAM_INDEX +#define PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL0_SLICE2_RENG_RAM_DATA +#define PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL0_SLICE3_RENG_RAM_INDEX +#define PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL0_SLICE3_RENG_RAM_DATA +#define PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL0_SLICE4_RENG_RAM_INDEX +#define PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL0_SLICE4_RENG_RAM_DATA +#define PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L + + +// addressBlock: mmhub_l1tlb_vml1dec +//VML1_0_MC_VM_MX_L1_TLB0_STATUS +#define VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_0_MC_VM_MX_L1_TLB1_STATUS +#define VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_0_MC_VM_MX_L1_TLB2_STATUS +#define VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_0_MC_VM_MX_L1_TLB3_STATUS +#define VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_0_MC_VM_MX_L1_TLB4_STATUS +#define VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 +#define VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L +#define VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_0_MC_VM_MX_L1_TLB5_STATUS +#define VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 +#define VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L +#define VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_0_MC_VM_MX_L1_TLB6_STATUS +#define VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 +#define VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L +#define VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_0_MC_VM_MX_L1_TLB7_STATUS +#define VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 +#define VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L +#define VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L + + +// addressBlock: mmhub_l1tlb_vml1pldec +//VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_l1tlb_vml1prdec +//VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO +#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI +#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_atcl2dec +//ATCL2_0_ATC_L2_CNTL +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf +#define ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 +#define ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L +#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L +#define ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L +#define ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L +//ATCL2_0_ATC_L2_CNTL2 +#define ATCL2_0_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 +#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 +#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc +#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf +#define ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT 0x15 +#define ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT 0x1b +#define ATCL2_0_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L +#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L +#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L +#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L +#define ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK 0x07E00000L +#define ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK 0x08000000L +//ATCL2_0_ATC_L2_CACHE_DATA0 +#define ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 +#define ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL +#define ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L +//ATCL2_0_ATC_L2_CACHE_DATA1 +#define ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//ATCL2_0_ATC_L2_CACHE_DATA2 +#define ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATCL2_0_ATC_L2_CNTL3 +#define ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 +#define ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 +#define ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L +#define ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L +#define ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L +//ATCL2_0_ATC_L2_STATUS +#define ATCL2_0_ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 +#define ATCL2_0_ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x7FFFFFFEL +//ATCL2_0_ATC_L2_STATUS2 +#define ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 +#define ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 +#define ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL +#define ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L +//ATCL2_0_ATC_L2_STATUS3 +#define ATCL2_0_ATC_L2_STATUS3__BUSY__SHIFT 0x0 +#define ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT 0x1 +#define ATCL2_0_ATC_L2_STATUS3__BUSY_MASK 0x00000001L +#define ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK 0x7FFFFFFEL +//ATCL2_0_ATC_L2_MISC_CG +#define ATCL2_0_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATCL2_0_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATCL2_0_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//ATCL2_0_ATC_L2_MEM_POWER_LS +#define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATCL2_0_ATC_L2_CGTT_CLK_CTRL +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATCL2_0_ATC_L2_CNTL4 +#define ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES +#define ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_utcl2_vml2pfdec +//VML2PF0_VM_L2_CNTL +#define VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//VML2PF0_VM_L2_CNTL2 +#define VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//VML2PF0_VM_L2_CNTL3 +#define VML2PF0_VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VML2PF0_VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//VML2PF0_VM_L2_STATUS +#define VML2PF0_VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define VML2PF0_VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL +#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//VML2PF0_VM_L2_PROTECTION_FAULT_CNTL +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3 +#define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4 +#define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VML2PF0_VM_L2_PROTECTION_FAULT_STATUS +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +//VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32 +#define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32 +#define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//VML2PF0_VM_L2_CNTL4 +#define VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +//VML2PF0_VM_L2_MM_GROUP_RT_CLASSES +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VML2PF0_VM_L2_CACHE_PARITY_CNTL +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//VML2PF0_VM_L2_CGTT_CLK_CTRL +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + + +// addressBlock: mmhub_utcl2_vml2vcdec +//VML2VC0_VM_CONTEXT0_CNTL +#define VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT1_CNTL +#define VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT2_CNTL +#define VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT3_CNTL +#define VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT4_CNTL +#define VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT5_CNTL +#define VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT6_CNTL +#define VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT7_CNTL +#define VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT8_CNTL +#define VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT9_CNTL +#define VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT10_CNTL +#define VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT11_CNTL +#define VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT12_CNTL +#define VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT13_CNTL +#define VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT14_CNTL +#define VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXT15_CNTL +#define VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC0_VM_CONTEXTS_DISABLE +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//VML2VC0_VM_INVALIDATE_ENG0_SEM +#define VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG1_SEM +#define VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG2_SEM +#define VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG3_SEM +#define VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG4_SEM +#define VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG5_SEM +#define VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG6_SEM +#define VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG7_SEM +#define VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG8_SEM +#define VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG9_SEM +#define VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG10_SEM +#define VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG11_SEM +#define VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG12_SEM +#define VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG13_SEM +#define VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG14_SEM +#define VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG15_SEM +#define VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG16_SEM +#define VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG17_SEM +#define VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC0_VM_INVALIDATE_ENG0_REQ +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG1_REQ +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG2_REQ +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG3_REQ +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG4_REQ +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG5_REQ +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG6_REQ +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG7_REQ +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG8_REQ +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG9_REQ +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG10_REQ +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG11_REQ +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG12_REQ +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG13_REQ +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG14_REQ +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG15_REQ +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG16_REQ +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG17_REQ +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC0_VM_INVALIDATE_ENG0_ACK +#define VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG1_ACK +#define VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG2_ACK +#define VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG3_ACK +#define VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG4_ACK +#define VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG5_ACK +#define VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG6_ACK +#define VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG7_ACK +#define VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG8_ACK +#define VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG9_ACK +#define VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG10_ACK +#define VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG11_ACK +#define VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG12_ACK +#define VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG13_ACK +#define VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG14_ACK +#define VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG15_ACK +#define VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG16_ACK +#define VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG17_ACK +#define VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL + + +// addressBlock: mmhub_utcl2_vmsharedpfdec +//VMSHAREDPF0_MC_VM_NB_MMIOBASE +#define VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//VMSHAREDPF0_MC_VM_NB_MMIOLIMIT +#define VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//VMSHAREDPF0_MC_VM_NB_PCI_CTRL +#define VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//VMSHAREDPF0_MC_VM_NB_PCI_ARB +#define VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1 +#define VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2 +#define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2 +#define VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL +//VMSHAREDPF0_MC_VM_FB_OFFSET +#define VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//VMSHAREDPF0_MC_VM_STEERING +#define VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ +#define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//VMSHAREDPF0_MC_MEM_POWER_LS +#define VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START +#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END +#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//VMSHAREDPF0_MC_VM_APT_CNTL +#define VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +//VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START +#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END +#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL +#define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +#define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL +#define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L +//VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE +#define VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL +//VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL +#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 +#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L + + +// addressBlock: mmhub_utcl2_vmsharedvcdec +//VMSHAREDVC0_MC_VM_FB_LOCATION_BASE +#define VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//VMSHAREDVC0_MC_VM_FB_LOCATION_TOP +#define VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//VMSHAREDVC0_MC_VM_AGP_TOP +#define VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//VMSHAREDVC0_MC_VM_AGP_BOT +#define VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//VMSHAREDVC0_MC_VM_AGP_BASE +#define VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR +#define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L +#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L + + +// addressBlock: mmhub_utcl2_vmsharedhvdec +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1 +#define VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 +#define VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L +//VMSHAREDHV0_MC_VM_MARC_BASE_LO_0 +#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_BASE_LO_1 +#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_BASE_LO_2 +#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_BASE_LO_3 +#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_BASE_HI_0 +#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_BASE_HI_1 +#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_BASE_HI_2 +#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_BASE_HI_3 +#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L +#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_LEN_LO_0 +#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_LEN_LO_1 +#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_LEN_LO_2 +#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_LEN_LO_3 +#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L +//VMSHAREDHV0_MC_VM_MARC_LEN_HI_0 +#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_LEN_HI_1 +#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_LEN_HI_2 +#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL +//VMSHAREDHV0_MC_VM_MARC_LEN_HI_3 +#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL +//VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER +#define VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15 +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID +#define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L +#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec +//ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO +#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI +#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec +//ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_utcl2_vml2pldec +//VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_utcl2_vml2prdec +//VML2PR0_MC_VM_L2_PERFCOUNTER_LO +#define VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//VML2PR0_MC_VM_L2_PERFCOUNTER_HI +#define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_dagb_dagbdec5 +//DAGB5_RDCLI0 +#define DAGB5_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI1 +#define DAGB5_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI2 +#define DAGB5_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI3 +#define DAGB5_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI4 +#define DAGB5_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI5 +#define DAGB5_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI6 +#define DAGB5_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI7 +#define DAGB5_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI8 +#define DAGB5_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI9 +#define DAGB5_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI10 +#define DAGB5_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI11 +#define DAGB5_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI12 +#define DAGB5_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI13 +#define DAGB5_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI14 +#define DAGB5_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB5_RDCLI15 +#define DAGB5_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB5_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB5_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB5_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB5_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB5_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB5_RD_CNTL +#define DAGB5_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB5_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB5_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB5_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB5_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB5_RD_GMI_CNTL +#define DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB5_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB5_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB5_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB5_RD_ADDR_DAGB +#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB5_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB5_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB5_RD_CGTT_CLK_CTRL +#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB5_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB5_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB5_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB5_RD_VC0_CNTL +#define DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC1_CNTL +#define DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC2_CNTL +#define DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC3_CNTL +#define DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC4_CNTL +#define DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC5_CNTL +#define DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC6_CNTL +#define DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_VC7_CNTL +#define DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_RD_CNTL_MISC +#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB5_RD_TLB_CREDIT +#define DAGB5_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB5_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB5_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB5_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB5_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB5_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB5_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB5_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB5_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB5_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB5_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB5_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB5_RDCLI_ASK_PENDING +#define DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_GO_PENDING +#define DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_GBLSEND_PENDING +#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_TLB_PENDING +#define DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_OARB_PENDING +#define DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_RDCLI_OSD_PENDING +#define DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI0 +#define DAGB5_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI1 +#define DAGB5_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI2 +#define DAGB5_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI3 +#define DAGB5_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI4 +#define DAGB5_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI5 +#define DAGB5_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI6 +#define DAGB5_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI7 +#define DAGB5_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI8 +#define DAGB5_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI9 +#define DAGB5_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI10 +#define DAGB5_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI11 +#define DAGB5_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI12 +#define DAGB5_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI13 +#define DAGB5_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI14 +#define DAGB5_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB5_WRCLI15 +#define DAGB5_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB5_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB5_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB5_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB5_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB5_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB5_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB5_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB5_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB5_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB5_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB5_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB5_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB5_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB5_WR_CNTL +#define DAGB5_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB5_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB5_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB5_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB5_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB5_WR_GMI_CNTL +#define DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB5_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB5_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB5_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB5_WR_ADDR_DAGB +#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB5_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB5_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB5_WR_CGTT_CLK_CTRL +#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB5_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB5_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB5_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB5_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB5_WR_DATA_DAGB +#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB5_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB5_WR_DATA_DAGB_MAX_BURST0 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB5_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB5_WR_DATA_DAGB_MAX_BURST1 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB5_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB5_WR_VC0_CNTL +#define DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC1_CNTL +#define DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC2_CNTL +#define DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC3_CNTL +#define DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC4_CNTL +#define DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC5_CNTL +#define DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC6_CNTL +#define DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_VC7_CNTL +#define DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB5_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB5_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB5_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB5_WR_CNTL_MISC +#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB5_WR_TLB_CREDIT +#define DAGB5_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB5_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB5_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB5_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB5_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB5_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB5_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB5_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB5_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB5_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB5_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB5_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB5_WR_DATA_CREDIT +#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB5_WR_MISC_CREDIT +#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB5_WRCLI_ASK_PENDING +#define DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_GO_PENDING +#define DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_GBLSEND_PENDING +#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_TLB_PENDING +#define DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_OARB_PENDING +#define DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_OSD_PENDING +#define DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_DBUS_ASK_PENDING +#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_WRCLI_DBUS_GO_PENDING +#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB5_DAGB_DLY +#define DAGB5_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB5_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB5_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB5_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB5_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB5_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB5_CNTL_MISC +#define DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB5_CNTL_MISC2 +#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB5_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB5_FIFO_EMPTY +#define DAGB5_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB5_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB5_FIFO_FULL +#define DAGB5_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB5_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB5_WR_CREDITS_FULL +#define DAGB5_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB5_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB5_RD_CREDITS_FULL +#define DAGB5_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB5_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB5_PERFCOUNTER_LO +#define DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB5_PERFCOUNTER_HI +#define DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB5_PERFCOUNTER0_CFG +#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB5_PERFCOUNTER1_CFG +#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB5_PERFCOUNTER2_CFG +#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB5_PERFCOUNTER_RSLT_CNTL +#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB5_RESERVE0 +#define DAGB5_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE1 +#define DAGB5_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE2 +#define DAGB5_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE3 +#define DAGB5_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE4 +#define DAGB5_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE5 +#define DAGB5_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE6 +#define DAGB5_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE7 +#define DAGB5_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE8 +#define DAGB5_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE9 +#define DAGB5_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE10 +#define DAGB5_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE11 +#define DAGB5_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE12 +#define DAGB5_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB5_RESERVE13 +#define DAGB5_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB5_RESERVE13__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec6 +//DAGB6_RDCLI0 +#define DAGB6_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI1 +#define DAGB6_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI2 +#define DAGB6_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI3 +#define DAGB6_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI4 +#define DAGB6_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI5 +#define DAGB6_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI6 +#define DAGB6_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI7 +#define DAGB6_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI8 +#define DAGB6_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI9 +#define DAGB6_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI10 +#define DAGB6_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI11 +#define DAGB6_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI12 +#define DAGB6_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI13 +#define DAGB6_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI14 +#define DAGB6_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB6_RDCLI15 +#define DAGB6_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB6_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB6_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB6_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB6_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB6_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB6_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB6_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB6_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB6_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB6_RD_CNTL +#define DAGB6_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB6_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB6_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB6_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB6_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB6_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB6_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB6_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB6_RD_GMI_CNTL +#define DAGB6_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB6_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB6_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB6_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB6_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB6_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB6_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB6_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB6_RD_ADDR_DAGB +#define DAGB6_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB6_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB6_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB6_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB6_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB6_RD_CGTT_CLK_CTRL +#define DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB6_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB6_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB6_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB6_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB6_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB6_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB6_RD_VC0_CNTL +#define DAGB6_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_RD_VC1_CNTL +#define DAGB6_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_RD_VC2_CNTL +#define DAGB6_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_RD_VC3_CNTL +#define DAGB6_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_RD_VC4_CNTL +#define DAGB6_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_RD_VC5_CNTL +#define DAGB6_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_RD_VC6_CNTL +#define DAGB6_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_RD_VC7_CNTL +#define DAGB6_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_RD_CNTL_MISC +#define DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB6_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB6_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB6_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB6_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB6_RD_TLB_CREDIT +#define DAGB6_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB6_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB6_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB6_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB6_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB6_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB6_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB6_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB6_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB6_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB6_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB6_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB6_RDCLI_ASK_PENDING +#define DAGB6_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_RDCLI_GO_PENDING +#define DAGB6_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_RDCLI_GBLSEND_PENDING +#define DAGB6_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_RDCLI_TLB_PENDING +#define DAGB6_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_RDCLI_OARB_PENDING +#define DAGB6_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_RDCLI_OSD_PENDING +#define DAGB6_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_WRCLI0 +#define DAGB6_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI1 +#define DAGB6_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI2 +#define DAGB6_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI3 +#define DAGB6_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI4 +#define DAGB6_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI5 +#define DAGB6_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI6 +#define DAGB6_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI7 +#define DAGB6_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI8 +#define DAGB6_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI9 +#define DAGB6_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI10 +#define DAGB6_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI11 +#define DAGB6_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI12 +#define DAGB6_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI13 +#define DAGB6_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI14 +#define DAGB6_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB6_WRCLI15 +#define DAGB6_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB6_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB6_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB6_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB6_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB6_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB6_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB6_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB6_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB6_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB6_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB6_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB6_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB6_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB6_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB6_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB6_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB6_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB6_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB6_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB6_WR_CNTL +#define DAGB6_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB6_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB6_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB6_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB6_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB6_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB6_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB6_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB6_WR_GMI_CNTL +#define DAGB6_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB6_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB6_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB6_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB6_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB6_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB6_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB6_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB6_WR_ADDR_DAGB +#define DAGB6_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB6_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB6_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB6_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB6_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB6_WR_CGTT_CLK_CTRL +#define DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB6_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB6_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB6_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB6_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB6_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB6_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB6_WR_DATA_DAGB +#define DAGB6_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB6_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB6_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB6_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB6_WR_DATA_DAGB_MAX_BURST0 +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB6_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB6_WR_DATA_DAGB_MAX_BURST1 +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB6_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB6_WR_VC0_CNTL +#define DAGB6_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_WR_VC1_CNTL +#define DAGB6_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_WR_VC2_CNTL +#define DAGB6_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_WR_VC3_CNTL +#define DAGB6_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_WR_VC4_CNTL +#define DAGB6_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_WR_VC5_CNTL +#define DAGB6_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_WR_VC6_CNTL +#define DAGB6_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_WR_VC7_CNTL +#define DAGB6_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB6_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB6_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB6_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB6_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB6_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB6_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB6_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB6_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB6_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB6_WR_CNTL_MISC +#define DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB6_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB6_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB6_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB6_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB6_WR_TLB_CREDIT +#define DAGB6_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB6_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB6_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB6_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB6_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB6_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB6_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB6_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB6_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB6_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB6_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB6_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB6_WR_DATA_CREDIT +#define DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB6_WR_MISC_CREDIT +#define DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB6_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB6_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB6_WRCLI_ASK_PENDING +#define DAGB6_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_WRCLI_GO_PENDING +#define DAGB6_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_WRCLI_GBLSEND_PENDING +#define DAGB6_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_WRCLI_TLB_PENDING +#define DAGB6_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_WRCLI_OARB_PENDING +#define DAGB6_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_WRCLI_OSD_PENDING +#define DAGB6_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_WRCLI_DBUS_ASK_PENDING +#define DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_WRCLI_DBUS_GO_PENDING +#define DAGB6_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB6_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB6_DAGB_DLY +#define DAGB6_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB6_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB6_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB6_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB6_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB6_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB6_CNTL_MISC +#define DAGB6_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB6_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB6_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB6_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB6_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB6_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB6_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB6_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB6_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB6_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB6_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB6_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB6_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB6_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB6_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB6_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB6_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB6_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB6_CNTL_MISC2 +#define DAGB6_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB6_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB6_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB6_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB6_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB6_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB6_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB6_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB6_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB6_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB6_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB6_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB6_FIFO_EMPTY +#define DAGB6_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB6_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB6_FIFO_FULL +#define DAGB6_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB6_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB6_WR_CREDITS_FULL +#define DAGB6_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB6_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB6_RD_CREDITS_FULL +#define DAGB6_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB6_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB6_PERFCOUNTER_LO +#define DAGB6_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB6_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB6_PERFCOUNTER_HI +#define DAGB6_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB6_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB6_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB6_PERFCOUNTER0_CFG +#define DAGB6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB6_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB6_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB6_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB6_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB6_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB6_PERFCOUNTER1_CFG +#define DAGB6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB6_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB6_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB6_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB6_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB6_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB6_PERFCOUNTER2_CFG +#define DAGB6_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB6_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB6_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB6_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB6_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB6_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB6_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB6_PERFCOUNTER_RSLT_CNTL +#define DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB6_RESERVE0 +#define DAGB6_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE1 +#define DAGB6_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE2 +#define DAGB6_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE3 +#define DAGB6_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE4 +#define DAGB6_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE5 +#define DAGB6_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE6 +#define DAGB6_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE7 +#define DAGB6_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE8 +#define DAGB6_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE9 +#define DAGB6_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE10 +#define DAGB6_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE11 +#define DAGB6_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE12 +#define DAGB6_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB6_RESERVE13 +#define DAGB6_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB6_RESERVE13__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_dagb_dagbdec7 +//DAGB7_RDCLI0 +#define DAGB7_RDCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI0__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI0__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI0__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI1 +#define DAGB7_RDCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI1__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI1__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI1__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI2 +#define DAGB7_RDCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI2__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI2__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI2__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI3 +#define DAGB7_RDCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI3__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI3__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI3__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI4 +#define DAGB7_RDCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI4__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI4__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI4__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI5 +#define DAGB7_RDCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI5__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI5__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI5__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI6 +#define DAGB7_RDCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI6__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI6__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI6__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI7 +#define DAGB7_RDCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI7__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI7__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI7__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI8 +#define DAGB7_RDCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI8__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI8__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI8__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI9 +#define DAGB7_RDCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI9__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI9__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI9__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI10 +#define DAGB7_RDCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI10__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI10__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI10__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI11 +#define DAGB7_RDCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI11__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI11__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI11__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI12 +#define DAGB7_RDCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI12__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI12__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI12__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI13 +#define DAGB7_RDCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI13__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI13__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI13__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI14 +#define DAGB7_RDCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI14__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI14__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI14__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB7_RDCLI15 +#define DAGB7_RDCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_RDCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB7_RDCLI15__URG_LOW__SHIFT 0x8 +#define DAGB7_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_RDCLI15__MAX_BW__SHIFT 0xd +#define DAGB7_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_RDCLI15__MIN_BW__SHIFT 0x16 +#define DAGB7_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_RDCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB7_RDCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_RDCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB7_RDCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB7_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_RDCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB7_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_RDCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB7_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_RDCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB7_RD_CNTL +#define DAGB7_RD_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB7_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB7_RD_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB7_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB7_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB7_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB7_RD_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB7_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB7_RD_GMI_CNTL +#define DAGB7_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB7_RD_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB7_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB7_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB7_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB7_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB7_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB7_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB7_RD_ADDR_DAGB +#define DAGB7_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB7_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB7_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB7_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB7_RD_OUTPUT_DAGB_MAX_BURST +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB7_RD_CGTT_CLK_CTRL +#define DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB7_L1TLB_RD_CGTT_CLK_CTRL +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB7_ATCVM_RD_CGTT_CLK_CTRL +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB7_RD_ADDR_DAGB_MAX_BURST0 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB7_RD_ADDR_DAGB_LAZY_TIMER0 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB7_RD_ADDR_DAGB_MAX_BURST1 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB7_RD_ADDR_DAGB_LAZY_TIMER1 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB7_RD_VC0_CNTL +#define DAGB7_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_RD_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_RD_VC1_CNTL +#define DAGB7_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_RD_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_RD_VC2_CNTL +#define DAGB7_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_RD_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_RD_VC3_CNTL +#define DAGB7_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_RD_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_RD_VC4_CNTL +#define DAGB7_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_RD_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_RD_VC5_CNTL +#define DAGB7_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_RD_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_RD_VC6_CNTL +#define DAGB7_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_RD_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_RD_VC7_CNTL +#define DAGB7_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_RD_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_RD_CNTL_MISC +#define DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB7_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB7_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB7_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB7_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB7_RD_TLB_CREDIT +#define DAGB7_RD_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB7_RD_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB7_RD_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB7_RD_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB7_RD_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB7_RD_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB7_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB7_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB7_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB7_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB7_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB7_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB7_RDCLI_ASK_PENDING +#define DAGB7_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_RDCLI_GO_PENDING +#define DAGB7_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_RDCLI_GBLSEND_PENDING +#define DAGB7_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_RDCLI_TLB_PENDING +#define DAGB7_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_RDCLI_OARB_PENDING +#define DAGB7_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_RDCLI_OSD_PENDING +#define DAGB7_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_WRCLI0 +#define DAGB7_WRCLI0__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI0__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI0__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI0__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI0__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI0__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI0__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI0__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI0__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI0__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI0__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI0__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI1 +#define DAGB7_WRCLI1__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI1__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI1__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI1__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI1__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI1__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI1__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI1__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI1__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI1__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI1__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI1__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI2 +#define DAGB7_WRCLI2__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI2__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI2__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI2__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI2__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI2__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI2__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI2__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI2__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI2__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI2__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI2__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI3 +#define DAGB7_WRCLI3__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI3__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI3__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI3__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI3__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI3__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI3__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI3__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI3__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI3__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI3__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI3__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI4 +#define DAGB7_WRCLI4__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI4__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI4__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI4__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI4__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI4__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI4__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI4__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI4__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI4__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI4__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI4__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI5 +#define DAGB7_WRCLI5__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI5__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI5__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI5__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI5__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI5__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI5__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI5__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI5__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI5__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI5__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI5__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI6 +#define DAGB7_WRCLI6__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI6__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI6__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI6__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI6__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI6__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI6__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI6__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI6__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI6__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI6__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI6__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI7 +#define DAGB7_WRCLI7__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI7__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI7__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI7__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI7__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI7__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI7__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI7__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI7__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI7__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI7__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI7__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI8 +#define DAGB7_WRCLI8__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI8__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI8__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI8__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI8__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI8__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI8__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI8__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI8__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI8__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI8__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI8__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI9 +#define DAGB7_WRCLI9__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI9__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI9__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI9__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI9__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI9__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI9__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI9__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI9__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI9__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI9__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI9__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI10 +#define DAGB7_WRCLI10__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI10__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI10__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI10__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI10__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI10__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI10__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI10__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI10__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI10__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI10__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI10__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI11 +#define DAGB7_WRCLI11__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI11__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI11__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI11__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI11__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI11__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI11__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI11__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI11__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI11__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI11__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI11__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI12 +#define DAGB7_WRCLI12__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI12__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI12__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI12__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI12__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI12__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI12__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI12__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI12__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI12__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI12__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI12__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI13 +#define DAGB7_WRCLI13__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI13__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI13__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI13__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI13__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI13__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI13__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI13__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI13__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI13__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI13__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI13__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI14 +#define DAGB7_WRCLI14__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI14__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI14__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI14__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI14__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI14__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI14__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI14__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI14__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI14__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI14__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI14__MAX_OSD_MASK 0xFC000000L +//DAGB7_WRCLI15 +#define DAGB7_WRCLI15__VIRT_CHAN__SHIFT 0x0 +#define DAGB7_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 +#define DAGB7_WRCLI15__URG_HIGH__SHIFT 0x4 +#define DAGB7_WRCLI15__URG_LOW__SHIFT 0x8 +#define DAGB7_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc +#define DAGB7_WRCLI15__MAX_BW__SHIFT 0xd +#define DAGB7_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 +#define DAGB7_WRCLI15__MIN_BW__SHIFT 0x16 +#define DAGB7_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 +#define DAGB7_WRCLI15__MAX_OSD__SHIFT 0x1a +#define DAGB7_WRCLI15__VIRT_CHAN_MASK 0x00000007L +#define DAGB7_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L +#define DAGB7_WRCLI15__URG_HIGH_MASK 0x000000F0L +#define DAGB7_WRCLI15__URG_LOW_MASK 0x00000F00L +#define DAGB7_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L +#define DAGB7_WRCLI15__MAX_BW_MASK 0x001FE000L +#define DAGB7_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L +#define DAGB7_WRCLI15__MIN_BW_MASK 0x01C00000L +#define DAGB7_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L +#define DAGB7_WRCLI15__MAX_OSD_MASK 0xFC000000L +//DAGB7_WR_CNTL +#define DAGB7_WR_CNTL__SCLK_FREQ__SHIFT 0x0 +#define DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 +#define DAGB7_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa +#define DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 +#define DAGB7_WR_CNTL__IO_LEVEL__SHIFT 0x11 +#define DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 +#define DAGB7_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 +#define DAGB7_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL +#define DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L +#define DAGB7_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L +#define DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L +#define DAGB7_WR_CNTL__IO_LEVEL_MASK 0x000E0000L +#define DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L +#define DAGB7_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L +//DAGB7_WR_GMI_CNTL +#define DAGB7_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 +#define DAGB7_WR_GMI_CNTL__LEVEL__SHIFT 0x6 +#define DAGB7_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 +#define DAGB7_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd +#define DAGB7_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL +#define DAGB7_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L +#define DAGB7_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L +#define DAGB7_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L +//DAGB7_WR_ADDR_DAGB +#define DAGB7_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB7_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB7_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB7_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB7_WR_OUTPUT_DAGB_MAX_BURST +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L +#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L +//DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L +#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L +//DAGB7_WR_CGTT_CLK_CTRL +#define DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB7_L1TLB_WR_CGTT_CLK_CTRL +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB7_ATCVM_WR_CGTT_CLK_CTRL +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L +#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L +//DAGB7_WR_ADDR_DAGB_MAX_BURST0 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB7_WR_ADDR_DAGB_LAZY_TIMER0 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB7_WR_ADDR_DAGB_MAX_BURST1 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB7_WR_ADDR_DAGB_LAZY_TIMER1 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB7_WR_DATA_DAGB +#define DAGB7_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 +#define DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 +#define DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 +#define DAGB7_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 +#define DAGB7_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L +#define DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L +#define DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L +#define DAGB7_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L +//DAGB7_WR_DATA_DAGB_MAX_BURST0 +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L +#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L +//DAGB7_WR_DATA_DAGB_LAZY_TIMER0 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L +//DAGB7_WR_DATA_DAGB_MAX_BURST1 +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L +#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L +//DAGB7_WR_DATA_DAGB_LAZY_TIMER1 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L +#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L +//DAGB7_WR_VC0_CNTL +#define DAGB7_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_WR_VC0_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_WR_VC1_CNTL +#define DAGB7_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_WR_VC1_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_WR_VC2_CNTL +#define DAGB7_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_WR_VC2_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_WR_VC3_CNTL +#define DAGB7_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_WR_VC3_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_WR_VC4_CNTL +#define DAGB7_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_WR_VC4_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_WR_VC5_CNTL +#define DAGB7_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_WR_VC5_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_WR_VC6_CNTL +#define DAGB7_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_WR_VC6_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_WR_VC7_CNTL +#define DAGB7_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 +#define DAGB7_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 +#define DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb +#define DAGB7_WR_VC7_CNTL__MAX_BW__SHIFT 0xc +#define DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 +#define DAGB7_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 +#define DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 +#define DAGB7_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 +#define DAGB7_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL +#define DAGB7_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L +#define DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L +#define DAGB7_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L +#define DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L +#define DAGB7_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L +#define DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L +#define DAGB7_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L +//DAGB7_WR_CNTL_MISC +#define DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 +#define DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 +#define DAGB7_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd +#define DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 +#define DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 +#define DAGB7_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 +#define DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a +#define DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL +#define DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L +#define DAGB7_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L +#define DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L +#define DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L +#define DAGB7_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L +#define DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L +//DAGB7_WR_TLB_CREDIT +#define DAGB7_WR_TLB_CREDIT__TLB0__SHIFT 0x0 +#define DAGB7_WR_TLB_CREDIT__TLB1__SHIFT 0x5 +#define DAGB7_WR_TLB_CREDIT__TLB2__SHIFT 0xa +#define DAGB7_WR_TLB_CREDIT__TLB3__SHIFT 0xf +#define DAGB7_WR_TLB_CREDIT__TLB4__SHIFT 0x14 +#define DAGB7_WR_TLB_CREDIT__TLB5__SHIFT 0x19 +#define DAGB7_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL +#define DAGB7_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L +#define DAGB7_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L +#define DAGB7_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L +#define DAGB7_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L +#define DAGB7_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L +//DAGB7_WR_DATA_CREDIT +#define DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 +#define DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 +#define DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 +#define DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 +#define DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL +#define DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L +#define DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L +#define DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L +//DAGB7_WR_MISC_CREDIT +#define DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 +#define DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 +#define DAGB7_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 +#define DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 +#define DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL +#define DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L +#define DAGB7_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L +#define DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L +//DAGB7_WRCLI_ASK_PENDING +#define DAGB7_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_WRCLI_GO_PENDING +#define DAGB7_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_WRCLI_GBLSEND_PENDING +#define DAGB7_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_WRCLI_TLB_PENDING +#define DAGB7_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_WRCLI_OARB_PENDING +#define DAGB7_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_WRCLI_OSD_PENDING +#define DAGB7_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_WRCLI_DBUS_ASK_PENDING +#define DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_WRCLI_DBUS_GO_PENDING +#define DAGB7_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 +#define DAGB7_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL +//DAGB7_DAGB_DLY +#define DAGB7_DAGB_DLY__DLY__SHIFT 0x0 +#define DAGB7_DAGB_DLY__CLI__SHIFT 0x8 +#define DAGB7_DAGB_DLY__POS__SHIFT 0x10 +#define DAGB7_DAGB_DLY__DLY_MASK 0x000000FFL +#define DAGB7_DAGB_DLY__CLI_MASK 0x0000FF00L +#define DAGB7_DAGB_DLY__POS_MASK 0x000F0000L +//DAGB7_CNTL_MISC +#define DAGB7_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 +#define DAGB7_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 +#define DAGB7_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 +#define DAGB7_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 +#define DAGB7_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc +#define DAGB7_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf +#define DAGB7_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 +#define DAGB7_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 +#define DAGB7_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 +#define DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e +#define DAGB7_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L +#define DAGB7_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L +#define DAGB7_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L +#define DAGB7_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L +#define DAGB7_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L +#define DAGB7_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L +#define DAGB7_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L +#define DAGB7_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L +#define DAGB7_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L +#define DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L +//DAGB7_CNTL_MISC2 +#define DAGB7_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 +#define DAGB7_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 +#define DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 +#define DAGB7_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 +#define DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 +#define DAGB7_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 +#define DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 +#define DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 +#define DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 +#define DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 +#define DAGB7_CNTL_MISC2__SWAP_CTL__SHIFT 0xa +#define DAGB7_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb +#define DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 +#define DAGB7_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L +#define DAGB7_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L +#define DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L +#define DAGB7_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L +#define DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L +#define DAGB7_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L +#define DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L +#define DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L +#define DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L +#define DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L +#define DAGB7_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L +#define DAGB7_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L +#define DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L +//DAGB7_FIFO_EMPTY +#define DAGB7_FIFO_EMPTY__EMPTY__SHIFT 0x0 +#define DAGB7_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL +//DAGB7_FIFO_FULL +#define DAGB7_FIFO_FULL__FULL__SHIFT 0x0 +#define DAGB7_FIFO_FULL__FULL_MASK 0x007FFFFFL +//DAGB7_WR_CREDITS_FULL +#define DAGB7_WR_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB7_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL +//DAGB7_RD_CREDITS_FULL +#define DAGB7_RD_CREDITS_FULL__FULL__SHIFT 0x0 +#define DAGB7_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL +//DAGB7_PERFCOUNTER_LO +#define DAGB7_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define DAGB7_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//DAGB7_PERFCOUNTER_HI +#define DAGB7_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define DAGB7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define DAGB7_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define DAGB7_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//DAGB7_PERFCOUNTER0_CFG +#define DAGB7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB7_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define DAGB7_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB7_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB7_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define DAGB7_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//DAGB7_PERFCOUNTER1_CFG +#define DAGB7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB7_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define DAGB7_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB7_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB7_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define DAGB7_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//DAGB7_PERFCOUNTER2_CFG +#define DAGB7_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define DAGB7_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define DAGB7_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define DAGB7_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define DAGB7_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define DAGB7_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define DAGB7_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//DAGB7_PERFCOUNTER_RSLT_CNTL +#define DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//DAGB7_RESERVE0 +#define DAGB7_RESERVE0__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE0__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE1 +#define DAGB7_RESERVE1__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE1__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE2 +#define DAGB7_RESERVE2__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE2__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE3 +#define DAGB7_RESERVE3__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE3__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE4 +#define DAGB7_RESERVE4__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE4__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE5 +#define DAGB7_RESERVE5__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE5__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE6 +#define DAGB7_RESERVE6__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE6__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE7 +#define DAGB7_RESERVE7__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE7__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE8 +#define DAGB7_RESERVE8__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE8__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE9 +#define DAGB7_RESERVE9__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE9__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE10 +#define DAGB7_RESERVE10__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE10__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE11 +#define DAGB7_RESERVE11__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE11__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE12 +#define DAGB7_RESERVE12__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE12__RESERVE_MASK 0xFFFFFFFFL +//DAGB7_RESERVE13 +#define DAGB7_RESERVE13__RESERVE__SHIFT 0x0 +#define DAGB7_RESERVE13__RESERVE_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_ea_mmeadec5 +//MMEA5_DRAM_RD_CLI2GRP_MAP0 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_DRAM_RD_CLI2GRP_MAP1 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_DRAM_WR_CLI2GRP_MAP0 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_DRAM_WR_CLI2GRP_MAP1 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_DRAM_RD_GRP2VC_MAP +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA5_DRAM_WR_GRP2VC_MAP +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA5_DRAM_RD_LAZY +#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA5_DRAM_WR_LAZY +#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA5_DRAM_RD_CAM_CNTL +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA5_DRAM_WR_CAM_CNTL +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA5_DRAM_PAGE_BURST +#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA5_DRAM_RD_PRI_AGE +#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_DRAM_WR_PRI_AGE +#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_DRAM_RD_PRI_QUEUING +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_DRAM_WR_PRI_QUEUING +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_DRAM_RD_PRI_FIXED +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_DRAM_WR_PRI_FIXED +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_DRAM_RD_PRI_URGENCY +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_DRAM_WR_PRI_URGENCY +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_RD_CLI2GRP_MAP0 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_GMI_RD_CLI2GRP_MAP1 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_GMI_WR_CLI2GRP_MAP0 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_GMI_WR_CLI2GRP_MAP1 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_GMI_RD_GRP2VC_MAP +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA5_GMI_WR_GRP2VC_MAP +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA5_GMI_RD_LAZY +#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA5_GMI_WR_LAZY +#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA5_GMI_RD_CAM_CNTL +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA5_GMI_WR_CAM_CNTL +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA5_GMI_PAGE_BURST +#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA5_GMI_RD_PRI_AGE +#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_GMI_WR_PRI_AGE +#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_GMI_RD_PRI_QUEUING +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_GMI_WR_PRI_QUEUING +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_GMI_RD_PRI_FIXED +#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_GMI_WR_PRI_FIXED +#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_GMI_RD_PRI_URGENCY +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_GMI_WR_PRI_URGENCY +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_GMI_RD_PRI_URGENCY_MASKING +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA5_GMI_WR_PRI_URGENCY_MASKING +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA5_GMI_RD_PRI_QUANT_PRI1 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_RD_PRI_QUANT_PRI2 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_RD_PRI_QUANT_PRI3 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_WR_PRI_QUANT_PRI1 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_WR_PRI_QUANT_PRI2 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_GMI_WR_PRI_QUANT_PRI3 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_ADDRNORM_BASE_ADDR0 +#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR0 +#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_BASE_ADDR1 +#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR1 +#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_OFFSET_ADDR1 +#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA5_ADDRNORM_BASE_ADDR2 +#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR2 +#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_BASE_ADDR3 +#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR3 +#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_OFFSET_ADDR3 +#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA5_ADDRNORM_BASE_ADDR4 +#define MMEA5_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR4 +#define MMEA5_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_BASE_ADDR5 +#define MMEA5_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA5_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA5_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA5_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA5_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_LIMIT_ADDR5 +#define MMEA5_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA5_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc +#define MMEA5_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA5_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA5_ADDRNORM_OFFSET_ADDR5 +#define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA5_ADDRNORMDRAM_HOLE_CNTL +#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA5_ADDRNORMGMI_HOLE_CNTL +#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA5_ADDRDEC_BANK_CFG +#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA5_ADDRDEC_MISC_CFG +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA5_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA5_ADDRDECGMI_ADDR_HASH_BANK0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECGMI_ADDR_HASH_BANK1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECGMI_ADDR_HASH_BANK2 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECGMI_ADDR_HASH_BANK3 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECGMI_ADDR_HASH_BANK4 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECGMI_ADDR_HASH_BANK5 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECGMI_ADDR_HASH_PC +#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA5_ADDRDECGMI_ADDR_HASH_PC2 +#define MMEA5_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA5_ADDRDECGMI_ADDR_HASH_CS0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDECGMI_ADDR_HASH_CS1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDECGMI_HARVEST_ENABLE +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA5_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA5_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA5_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC0_RM_SEL_CS01 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC0_RM_SEL_CS23 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA5_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA5_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC1_RM_SEL_CS01 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC1_RM_SEL_CS23 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA5_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA5_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA5_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA5_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA5_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA5_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA5_ADDRDEC2_RM_SEL_CS01 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC2_RM_SEL_CS23 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA5_ADDRNORMDRAM_GLOBAL_CNTL +#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA5_ADDRNORMGMI_GLOBAL_CNTL +#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA5_IO_RD_CLI2GRP_MAP0 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_IO_RD_CLI2GRP_MAP1 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_IO_WR_CLI2GRP_MAP0 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA5_IO_WR_CLI2GRP_MAP1 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA5_IO_RD_COMBINE_FLUSH +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA5_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA5_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA5_IO_WR_COMBINE_FLUSH +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA5_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA5_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA5_IO_GROUP_BURST +#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA5_IO_RD_PRI_AGE +#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_IO_WR_PRI_AGE +#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA5_IO_RD_PRI_QUEUING +#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_IO_WR_PRI_QUEUING +#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA5_IO_RD_PRI_FIXED +#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_IO_WR_PRI_FIXED +#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA5_IO_RD_PRI_URGENCY +#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_IO_WR_PRI_URGENCY +#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA5_IO_RD_PRI_URGENCY_MASKING +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA5_IO_WR_PRI_URGENCY_MASKING +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA5_IO_RD_PRI_QUANT_PRI1 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_RD_PRI_QUANT_PRI2 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_RD_PRI_QUANT_PRI3 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_WR_PRI_QUANT_PRI1 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_WR_PRI_QUANT_PRI2 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_IO_WR_PRI_QUANT_PRI3 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA5_SDP_ARB_DRAM +#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA5_SDP_ARB_GMI +#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA5_SDP_ARB_FINAL +#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +//MMEA5_SDP_DRAM_PRIORITY +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA5_SDP_GMI_PRIORITY +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA5_SDP_IO_PRIORITY +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA5_SDP_CREDITS +#define MMEA5_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA5_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA5_SDP_TAG_RESERVE0 +#define MMEA5_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA5_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA5_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA5_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA5_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA5_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA5_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA5_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA5_SDP_TAG_RESERVE1 +#define MMEA5_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA5_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA5_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA5_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA5_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA5_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA5_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA5_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA5_SDP_VCC_RESERVE0 +#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA5_SDP_VCC_RESERVE1 +#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA5_SDP_VCD_RESERVE0 +#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA5_SDP_VCD_RESERVE1 +#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA5_SDP_REQ_CNTL +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +//MMEA5_MISC +#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA5_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA5_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA5_LATENCY_SAMPLING +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA5_PERFCOUNTER_LO +#define MMEA5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA5_PERFCOUNTER_HI +#define MMEA5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA5_PERFCOUNTER0_CFG +#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA5_PERFCOUNTER1_CFG +#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA5_PERFCOUNTER_RSLT_CNTL +#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA5_EDC_CNT +#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA5_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA5_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA5_EDC_CNT2 +#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA5_DSM_CNTL +#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA5_DSM_CNTLA +#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA5_DSM_CNTL2 +#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA5_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA5_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA5_DSM_CNTL2A +#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA5_CGTT_CLK_CTRL +#define MMEA5_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA5_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA5_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA5_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA5_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA5_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA5_EDC_MODE +#define MMEA5_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA5_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA5_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA5_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA5_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA5_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA5_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA5_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA5_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA5_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA5_ERR_STATUS +#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA5_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA5_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA5_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA5_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA5_MISC2 +#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA5_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA5_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +//MMEA5_ADDRDEC_SELECT +#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA5_EDC_CNT3 +#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA5_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 +#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc +#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA5_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L +#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L + + +// addressBlock: mmhub_ea_mmeadec6 +//MMEA6_DRAM_RD_CLI2GRP_MAP0 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA6_DRAM_RD_CLI2GRP_MAP1 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA6_DRAM_WR_CLI2GRP_MAP0 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA6_DRAM_WR_CLI2GRP_MAP1 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA6_DRAM_RD_GRP2VC_MAP +#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA6_DRAM_WR_GRP2VC_MAP +#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA6_DRAM_RD_LAZY +#define MMEA6_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA6_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA6_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA6_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA6_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA6_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA6_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA6_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA6_DRAM_WR_LAZY +#define MMEA6_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA6_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA6_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA6_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA6_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA6_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA6_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA6_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA6_DRAM_RD_CAM_CNTL +#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA6_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA6_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA6_DRAM_WR_CAM_CNTL +#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA6_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA6_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA6_DRAM_PAGE_BURST +#define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA6_DRAM_RD_PRI_AGE +#define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA6_DRAM_WR_PRI_AGE +#define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA6_DRAM_RD_PRI_QUEUING +#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA6_DRAM_WR_PRI_QUEUING +#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA6_DRAM_RD_PRI_FIXED +#define MMEA6_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA6_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA6_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA6_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA6_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA6_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA6_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA6_DRAM_WR_PRI_FIXED +#define MMEA6_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA6_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA6_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA6_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA6_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA6_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA6_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA6_DRAM_RD_PRI_URGENCY +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA6_DRAM_WR_PRI_URGENCY +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA6_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_GMI_RD_CLI2GRP_MAP0 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA6_GMI_RD_CLI2GRP_MAP1 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA6_GMI_WR_CLI2GRP_MAP0 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA6_GMI_WR_CLI2GRP_MAP1 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA6_GMI_RD_GRP2VC_MAP +#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA6_GMI_WR_GRP2VC_MAP +#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA6_GMI_RD_LAZY +#define MMEA6_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA6_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA6_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA6_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA6_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA6_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA6_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA6_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA6_GMI_WR_LAZY +#define MMEA6_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA6_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA6_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA6_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA6_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA6_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA6_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA6_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA6_GMI_RD_CAM_CNTL +#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA6_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA6_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA6_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA6_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA6_GMI_WR_CAM_CNTL +#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA6_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA6_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA6_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA6_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA6_GMI_PAGE_BURST +#define MMEA6_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA6_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA6_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA6_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA6_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA6_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA6_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA6_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA6_GMI_RD_PRI_AGE +#define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA6_GMI_WR_PRI_AGE +#define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA6_GMI_RD_PRI_QUEUING +#define MMEA6_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA6_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA6_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA6_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA6_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA6_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA6_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA6_GMI_WR_PRI_QUEUING +#define MMEA6_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA6_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA6_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA6_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA6_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA6_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA6_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA6_GMI_RD_PRI_FIXED +#define MMEA6_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA6_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA6_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA6_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA6_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA6_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA6_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA6_GMI_WR_PRI_FIXED +#define MMEA6_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA6_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA6_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA6_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA6_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA6_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA6_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA6_GMI_RD_PRI_URGENCY +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA6_GMI_WR_PRI_URGENCY +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA6_GMI_RD_PRI_URGENCY_MASKING +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA6_GMI_WR_PRI_URGENCY_MASKING +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA6_GMI_RD_PRI_QUANT_PRI1 +#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_GMI_RD_PRI_QUANT_PRI2 +#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_GMI_RD_PRI_QUANT_PRI3 +#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_GMI_WR_PRI_QUANT_PRI1 +#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_GMI_WR_PRI_QUANT_PRI2 +#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_GMI_WR_PRI_QUANT_PRI3 +#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_ADDRNORM_BASE_ADDR0 +#define MMEA6_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA6_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA6_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA6_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA6_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_LIMIT_ADDR0 +#define MMEA6_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA6_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA6_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_BASE_ADDR1 +#define MMEA6_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA6_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA6_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA6_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA6_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_LIMIT_ADDR1 +#define MMEA6_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA6_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA6_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_OFFSET_ADDR1 +#define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA6_ADDRNORM_BASE_ADDR2 +#define MMEA6_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA6_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA6_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA6_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA6_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_LIMIT_ADDR2 +#define MMEA6_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA6_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA6_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_BASE_ADDR3 +#define MMEA6_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA6_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA6_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA6_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA6_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_LIMIT_ADDR3 +#define MMEA6_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA6_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA6_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_OFFSET_ADDR3 +#define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA6_ADDRNORM_BASE_ADDR4 +#define MMEA6_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA6_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA6_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA6_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA6_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_LIMIT_ADDR4 +#define MMEA6_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA6_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA6_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_BASE_ADDR5 +#define MMEA6_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA6_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA6_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA6_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA6_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_LIMIT_ADDR5 +#define MMEA6_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA6_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc +#define MMEA6_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA6_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA6_ADDRNORM_OFFSET_ADDR5 +#define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA6_ADDRNORMDRAM_HOLE_CNTL +#define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA6_ADDRNORMGMI_HOLE_CNTL +#define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA6_ADDRDEC_BANK_CFG +#define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA6_ADDRDEC_MISC_CFG +#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA6_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA6_ADDRDECGMI_ADDR_HASH_BANK0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECGMI_ADDR_HASH_BANK1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECGMI_ADDR_HASH_BANK2 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECGMI_ADDR_HASH_BANK3 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECGMI_ADDR_HASH_BANK4 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECGMI_ADDR_HASH_BANK5 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECGMI_ADDR_HASH_PC +#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA6_ADDRDECGMI_ADDR_HASH_PC2 +#define MMEA6_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA6_ADDRDECGMI_ADDR_HASH_CS0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDECGMI_ADDR_HASH_CS1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDECGMI_HARVEST_ENABLE +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA6_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA6_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA6_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA6_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA6_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA6_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA6_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA6_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA6_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA6_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA6_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA6_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA6_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA6_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA6_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA6_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA6_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA6_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA6_ADDRDEC0_RM_SEL_CS01 +#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC0_RM_SEL_CS23 +#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA6_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA6_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA6_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA6_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA6_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA6_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA6_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA6_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA6_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA6_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA6_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA6_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA6_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA6_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA6_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA6_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA6_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA6_ADDRDEC1_RM_SEL_CS01 +#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC1_RM_SEL_CS23 +#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA6_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA6_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA6_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA6_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA6_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA6_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA6_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA6_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA6_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA6_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA6_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA6_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA6_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA6_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA6_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA6_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA6_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA6_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA6_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA6_ADDRDEC2_RM_SEL_CS01 +#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC2_RM_SEL_CS23 +#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA6_ADDRNORMDRAM_GLOBAL_CNTL +#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA6_ADDRNORMGMI_GLOBAL_CNTL +#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA6_IO_RD_CLI2GRP_MAP0 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA6_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA6_IO_RD_CLI2GRP_MAP1 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA6_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA6_IO_WR_CLI2GRP_MAP0 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA6_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA6_IO_WR_CLI2GRP_MAP1 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA6_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA6_IO_RD_COMBINE_FLUSH +#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA6_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA6_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA6_IO_WR_COMBINE_FLUSH +#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA6_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA6_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA6_IO_GROUP_BURST +#define MMEA6_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA6_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA6_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA6_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA6_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA6_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA6_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA6_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA6_IO_RD_PRI_AGE +#define MMEA6_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA6_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA6_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA6_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA6_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA6_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA6_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA6_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA6_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA6_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA6_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA6_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA6_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA6_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA6_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA6_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA6_IO_WR_PRI_AGE +#define MMEA6_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA6_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA6_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA6_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA6_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA6_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA6_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA6_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA6_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA6_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA6_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA6_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA6_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA6_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA6_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA6_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA6_IO_RD_PRI_QUEUING +#define MMEA6_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA6_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA6_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA6_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA6_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA6_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA6_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA6_IO_WR_PRI_QUEUING +#define MMEA6_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA6_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA6_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA6_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA6_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA6_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA6_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA6_IO_RD_PRI_FIXED +#define MMEA6_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA6_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA6_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA6_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA6_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA6_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA6_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA6_IO_WR_PRI_FIXED +#define MMEA6_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA6_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA6_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA6_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA6_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA6_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA6_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA6_IO_RD_PRI_URGENCY +#define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA6_IO_WR_PRI_URGENCY +#define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA6_IO_RD_PRI_URGENCY_MASKING +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA6_IO_WR_PRI_URGENCY_MASKING +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA6_IO_RD_PRI_QUANT_PRI1 +#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_IO_RD_PRI_QUANT_PRI2 +#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_IO_RD_PRI_QUANT_PRI3 +#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_IO_WR_PRI_QUANT_PRI1 +#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_IO_WR_PRI_QUANT_PRI2 +#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_IO_WR_PRI_QUANT_PRI3 +#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA6_SDP_ARB_DRAM +#define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA6_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA6_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA6_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA6_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA6_SDP_ARB_GMI +#define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA6_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA6_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA6_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA6_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA6_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA6_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA6_SDP_ARB_FINAL +#define MMEA6_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA6_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA6_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA6_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA6_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA6_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA6_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA6_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA6_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA6_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA6_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA6_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA6_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA6_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA6_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +//MMEA6_SDP_DRAM_PRIORITY +#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA6_SDP_GMI_PRIORITY +#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA6_SDP_IO_PRIORITY +#define MMEA6_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA6_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA6_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA6_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA6_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA6_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA6_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA6_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA6_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA6_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA6_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA6_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA6_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA6_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA6_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA6_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA6_SDP_CREDITS +#define MMEA6_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA6_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA6_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA6_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA6_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA6_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA6_SDP_TAG_RESERVE0 +#define MMEA6_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA6_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA6_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA6_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA6_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA6_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA6_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA6_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA6_SDP_TAG_RESERVE1 +#define MMEA6_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA6_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA6_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA6_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA6_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA6_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA6_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA6_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA6_SDP_VCC_RESERVE0 +#define MMEA6_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA6_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA6_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA6_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA6_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA6_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA6_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA6_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA6_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA6_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA6_SDP_VCC_RESERVE1 +#define MMEA6_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA6_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA6_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA6_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA6_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA6_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA6_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA6_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA6_SDP_VCD_RESERVE0 +#define MMEA6_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA6_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA6_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA6_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA6_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA6_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA6_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA6_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA6_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA6_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA6_SDP_VCD_RESERVE1 +#define MMEA6_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA6_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA6_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA6_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA6_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA6_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA6_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA6_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA6_SDP_REQ_CNTL +#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA6_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA6_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +//MMEA6_MISC +#define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA6_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA6_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA6_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA6_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA6_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA6_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA6_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA6_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA6_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA6_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA6_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA6_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA6_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA6_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA6_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA6_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA6_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA6_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA6_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA6_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA6_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA6_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA6_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA6_LATENCY_SAMPLING +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA6_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA6_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA6_PERFCOUNTER_LO +#define MMEA6_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA6_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA6_PERFCOUNTER_HI +#define MMEA6_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA6_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA6_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA6_PERFCOUNTER0_CFG +#define MMEA6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA6_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA6_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA6_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA6_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA6_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA6_PERFCOUNTER1_CFG +#define MMEA6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA6_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA6_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA6_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA6_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA6_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA6_PERFCOUNTER_RSLT_CNTL +#define MMEA6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA6_EDC_CNT +#define MMEA6_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA6_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA6_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA6_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA6_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA6_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA6_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA6_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA6_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA6_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA6_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA6_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA6_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA6_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA6_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA6_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA6_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA6_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA6_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA6_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA6_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA6_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA6_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA6_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA6_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA6_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA6_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA6_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA6_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA6_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA6_EDC_CNT2 +#define MMEA6_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA6_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA6_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA6_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA6_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA6_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA6_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA6_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA6_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA6_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA6_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA6_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA6_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA6_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA6_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA6_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA6_DSM_CNTL +#define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA6_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA6_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA6_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA6_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA6_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA6_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA6_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA6_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA6_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA6_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA6_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA6_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA6_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA6_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA6_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA6_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA6_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA6_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA6_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA6_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA6_DSM_CNTLA +#define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA6_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA6_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA6_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA6_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA6_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA6_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA6_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA6_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA6_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA6_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA6_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA6_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA6_DSM_CNTL2 +#define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA6_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA6_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA6_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA6_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA6_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA6_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA6_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA6_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA6_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA6_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA6_DSM_CNTL2A +#define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA6_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA6_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA6_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA6_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA6_CGTT_CLK_CTRL +#define MMEA6_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA6_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA6_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA6_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA6_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA6_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA6_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA6_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA6_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA6_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA6_EDC_MODE +#define MMEA6_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA6_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA6_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA6_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA6_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA6_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA6_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA6_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA6_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA6_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA6_ERR_STATUS +#define MMEA6_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA6_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA6_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA6_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA6_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA6_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA6_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA6_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA6_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA6_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA6_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA6_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA6_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA6_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA6_MISC2 +#define MMEA6_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA6_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA6_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA6_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA6_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA6_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA6_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA6_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +//MMEA6_ADDRDEC_SELECT +#define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA6_EDC_CNT3 +#define MMEA6_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA6_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA6_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA6_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA6_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 +#define MMEA6_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA6_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc +#define MMEA6_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA6_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA6_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA6_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA6_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L +#define MMEA6_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA6_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L + + +// addressBlock: mmhub_ea_mmeadec7 +//MMEA7_DRAM_RD_CLI2GRP_MAP0 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA7_DRAM_RD_CLI2GRP_MAP1 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA7_DRAM_WR_CLI2GRP_MAP0 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA7_DRAM_WR_CLI2GRP_MAP1 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA7_DRAM_RD_GRP2VC_MAP +#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA7_DRAM_WR_GRP2VC_MAP +#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA7_DRAM_RD_LAZY +#define MMEA7_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA7_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA7_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA7_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA7_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA7_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA7_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA7_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA7_DRAM_WR_LAZY +#define MMEA7_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA7_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA7_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA7_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA7_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA7_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA7_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA7_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA7_DRAM_RD_CAM_CNTL +#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA7_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA7_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA7_DRAM_WR_CAM_CNTL +#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA7_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA7_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +//MMEA7_DRAM_PAGE_BURST +#define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA7_DRAM_RD_PRI_AGE +#define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA7_DRAM_WR_PRI_AGE +#define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA7_DRAM_RD_PRI_QUEUING +#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA7_DRAM_WR_PRI_QUEUING +#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA7_DRAM_RD_PRI_FIXED +#define MMEA7_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA7_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA7_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA7_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA7_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA7_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA7_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA7_DRAM_WR_PRI_FIXED +#define MMEA7_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA7_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA7_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA7_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA7_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA7_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA7_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA7_DRAM_RD_PRI_URGENCY +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA7_DRAM_WR_PRI_URGENCY +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA7_DRAM_RD_PRI_QUANT_PRI1 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_DRAM_RD_PRI_QUANT_PRI2 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_DRAM_RD_PRI_QUANT_PRI3 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_DRAM_WR_PRI_QUANT_PRI1 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_DRAM_WR_PRI_QUANT_PRI2 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_DRAM_WR_PRI_QUANT_PRI3 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_GMI_RD_CLI2GRP_MAP0 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA7_GMI_RD_CLI2GRP_MAP1 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA7_GMI_WR_CLI2GRP_MAP0 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA7_GMI_WR_CLI2GRP_MAP1 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA7_GMI_RD_GRP2VC_MAP +#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA7_GMI_WR_GRP2VC_MAP +#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 +#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 +#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 +#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 +#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L +#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L +#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L +#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L +//MMEA7_GMI_RD_LAZY +#define MMEA7_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA7_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA7_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA7_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA7_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA7_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA7_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA7_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA7_GMI_WR_LAZY +#define MMEA7_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 +#define MMEA7_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 +#define MMEA7_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 +#define MMEA7_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 +#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc +#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 +#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b +#define MMEA7_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L +#define MMEA7_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L +#define MMEA7_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L +#define MMEA7_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L +#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L +#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L +#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L +//MMEA7_GMI_RD_CAM_CNTL +#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA7_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA7_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA7_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA7_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA7_GMI_WR_CAM_CNTL +#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 +#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 +#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 +#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc +#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 +#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 +#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 +#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 +#define MMEA7_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c +#define MMEA7_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d +#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL +#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L +#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L +#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L +#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L +#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L +#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L +#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L +#define MMEA7_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L +#define MMEA7_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L +//MMEA7_GMI_PAGE_BURST +#define MMEA7_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA7_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA7_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA7_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA7_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA7_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA7_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA7_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA7_GMI_RD_PRI_AGE +#define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA7_GMI_WR_PRI_AGE +#define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA7_GMI_RD_PRI_QUEUING +#define MMEA7_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA7_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA7_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA7_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA7_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA7_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA7_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA7_GMI_WR_PRI_QUEUING +#define MMEA7_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA7_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA7_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA7_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA7_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA7_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA7_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA7_GMI_RD_PRI_FIXED +#define MMEA7_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA7_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA7_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA7_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA7_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA7_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA7_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA7_GMI_WR_PRI_FIXED +#define MMEA7_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA7_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA7_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA7_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA7_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA7_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA7_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA7_GMI_RD_PRI_URGENCY +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA7_GMI_WR_PRI_URGENCY +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA7_GMI_RD_PRI_URGENCY_MASKING +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA7_GMI_WR_PRI_URGENCY_MASKING +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA7_GMI_RD_PRI_QUANT_PRI1 +#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_GMI_RD_PRI_QUANT_PRI2 +#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_GMI_RD_PRI_QUANT_PRI3 +#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_GMI_WR_PRI_QUANT_PRI1 +#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_GMI_WR_PRI_QUANT_PRI2 +#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_GMI_WR_PRI_QUANT_PRI3 +#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_ADDRNORM_BASE_ADDR0 +#define MMEA7_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA7_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA7_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA7_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA7_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_LIMIT_ADDR0 +#define MMEA7_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA7_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA7_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_BASE_ADDR1 +#define MMEA7_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA7_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA7_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA7_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA7_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_LIMIT_ADDR1 +#define MMEA7_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA7_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA7_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_OFFSET_ADDR1 +#define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA7_ADDRNORM_BASE_ADDR2 +#define MMEA7_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA7_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA7_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA7_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA7_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_LIMIT_ADDR2 +#define MMEA7_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA7_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA7_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_BASE_ADDR3 +#define MMEA7_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA7_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA7_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA7_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA7_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_LIMIT_ADDR3 +#define MMEA7_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA7_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA7_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_OFFSET_ADDR3 +#define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA7_ADDRNORM_BASE_ADDR4 +#define MMEA7_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA7_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA7_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA7_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA7_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_LIMIT_ADDR4 +#define MMEA7_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA7_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA7_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_BASE_ADDR5 +#define MMEA7_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT 0x0 +#define MMEA7_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT 0x1 +#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT 0x2 +#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT 0x6 +#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT 0x8 +#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT 0x9 +#define MMEA7_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK 0x00000001L +#define MMEA7_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK 0x00000002L +#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK 0x0000003CL +#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK 0x000000C0L +#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK 0x00000100L +#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK 0x00000E00L +#define MMEA7_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_LIMIT_ADDR5 +#define MMEA7_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT 0x0 +#define MMEA7_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT 0xc +#define MMEA7_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK 0x0000001FL +#define MMEA7_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK 0xFFFFF000L +//MMEA7_ADDRNORM_OFFSET_ADDR5 +#define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT 0x0 +#define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT 0x14 +#define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK 0x00000001L +#define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK 0xFFF00000L +//MMEA7_ADDRNORMDRAM_HOLE_CNTL +#define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA7_ADDRNORMGMI_HOLE_CNTL +#define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 +#define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 +#define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L +#define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L +//MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG +#define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 +#define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 +#define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL +#define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L +//MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG +#define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 +#define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 +#define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL +#define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L +//MMEA7_ADDRDEC_BANK_CFG +#define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 +#define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 +#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc +#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf +#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 +#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 +#define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL +#define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L +#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L +#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L +#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L +#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L +//MMEA7_ADDRDEC_MISC_CFG +#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 +#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 +#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 +#define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 +#define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 +#define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc +#define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 +#define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 +#define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 +#define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a +#define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d +#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L +#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L +#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L +#define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L +#define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L +#define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L +#define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L +#define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L +#define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L +#define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L +#define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L +//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECDRAM_ADDR_HASH_PC +#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECDRAM_ADDR_HASH_PC2 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA7_ADDRDECDRAM_ADDR_HASH_CS0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDECDRAM_ADDR_HASH_CS1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDECDRAM_HARVEST_ENABLE +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA7_ADDRDECGMI_ADDR_HASH_BANK0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECGMI_ADDR_HASH_BANK1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECGMI_ADDR_HASH_BANK2 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECGMI_ADDR_HASH_BANK3 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECGMI_ADDR_HASH_BANK4 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECGMI_ADDR_HASH_BANK5 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECGMI_ADDR_HASH_PC +#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe +#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL +#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L +//MMEA7_ADDRDECGMI_ADDR_HASH_PC2 +#define MMEA7_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000003FL +//MMEA7_ADDRDECGMI_ADDR_HASH_CS0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDECGMI_ADDR_HASH_CS1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDECGMI_HARVEST_ENABLE +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L +#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L +//MMEA7_ADDRDEC0_BASE_ADDR_CS0 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_BASE_ADDR_CS1 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_BASE_ADDR_CS2 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_BASE_ADDR_CS3 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_BASE_ADDR_SECCS0 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_BASE_ADDR_SECCS1 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_BASE_ADDR_SECCS2 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_BASE_ADDR_SECCS3 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_ADDR_MASK_CS01 +#define MMEA7_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_ADDR_MASK_CS23 +#define MMEA7_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_ADDR_MASK_SECCS01 +#define MMEA7_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_ADDR_MASK_SECCS23 +#define MMEA7_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC0_ADDR_CFG_CS01 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA7_ADDRDEC0_ADDR_CFG_CS23 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA7_ADDRDEC0_ADDR_SEL_CS01 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA7_ADDRDEC0_ADDR_SEL_CS23 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA7_ADDRDEC0_ADDR_SEL2_CS01 +#define MMEA7_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA7_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA7_ADDRDEC0_ADDR_SEL2_CS23 +#define MMEA7_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA7_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA7_ADDRDEC0_COL_SEL_LO_CS01 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA7_ADDRDEC0_COL_SEL_LO_CS23 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA7_ADDRDEC0_COL_SEL_HI_CS01 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA7_ADDRDEC0_COL_SEL_HI_CS23 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA7_ADDRDEC0_RM_SEL_CS01 +#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC0_RM_SEL_CS23 +#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC0_RM_SEL_SECCS01 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC0_RM_SEL_SECCS23 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC1_BASE_ADDR_CS0 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_BASE_ADDR_CS1 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_BASE_ADDR_CS2 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_BASE_ADDR_CS3 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_BASE_ADDR_SECCS0 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_BASE_ADDR_SECCS1 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_BASE_ADDR_SECCS2 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_BASE_ADDR_SECCS3 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_ADDR_MASK_CS01 +#define MMEA7_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_ADDR_MASK_CS23 +#define MMEA7_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_ADDR_MASK_SECCS01 +#define MMEA7_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_ADDR_MASK_SECCS23 +#define MMEA7_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC1_ADDR_CFG_CS01 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA7_ADDRDEC1_ADDR_CFG_CS23 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA7_ADDRDEC1_ADDR_SEL_CS01 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA7_ADDRDEC1_ADDR_SEL_CS23 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA7_ADDRDEC1_ADDR_SEL2_CS01 +#define MMEA7_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA7_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA7_ADDRDEC1_ADDR_SEL2_CS23 +#define MMEA7_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA7_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA7_ADDRDEC1_COL_SEL_LO_CS01 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA7_ADDRDEC1_COL_SEL_LO_CS23 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA7_ADDRDEC1_COL_SEL_HI_CS01 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA7_ADDRDEC1_COL_SEL_HI_CS23 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA7_ADDRDEC1_RM_SEL_CS01 +#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC1_RM_SEL_CS23 +#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC1_RM_SEL_SECCS01 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC1_RM_SEL_SECCS23 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC2_BASE_ADDR_CS0 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_BASE_ADDR_CS1 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_BASE_ADDR_CS2 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_BASE_ADDR_CS3 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_BASE_ADDR_SECCS0 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_BASE_ADDR_SECCS1 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_BASE_ADDR_SECCS2 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_BASE_ADDR_SECCS3 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L +#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_ADDR_MASK_CS01 +#define MMEA7_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_ADDR_MASK_CS23 +#define MMEA7_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_ADDR_MASK_SECCS01 +#define MMEA7_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_ADDR_MASK_SECCS23 +#define MMEA7_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 +#define MMEA7_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL +//MMEA7_ADDRDEC2_ADDR_CFG_CS01 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L +//MMEA7_ADDRDEC2_ADDR_CFG_CS23 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L +#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L +//MMEA7_ADDRDEC2_ADDR_SEL_CS01 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L +//MMEA7_ADDRDEC2_ADDR_SEL_CS23 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L +#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L +//MMEA7_ADDRDEC2_ADDR_SEL2_CS01 +#define MMEA7_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 +#define MMEA7_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL +//MMEA7_ADDRDEC2_ADDR_SEL2_CS23 +#define MMEA7_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 +#define MMEA7_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL +//MMEA7_ADDRDEC2_COL_SEL_LO_CS01 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L +//MMEA7_ADDRDEC2_COL_SEL_LO_CS23 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L +#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L +//MMEA7_ADDRDEC2_COL_SEL_HI_CS01 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L +//MMEA7_ADDRDEC2_COL_SEL_HI_CS23 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L +#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L +//MMEA7_ADDRDEC2_RM_SEL_CS01 +#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC2_RM_SEL_CS23 +#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC2_RM_SEL_SECCS01 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRDEC2_RM_SEL_SECCS23 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L +#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L +//MMEA7_ADDRNORMDRAM_GLOBAL_CNTL +#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA7_ADDRNORMGMI_GLOBAL_CNTL +#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT 0x14 +#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT 0x15 +#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT 0x16 +#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK 0x00100000L +#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK 0x00200000L +#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK 0x00400000L +//MMEA7_IO_RD_CLI2GRP_MAP0 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA7_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA7_IO_RD_CLI2GRP_MAP1 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA7_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA7_IO_WR_CLI2GRP_MAP0 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L +#define MMEA7_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L +//MMEA7_IO_WR_CLI2GRP_MAP1 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L +#define MMEA7_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L +//MMEA7_IO_RD_COMBINE_FLUSH +#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA7_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA7_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA7_IO_WR_COMBINE_FLUSH +#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 +#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 +#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 +#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc +#define MMEA7_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 +#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL +#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L +#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L +#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L +#define MMEA7_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L +//MMEA7_IO_GROUP_BURST +#define MMEA7_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 +#define MMEA7_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 +#define MMEA7_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 +#define MMEA7_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 +#define MMEA7_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL +#define MMEA7_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L +#define MMEA7_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L +#define MMEA7_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L +//MMEA7_IO_RD_PRI_AGE +#define MMEA7_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA7_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA7_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA7_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA7_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA7_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA7_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA7_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA7_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA7_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA7_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA7_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA7_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA7_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA7_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA7_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA7_IO_WR_PRI_AGE +#define MMEA7_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 +#define MMEA7_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 +#define MMEA7_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 +#define MMEA7_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 +#define MMEA7_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc +#define MMEA7_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf +#define MMEA7_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 +#define MMEA7_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 +#define MMEA7_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L +#define MMEA7_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L +#define MMEA7_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L +#define MMEA7_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L +#define MMEA7_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L +#define MMEA7_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L +#define MMEA7_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L +#define MMEA7_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L +//MMEA7_IO_RD_PRI_QUEUING +#define MMEA7_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA7_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA7_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA7_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA7_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA7_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA7_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA7_IO_WR_PRI_QUEUING +#define MMEA7_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 +#define MMEA7_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 +#define MMEA7_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 +#define MMEA7_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 +#define MMEA7_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L +#define MMEA7_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L +#define MMEA7_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L +//MMEA7_IO_RD_PRI_FIXED +#define MMEA7_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA7_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA7_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA7_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA7_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA7_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA7_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA7_IO_WR_PRI_FIXED +#define MMEA7_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 +#define MMEA7_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 +#define MMEA7_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 +#define MMEA7_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 +#define MMEA7_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L +#define MMEA7_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L +#define MMEA7_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L +//MMEA7_IO_RD_PRI_URGENCY +#define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA7_IO_WR_PRI_URGENCY +#define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 +#define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 +#define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 +#define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 +#define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc +#define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd +#define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe +#define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf +#define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L +#define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L +#define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L +#define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L +#define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L +#define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L +#define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L +#define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L +//MMEA7_IO_RD_PRI_URGENCY_MASKING +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA7_IO_WR_PRI_URGENCY_MASKING +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L +#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L +//MMEA7_IO_RD_PRI_QUANT_PRI1 +#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_IO_RD_PRI_QUANT_PRI2 +#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_IO_RD_PRI_QUANT_PRI3 +#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_IO_WR_PRI_QUANT_PRI1 +#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_IO_WR_PRI_QUANT_PRI2 +#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_IO_WR_PRI_QUANT_PRI3 +#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 +#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 +#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 +#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 +#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL +#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L +#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L +#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L +//MMEA7_SDP_ARB_DRAM +#define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA7_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA7_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA7_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA7_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +//MMEA7_SDP_ARB_GMI +#define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 +#define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 +#define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 +#define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 +#define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 +#define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 +#define MMEA7_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 +#define MMEA7_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 +#define MMEA7_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 +#define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL +#define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L +#define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L +#define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L +#define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L +#define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L +#define MMEA7_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L +#define MMEA7_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L +#define MMEA7_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L +//MMEA7_SDP_ARB_FINAL +#define MMEA7_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define MMEA7_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 +#define MMEA7_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define MMEA7_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 +#define MMEA7_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 +#define MMEA7_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a +#define MMEA7_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b +#define MMEA7_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define MMEA7_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L +#define MMEA7_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define MMEA7_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L +#define MMEA7_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L +#define MMEA7_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L +#define MMEA7_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L +#define MMEA7_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L +//MMEA7_SDP_DRAM_PRIORITY +#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA7_SDP_GMI_PRIORITY +#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA7_SDP_IO_PRIORITY +#define MMEA7_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 +#define MMEA7_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 +#define MMEA7_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 +#define MMEA7_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc +#define MMEA7_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 +#define MMEA7_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 +#define MMEA7_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 +#define MMEA7_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c +#define MMEA7_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL +#define MMEA7_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L +#define MMEA7_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L +#define MMEA7_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L +#define MMEA7_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L +#define MMEA7_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L +#define MMEA7_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L +#define MMEA7_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L +//MMEA7_SDP_CREDITS +#define MMEA7_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define MMEA7_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 +#define MMEA7_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define MMEA7_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL +#define MMEA7_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L +#define MMEA7_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +//MMEA7_SDP_TAG_RESERVE0 +#define MMEA7_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define MMEA7_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 +#define MMEA7_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 +#define MMEA7_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 +#define MMEA7_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL +#define MMEA7_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L +#define MMEA7_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L +#define MMEA7_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L +//MMEA7_SDP_TAG_RESERVE1 +#define MMEA7_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 +#define MMEA7_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 +#define MMEA7_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 +#define MMEA7_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 +#define MMEA7_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL +#define MMEA7_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L +#define MMEA7_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L +#define MMEA7_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L +//MMEA7_SDP_VCC_RESERVE0 +#define MMEA7_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA7_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA7_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA7_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA7_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA7_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA7_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA7_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA7_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA7_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA7_SDP_VCC_RESERVE1 +#define MMEA7_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA7_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA7_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA7_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA7_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA7_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA7_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA7_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA7_SDP_VCD_RESERVE0 +#define MMEA7_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define MMEA7_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define MMEA7_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define MMEA7_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define MMEA7_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define MMEA7_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define MMEA7_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define MMEA7_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define MMEA7_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define MMEA7_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//MMEA7_SDP_VCD_RESERVE1 +#define MMEA7_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define MMEA7_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define MMEA7_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define MMEA7_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define MMEA7_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define MMEA7_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define MMEA7_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define MMEA7_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//MMEA7_SDP_REQ_CNTL +#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 +#define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 +#define MMEA7_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 +#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L +#define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L +#define MMEA7_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L +//MMEA7_MISC +#define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 +#define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 +#define MMEA7_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 +#define MMEA7_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 +#define MMEA7_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 +#define MMEA7_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd +#define MMEA7_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe +#define MMEA7_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf +#define MMEA7_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 +#define MMEA7_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 +#define MMEA7_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 +#define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a +#define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b +#define MMEA7_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c +#define MMEA7_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d +#define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e +#define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f +#define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L +#define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L +#define MMEA7_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L +#define MMEA7_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L +#define MMEA7_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L +#define MMEA7_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L +#define MMEA7_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L +#define MMEA7_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L +#define MMEA7_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L +#define MMEA7_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L +#define MMEA7_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L +#define MMEA7_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L +#define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L +#define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L +#define MMEA7_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L +#define MMEA7_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L +#define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L +#define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L +//MMEA7_LATENCY_SAMPLING +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L +#define MMEA7_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L +#define MMEA7_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L +//MMEA7_PERFCOUNTER_LO +#define MMEA7_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMEA7_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMEA7_PERFCOUNTER_HI +#define MMEA7_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMEA7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMEA7_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMEA7_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMEA7_PERFCOUNTER0_CFG +#define MMEA7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA7_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMEA7_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA7_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA7_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMEA7_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMEA7_PERFCOUNTER1_CFG +#define MMEA7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMEA7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMEA7_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMEA7_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMEA7_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMEA7_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMEA7_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMEA7_PERFCOUNTER_RSLT_CNTL +#define MMEA7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMEA7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMEA7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMEA7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMEA7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMEA7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMEA7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMEA7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA7_EDC_CNT +#define MMEA7_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA7_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA7_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA7_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA7_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA7_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA7_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc +#define MMEA7_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe +#define MMEA7_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 +#define MMEA7_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 +#define MMEA7_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 +#define MMEA7_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 +#define MMEA7_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 +#define MMEA7_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a +#define MMEA7_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c +#define MMEA7_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA7_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA7_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA7_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA7_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA7_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA7_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L +#define MMEA7_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L +#define MMEA7_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L +#define MMEA7_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L +#define MMEA7_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L +#define MMEA7_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L +#define MMEA7_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L +#define MMEA7_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L +#define MMEA7_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L +//MMEA7_EDC_CNT2 +#define MMEA7_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 +#define MMEA7_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 +#define MMEA7_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 +#define MMEA7_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA7_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 +#define MMEA7_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa +#define MMEA7_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc +#define MMEA7_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe +#define MMEA7_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L +#define MMEA7_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA7_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L +#define MMEA7_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA7_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L +#define MMEA7_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA7_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L +#define MMEA7_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L +//MMEA7_DSM_CNTL +#define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA7_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA7_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA7_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA7_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA7_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA7_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA7_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA7_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA7_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 +#define MMEA7_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 +#define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA7_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA7_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA7_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA7_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA7_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA7_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA7_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA7_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +#define MMEA7_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L +#define MMEA7_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L +//MMEA7_DSM_CNTLA +#define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 +#define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 +#define MMEA7_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 +#define MMEA7_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define MMEA7_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 +#define MMEA7_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb +#define MMEA7_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc +#define MMEA7_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe +#define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf +#define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 +#define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 +#define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 +#define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +#define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L +#define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L +#define MMEA7_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define MMEA7_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define MMEA7_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L +#define MMEA7_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L +#define MMEA7_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L +#define MMEA7_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L +#define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L +#define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L +#define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L +#define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L +//MMEA7_DSM_CNTL2 +#define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA7_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA7_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA7_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA7_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 +#define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 +#define MMEA7_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a +#define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA7_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA7_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA7_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA7_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +#define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L +#define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L +#define MMEA7_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L +//MMEA7_DSM_CNTL2A +#define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 +#define MMEA7_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define MMEA7_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 +#define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb +#define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc +#define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe +#define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf +#define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 +#define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 +#define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 +#define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L +#define MMEA7_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define MMEA7_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L +#define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L +#define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L +#define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L +#define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L +#define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L +#define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L +#define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L +//MMEA7_CGTT_CLK_CTRL +#define MMEA7_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMEA7_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define MMEA7_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc +#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 +#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 +#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 +#define MMEA7_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 +#define MMEA7_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b +#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c +#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d +#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e +#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f +#define MMEA7_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define MMEA7_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define MMEA7_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L +#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L +#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L +#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L +#define MMEA7_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L +#define MMEA7_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L +#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L +#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L +#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L +#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L +//MMEA7_EDC_MODE +#define MMEA7_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define MMEA7_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define MMEA7_EDC_MODE__DED_MODE__SHIFT 0x14 +#define MMEA7_EDC_MODE__PROP_FED__SHIFT 0x1d +#define MMEA7_EDC_MODE__BYPASS__SHIFT 0x1f +#define MMEA7_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define MMEA7_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define MMEA7_EDC_MODE__DED_MODE_MASK 0x00300000L +#define MMEA7_EDC_MODE__PROP_FED_MASK 0x20000000L +#define MMEA7_EDC_MODE__BYPASS_MASK 0x80000000L +//MMEA7_ERR_STATUS +#define MMEA7_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define MMEA7_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define MMEA7_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define MMEA7_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MMEA7_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb +#define MMEA7_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc +#define MMEA7_ERR_STATUS__FUE_FLAG__SHIFT 0xd +#define MMEA7_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define MMEA7_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define MMEA7_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define MMEA7_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MMEA7_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L +#define MMEA7_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L +#define MMEA7_ERR_STATUS__FUE_FLAG_MASK 0x00002000L +//MMEA7_MISC2 +#define MMEA7_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 +#define MMEA7_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 +#define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 +#define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 +#define MMEA7_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc +#define MMEA7_MISC2__RRET_SWAP_MODE__SHIFT 0xd +#define MMEA7_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L +#define MMEA7_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L +#define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL +#define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L +#define MMEA7_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L +#define MMEA7_MISC2__RRET_SWAP_MODE_MASK 0x00002000L +//MMEA7_ADDRDEC_SELECT +#define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 +#define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 +#define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa +#define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf +#define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL +#define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L +#define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L +#define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L +//MMEA7_EDC_CNT3 +#define MMEA7_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 +#define MMEA7_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 +#define MMEA7_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 +#define MMEA7_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 +#define MMEA7_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 +#define MMEA7_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa +#define MMEA7_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc +#define MMEA7_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L +#define MMEA7_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL +#define MMEA7_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L +#define MMEA7_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L +#define MMEA7_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L +#define MMEA7_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L +#define MMEA7_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L + + +// addressBlock: mmhub_pctldec1 +//PCTL1_CTRL +#define PCTL1_CTRL__PG_ENABLE__SHIFT 0x0 +#define PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 +#define PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x4 +#define PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x10 +#define PCTL1_CTRL__OVR_EA0_SDP_PARTACK__SHIFT 0x11 +#define PCTL1_CTRL__OVR_EA1_SDP_PARTACK__SHIFT 0x12 +#define PCTL1_CTRL__OVR_EA2_SDP_PARTACK__SHIFT 0x13 +#define PCTL1_CTRL__OVR_EA3_SDP_PARTACK__SHIFT 0x14 +#define PCTL1_CTRL__OVR_EA4_SDP_PARTACK__SHIFT 0x15 +#define PCTL1_CTRL__OVR_EA0_SDP_FULLACK__SHIFT 0x16 +#define PCTL1_CTRL__OVR_EA1_SDP_FULLACK__SHIFT 0x17 +#define PCTL1_CTRL__OVR_EA2_SDP_FULLACK__SHIFT 0x18 +#define PCTL1_CTRL__OVR_EA3_SDP_FULLACK__SHIFT 0x19 +#define PCTL1_CTRL__OVR_EA4_SDP_FULLACK__SHIFT 0x1a +#define PCTL1_CTRL__PGFSM_CMD_STATUS__SHIFT 0x1b +#define PCTL1_CTRL__PG_ENABLE_MASK 0x00000001L +#define PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL +#define PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x000007F0L +#define PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0000F800L +#define PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00010000L +#define PCTL1_CTRL__OVR_EA0_SDP_PARTACK_MASK 0x00020000L +#define PCTL1_CTRL__OVR_EA1_SDP_PARTACK_MASK 0x00040000L +#define PCTL1_CTRL__OVR_EA2_SDP_PARTACK_MASK 0x00080000L +#define PCTL1_CTRL__OVR_EA3_SDP_PARTACK_MASK 0x00100000L +#define PCTL1_CTRL__OVR_EA4_SDP_PARTACK_MASK 0x00200000L +#define PCTL1_CTRL__OVR_EA0_SDP_FULLACK_MASK 0x00400000L +#define PCTL1_CTRL__OVR_EA1_SDP_FULLACK_MASK 0x00800000L +#define PCTL1_CTRL__OVR_EA2_SDP_FULLACK_MASK 0x01000000L +#define PCTL1_CTRL__OVR_EA3_SDP_FULLACK_MASK 0x02000000L +#define PCTL1_CTRL__OVR_EA4_SDP_FULLACK_MASK 0x04000000L +#define PCTL1_CTRL__PGFSM_CMD_STATUS_MASK 0x18000000L +//PCTL1_MMHUB_DEEPSLEEP_IB +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL1_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L +//PCTL1_MMHUB_DEEPSLEEP_OVERRIDE +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L +//PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L +#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L +//PCTL1_PG_IGNORE_DEEPSLEEP +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 +#define PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L +#define PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L +#define PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L +//PCTL1_PG_IGNORE_DEEPSLEEP_IB +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L +#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L +//PCTL1_SLICE0_CFG_DAGB_BUSY +#define PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL1_SLICE0_CFG_DS_ALLOW +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL1_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL1_SLICE0_CFG_DS_ALLOW_IB +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL1_SLICE1_CFG_DAGB_BUSY +#define PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL1_SLICE1_CFG_DS_ALLOW +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL1_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL1_SLICE1_CFG_DS_ALLOW_IB +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL1_SLICE2_CFG_DAGB_BUSY +#define PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL1_SLICE2_CFG_DS_ALLOW +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL1_SLICE2_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL1_SLICE2_CFG_DS_ALLOW_IB +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL1_SLICE3_CFG_DAGB_BUSY +#define PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL1_SLICE3_CFG_DS_ALLOW +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL1_SLICE3_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL1_SLICE3_CFG_DS_ALLOW_IB +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL1_SLICE4_CFG_DAGB_BUSY +#define PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 +#define PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL +//PCTL1_SLICE4_CFG_DS_ALLOW +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS0__SHIFT 0x0 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS1__SHIFT 0x1 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS2__SHIFT 0x2 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS3__SHIFT 0x3 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS4__SHIFT 0x4 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS5__SHIFT 0x5 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS6__SHIFT 0x6 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS7__SHIFT 0x7 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS8__SHIFT 0x8 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS9__SHIFT 0x9 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS10__SHIFT 0xa +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS11__SHIFT 0xb +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS12__SHIFT 0xc +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS13__SHIFT 0xd +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS14__SHIFT 0xe +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS15__SHIFT 0xf +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS16__SHIFT 0x10 +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS0_MASK 0x00000001L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS1_MASK 0x00000002L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS2_MASK 0x00000004L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS3_MASK 0x00000008L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS4_MASK 0x00000010L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS5_MASK 0x00000020L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS6_MASK 0x00000040L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS7_MASK 0x00000080L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS8_MASK 0x00000100L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS9_MASK 0x00000200L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS10_MASK 0x00000400L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS11_MASK 0x00000800L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS12_MASK 0x00001000L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS13_MASK 0x00002000L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS14_MASK 0x00004000L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS15_MASK 0x00008000L +#define PCTL1_SLICE4_CFG_DS_ALLOW__DS16_MASK 0x00010000L +//PCTL1_SLICE4_CFG_DS_ALLOW_IB +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L +#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L +//PCTL1_UTCL2_MISC +#define PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb +#define PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc +#define PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf +#define PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 +#define PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL1_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L +#define PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L +#define PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L +#define PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L +#define PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL1_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL1_SLICE0_MISC +#define PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL1_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL1_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL1_SLICE1_MISC +#define PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL1_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL1_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL1_SLICE2_MISC +#define PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL1_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL1_SLICE2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL1_SLICE3_MISC +#define PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL1_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL1_SLICE3_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL1_SLICE4_MISC +#define PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa +#define PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb +#define PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe +#define PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf +#define PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 +#define PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 +#define PCTL1_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT 0x12 +#define PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L +#define PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L +#define PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L +#define PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L +#define PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L +#define PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L +#define PCTL1_SLICE4_MISC__RD_TIMER_ENABLE_MASK 0x00040000L +//PCTL1_UTCL2_RENG_EXECUTE +#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd +#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL +#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L +//PCTL1_SLICE0_RENG_EXECUTE +#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL1_SLICE1_RENG_EXECUTE +#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL1_SLICE2_RENG_EXECUTE +#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL1_SLICE3_RENG_EXECUTE +#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL1_SLICE4_RENG_EXECUTE +#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 +#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 +#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 +#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc +#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L +#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L +#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL +#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L +//PCTL1_UTCL2_RENG_RAM_INDEX +#define PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL +//PCTL1_UTCL2_RENG_RAM_DATA +#define PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL1_SLICE0_RENG_RAM_INDEX +#define PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL1_SLICE0_RENG_RAM_DATA +#define PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL1_SLICE1_RENG_RAM_INDEX +#define PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL1_SLICE1_RENG_RAM_DATA +#define PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL1_SLICE2_RENG_RAM_INDEX +#define PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL1_SLICE2_RENG_RAM_DATA +#define PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL1_SLICE3_RENG_RAM_INDEX +#define PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL1_SLICE3_RENG_RAM_DATA +#define PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL1_SLICE4_RENG_RAM_INDEX +#define PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 +#define PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL +//PCTL1_SLICE4_RENG_RAM_DATA +#define PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 +#define PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL +//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L +//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L +//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL +#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L + + +// addressBlock: mmhub_l1tlb_vml1dec:1 +//VML1_1_MC_VM_MX_L1_TLB0_STATUS +#define VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 +#define VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L +#define VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_1_MC_VM_MX_L1_TLB1_STATUS +#define VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 +#define VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L +#define VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_1_MC_VM_MX_L1_TLB2_STATUS +#define VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 +#define VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L +#define VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_1_MC_VM_MX_L1_TLB3_STATUS +#define VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 +#define VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L +#define VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_1_MC_VM_MX_L1_TLB4_STATUS +#define VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 +#define VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L +#define VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_1_MC_VM_MX_L1_TLB5_STATUS +#define VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 +#define VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L +#define VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_1_MC_VM_MX_L1_TLB6_STATUS +#define VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 +#define VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L +#define VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//VML1_1_MC_VM_MX_L1_TLB7_STATUS +#define VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 +#define VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L +#define VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L + + +// addressBlock: mmhub_l1tlb_vml1pldec:1 +//VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_l1tlb_vml1prdec:1 +//VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO +#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI +#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_atcl2dec:1 +//ATCL2_1_ATC_L2_CNTL +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf +#define ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 +#define ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L +#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L +#define ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L +#define ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L +//ATCL2_1_ATC_L2_CNTL2 +#define ATCL2_1_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 +#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 +#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc +#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf +#define ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT 0x15 +#define ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT 0x1b +#define ATCL2_1_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L +#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L +#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L +#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L +#define ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK 0x07E00000L +#define ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK 0x08000000L +//ATCL2_1_ATC_L2_CACHE_DATA0 +#define ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 +#define ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL +#define ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L +//ATCL2_1_ATC_L2_CACHE_DATA1 +#define ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//ATCL2_1_ATC_L2_CACHE_DATA2 +#define ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//ATCL2_1_ATC_L2_CNTL3 +#define ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 +#define ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 +#define ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L +#define ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L +#define ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L +//ATCL2_1_ATC_L2_STATUS +#define ATCL2_1_ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 +#define ATCL2_1_ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x7FFFFFFEL +//ATCL2_1_ATC_L2_STATUS2 +#define ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 +#define ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 +#define ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL +#define ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L +//ATCL2_1_ATC_L2_STATUS3 +#define ATCL2_1_ATC_L2_STATUS3__BUSY__SHIFT 0x0 +#define ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT 0x1 +#define ATCL2_1_ATC_L2_STATUS3__BUSY_MASK 0x00000001L +#define ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK 0x7FFFFFFEL +//ATCL2_1_ATC_L2_MISC_CG +#define ATCL2_1_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define ATCL2_1_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define ATCL2_1_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define ATCL2_1_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//ATCL2_1_ATC_L2_MEM_POWER_LS +#define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//ATCL2_1_ATC_L2_CGTT_CLK_CTRL +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL +//ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L +#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L +//ATCL2_1_ATC_L2_CNTL4 +#define ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES +#define ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_utcl2_vml2pfdec:1 +//VML2PF1_VM_L2_CNTL +#define VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//VML2PF1_VM_L2_CNTL2 +#define VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//VML2PF1_VM_L2_CNTL3 +#define VML2PF1_VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define VML2PF1_VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//VML2PF1_VM_L2_STATUS +#define VML2PF1_VM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define VML2PF1_VM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL +#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 +#define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL +//VML2PF1_VM_L2_PROTECTION_FAULT_CNTL +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L +//VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3 +#define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4 +#define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//VML2PF1_VM_L2_PROTECTION_FAULT_STATUS +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L +#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L +//VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32 +#define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32 +#define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 +#define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL +//VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 +#define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL +//VML2PF1_VM_L2_CNTL4 +#define VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +//VML2PF1_VM_L2_MM_GROUP_RT_CLASSES +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +//VML2PF1_VM_L2_CACHE_PARITY_CNTL +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//VML2PF1_VM_L2_CGTT_CLK_CTRL +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L + + +// addressBlock: mmhub_utcl2_vml2vcdec:1 +//VML2VC1_VM_CONTEXT0_CNTL +#define VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT1_CNTL +#define VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT2_CNTL +#define VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT3_CNTL +#define VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT4_CNTL +#define VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT5_CNTL +#define VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT6_CNTL +#define VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT7_CNTL +#define VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT8_CNTL +#define VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT9_CNTL +#define VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT10_CNTL +#define VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT11_CNTL +#define VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT12_CNTL +#define VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT13_CNTL +#define VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT14_CNTL +#define VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXT15_CNTL +#define VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 +#define VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 +#define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 +#define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb +#define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd +#define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe +#define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf +#define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 +#define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 +#define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 +#define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 +#define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 +#define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 +#define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 +#define VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L +#define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +#define VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L +#define VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L +#define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L +#define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L +#define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L +#define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L +#define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L +#define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L +#define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L +#define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L +#define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L +#define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L +#define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L +#define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L +//VML2VC1_VM_CONTEXTS_DISABLE +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//VML2VC1_VM_INVALIDATE_ENG0_SEM +#define VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG1_SEM +#define VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG2_SEM +#define VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG3_SEM +#define VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG4_SEM +#define VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG5_SEM +#define VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG6_SEM +#define VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG7_SEM +#define VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG8_SEM +#define VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG9_SEM +#define VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG10_SEM +#define VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG11_SEM +#define VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG12_SEM +#define VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG13_SEM +#define VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG14_SEM +#define VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG15_SEM +#define VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG16_SEM +#define VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG17_SEM +#define VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//VML2VC1_VM_INVALIDATE_ENG0_REQ +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG1_REQ +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG2_REQ +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG3_REQ +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG4_REQ +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG5_REQ +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG6_REQ +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG7_REQ +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG8_REQ +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG9_REQ +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG10_REQ +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG11_REQ +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG12_REQ +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG13_REQ +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG14_REQ +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG15_REQ +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG16_REQ +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG17_REQ +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L +#define VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L +//VML2VC1_VM_INVALIDATE_ENG0_ACK +#define VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG1_ACK +#define VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG2_ACK +#define VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG3_ACK +#define VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG4_ACK +#define VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG5_ACK +#define VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG6_ACK +#define VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG7_ACK +#define VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG8_ACK +#define VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG9_ACK +#define VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG10_ACK +#define VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG11_ACK +#define VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG12_ACK +#define VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG13_ACK +#define VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG14_ACK +#define VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG15_ACK +#define VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG16_ACK +#define VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG17_ACK +#define VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 +#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL +//VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL + + +// addressBlock: mmhub_utcl2_vmsharedpfdec:1 +//VMSHAREDPF1_MC_VM_NB_MMIOBASE +#define VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//VMSHAREDPF1_MC_VM_NB_MMIOLIMIT +#define VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//VMSHAREDPF1_MC_VM_NB_PCI_CTRL +#define VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//VMSHAREDPF1_MC_VM_NB_PCI_ARB +#define VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1 +#define VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2 +#define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2 +#define VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL +//VMSHAREDPF1_MC_VM_FB_OFFSET +#define VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL +//VMSHAREDPF1_MC_VM_STEERING +#define VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ +#define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L +//VMSHAREDPF1_MC_MEM_POWER_LS +#define VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 +#define VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 +#define VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL +#define VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L +//VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START +#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END +#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//VMSHAREDPF1_MC_VM_APT_CNTL +#define VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +//VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START +#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL +//VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END +#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL +//VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL +#define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +#define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL +#define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L +//VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE +#define VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL +//VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL +#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 +#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L + + +// addressBlock: mmhub_utcl2_vmsharedvcdec:1 +//VMSHAREDVC1_MC_VM_FB_LOCATION_BASE +#define VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//VMSHAREDVC1_MC_VM_FB_LOCATION_TOP +#define VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//VMSHAREDVC1_MC_VM_AGP_TOP +#define VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//VMSHAREDVC1_MC_VM_AGP_BOT +#define VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//VMSHAREDVC1_MC_VM_AGP_BASE +#define VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR +#define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR +#define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 +#define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL +//VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L +#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L + + +// addressBlock: mmhub_utcl2_vmsharedhvdec:1 +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL +#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L +//VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1 +#define VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 +#define VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L +//VMSHAREDHV1_MC_VM_MARC_BASE_LO_0 +#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_BASE_LO_1 +#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_BASE_LO_2 +#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_BASE_LO_3 +#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_BASE_HI_0 +#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_BASE_HI_1 +#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_BASE_HI_2 +#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_BASE_HI_3 +#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L +#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_LEN_LO_0 +#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_LEN_LO_1 +#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_LEN_LO_2 +#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_LEN_LO_3 +#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L +//VMSHAREDHV1_MC_VM_MARC_LEN_HI_0 +#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_LEN_HI_1 +#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_LEN_HI_2 +#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL +//VMSHAREDHV1_MC_VM_MARC_LEN_HI_3 +#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL +//VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER +#define VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15 +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f +#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L +//VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L +#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L +//VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID +#define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L +#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L + + +// addressBlock: mmhub_utcl2_atcl2pfcntrdec:1 +//ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO +#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI +#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_utcl2_atcl2pfcntldec:1 +//ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_utcl2_vml2pldec:1 +//VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_utcl2_vml2prdec:1 +//VML2PR1_MC_VM_L2_PERFCOUNTER_LO +#define VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//VML2PR1_MC_VM_L2_PERFCOUNTER_HI +#define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h new file mode 100644 index 000000000000..1fe51fcb648e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_12_0_0_OFFSET_HEADER +#define _mp_12_0_0_OFFSET_HEADER + + + +// addressBlock: mp_SmuMp0_SmnDec +// base address: 0x0 +#define mmMP0_SMN_C2PMSG_32 0x0060 +#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_33 0x0061 +#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_34 0x0062 +#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_35 0x0063 +#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_36 0x0064 +#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_37 0x0065 +#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_38 0x0066 +#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_39 0x0067 +#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_40 0x0068 +#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_41 0x0069 +#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_42 0x006a +#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_43 0x006b +#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_44 0x006c +#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_45 0x006d +#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_46 0x006e +#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_47 0x006f +#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_48 0x0070 +#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_49 0x0071 +#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_50 0x0072 +#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_51 0x0073 +#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_52 0x0074 +#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_53 0x0075 +#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_54 0x0076 +#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_55 0x0077 +#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_56 0x0078 +#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_57 0x0079 +#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_58 0x007a +#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_59 0x007b +#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_60 0x007c +#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_61 0x007d +#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_62 0x007e +#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_63 0x007f +#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_64 0x0080 +#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_65 0x0081 +#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_66 0x0082 +#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_67 0x0083 +#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_68 0x0084 +#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_69 0x0085 +#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_70 0x0086 +#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_71 0x0087 +#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_72 0x0088 +#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_73 0x0089 +#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_74 0x008a +#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_75 0x008b +#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_76 0x008c +#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_77 0x008d +#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_78 0x008e +#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_79 0x008f +#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_80 0x0090 +#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_81 0x0091 +#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_82 0x0092 +#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_83 0x0093 +#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_84 0x0094 +#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_85 0x0095 +#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_86 0x0096 +#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_87 0x0097 +#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_88 0x0098 +#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_89 0x0099 +#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_90 0x009a +#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_91 0x009b +#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_92 0x009c +#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_93 0x009d +#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_94 0x009e +#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_95 0x009f +#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_96 0x00a0 +#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_97 0x00a1 +#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_98 0x00a2 +#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_99 0x00a3 +#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_100 0x00a4 +#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_101 0x00a5 +#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_102 0x00a6 +#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP0_SMN_C2PMSG_103 0x00a7 +#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP0_SMN_IH_CREDIT 0x00c1 +#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT 0x00c2 +#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 +#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define mmMP1_SMN_C2PMSG_32 0x0260 +#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_33 0x0261 +#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_34 0x0262 +#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_35 0x0263 +#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_36 0x0264 +#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_37 0x0265 +#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_38 0x0266 +#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_39 0x0267 +#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_40 0x0268 +#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_41 0x0269 +#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_42 0x026a +#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_43 0x026b +#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_44 0x026c +#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_45 0x026d +#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_46 0x026e +#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_47 0x026f +#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_48 0x0270 +#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_49 0x0271 +#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_50 0x0272 +#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_51 0x0273 +#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_52 0x0274 +#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_53 0x0275 +#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_54 0x0276 +#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_55 0x0277 +#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_56 0x0278 +#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_57 0x0279 +#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_58 0x027a +#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_59 0x027b +#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_60 0x027c +#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_61 0x027d +#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_62 0x027e +#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_63 0x027f +#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_64 0x0280 +#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_65 0x0281 +#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_66 0x0282 +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_67 0x0283 +#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_68 0x0284 +#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_69 0x0285 +#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_70 0x0286 +#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_71 0x0287 +#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_72 0x0288 +#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_73 0x0289 +#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_74 0x028a +#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_75 0x028b +#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_76 0x028c +#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_77 0x028d +#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_78 0x028e +#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_79 0x028f +#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_80 0x0290 +#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_81 0x0291 +#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_82 0x0292 +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_83 0x0293 +#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_84 0x0294 +#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_85 0x0295 +#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_86 0x0296 +#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_87 0x0297 +#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_88 0x0298 +#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_89 0x0299 +#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_90 0x029a +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_91 0x029b +#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_92 0x029c +#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_93 0x029d +#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_94 0x029e +#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_95 0x029f +#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_96 0x02a0 +#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_97 0x02a1 +#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_98 0x02a2 +#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_99 0x02a3 +#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_100 0x02a4 +#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_101 0x02a5 +#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_102 0x02a6 +#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_103 0x02a7 +#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 +#define mmMP1_SMN_IH_CREDIT 0x02c1 +#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT 0x02c2 +#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 +#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 +#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +#define mmMP1_SMN_FPS_CNT 0x02c4 +#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h new file mode 100644 index 000000000000..c78151e624b3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h @@ -0,0 +1,866 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_12_0_0_SH_MASK_HEADER +#define _mp_12_0_0_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp0_SmnDec +//MP0_SMN_C2PMSG_32 +#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_33 +#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_34 +#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_35 +#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_36 +#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_37 +#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_38 +#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_39 +#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_40 +#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_41 +#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_42 +#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_43 +#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_44 +#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_45 +#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_46 +#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_47 +#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_48 +#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_49 +#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_50 +#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_51 +#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_52 +#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_53 +#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_54 +#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_55 +#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_56 +#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_57 +#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_58 +#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_59 +#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_60 +#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_61 +#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_62 +#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_63 +#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_64 +#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_65 +#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_66 +#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_67 +#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_68 +#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_69 +#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_70 +#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_71 +#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_72 +#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_73 +#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_74 +#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_75 +#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_76 +#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_77 +#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_78 +#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_79 +#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_80 +#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_81 +#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_82 +#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_83 +#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_84 +#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_85 +#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_86 +#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_87 +#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_88 +#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_89 +#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_90 +#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_91 +#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_92 +#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_93 +#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_94 +#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_95 +#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_96 +#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_97 +#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_98 +#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_99 +#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_100 +#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_101 +#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_102 +#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_C2PMSG_103 +#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP0_SMN_IH_CREDIT +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_SMN_IH_SW_INT +#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: mp_SmuMp0Pub_CruDec +//MP0_IH_CREDIT +#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP0_IH_SW_INT +#define MP0_IH_SW_INT__ID__SHIFT 0x0 +#define MP0_IH_SW_INT__VALID__SHIFT 0x8 +#define MP0_IH_SW_INT__ID_MASK 0x000000FFL +#define MP0_IH_SW_INT__VALID_MASK 0x00000100L +//MP0_IH_SW_INT_CTRL +#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_FIRMWARE_FLAGS +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL +//MP1_C2PMSG_0 +#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_1 +#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_2 +#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_3 +#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_4 +#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_5 +#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_6 +#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_7 +#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_8 +#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_9 +#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_10 +#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_11 +#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_12 +#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_13 +#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_14 +#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_15 +#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_16 +#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_17 +#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_18 +#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_19 +#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_20 +#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_21 +#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_22 +#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_23 +#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_24 +#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_25 +#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_26 +#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_27 +#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_28 +#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_29 +#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_30 +#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_31 +#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_0 +#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_1 +#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_2 +#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_3 +#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 +#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_P2CMSG_INTEN +#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 +#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +//MP1_P2CMSG_INTSTS +#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +//MP1_C2PMSG_32 +#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_33 +#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_34 +#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_35 +#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_36 +#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_37 +#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_38 +#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_39 +#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_40 +#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_41 +#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_42 +#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_43 +#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_44 +#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_45 +#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_46 +#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_47 +#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_48 +#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_49 +#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_50 +#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_51 +#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_52 +#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_53 +#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_54 +#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_55 +#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_56 +#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_57 +#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_58 +#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_59 +#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_60 +#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_61 +#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_62 +#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_63 +#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_64 +#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_65 +#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_66 +#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_67 +#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_68 +#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_69 +#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_70 +#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_71 +#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_72 +#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_73 +#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_74 +#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_75 +#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_76 +#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_77 +#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_78 +#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_79 +#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_80 +#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_81 +#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_82 +#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_83 +#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_84 +#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_85 +#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_86 +#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_87 +#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_88 +#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_89 +#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_90 +#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_91 +#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_92 +#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_93 +#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_94 +#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_95 +#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_96 +#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_97 +#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_98 +#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_99 +#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_100 +#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_101 +#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_102 +#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_C2PMSG_103 +#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_IH_CREDIT +#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_IH_SW_INT +#define MP1_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_IH_SW_INT_CTRL +#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_FPS_CNT +#define MP1_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h index 88602479a1aa..ee8c15e4543d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h @@ -74709,6 +74709,36 @@ //PCIE_PERF_COUNT1_TXCLK2 #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0 #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK3 +#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_TXCLK3 +#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK3 +#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL +//PCIE_PERF_CNTL_TXCLK4 +#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0 +#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8 +#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT 0x10 +#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT 0x18 +#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL +#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L +#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK 0x00FF0000L +#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK 0xFF000000L +//PCIE_PERF_COUNT0_TXCLK4 +#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0 +#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL +//PCIE_PERF_COUNT1_TXCLK4 +#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0 +#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL //PCIE_PRBS_CLR #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0 #define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18 diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h index caf5ffdc130a..6702575bc6e3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h @@ -50,6 +50,12 @@ #define smnPCIE_PERF_CNTL_TXCLK2 0x11180254 #define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258 #define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c +#define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c +#define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220 +#define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224 +#define smnPCIE_PERF_CNTL_TXCLK4 0x11180228 +#define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c +#define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230 #define smnPCIE_RX_NUM_NAK 0x11180038 #define smnPCIE_RX_NUM_NAK_GENERATED 0x1118003c diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h index 1ee3a2329ee4..dc9895a684fe 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h @@ -1109,7 +1109,11 @@ #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L //IH_CHICKEN #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 +#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 +#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L +#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L +#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L //IH_MMHUB_CNTL #define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 #define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 diff --git a/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h new file mode 100644 index 000000000000..46466ae77f19 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _rsmu_0_0_2_OFFSET_HEADER +#define _rsmu_0_0_2_OFFSET_HEADER + +#define mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU 0x0d91 +#define mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h new file mode 100644 index 000000000000..ea0acb598254 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _rsmu_0_0_2_SH_MASK_HEADER +#define _rsmu_0_0_2_SH_MASK_HEADER + +//RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU +#define RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_WREN__SHIFT 0x0 +#define RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE__SHIFT 0x10 +#define RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_MODE_EN__SHIFT 0x1f +#define RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_WREN_MASK 0x0000FFFFL +#define RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE_MASK 0x000F0000L +#define RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_MODE_EN_MASK 0x80000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h new file mode 100644 index 000000000000..ff5df90071e6 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h @@ -0,0 +1,1051 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_2_2_OFFSET_HEADER +#define _sdma0_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma0_sdma0dec +// base address: 0x4980 +#define mmSDMA0_UCODE_ADDR 0x0000 +#define mmSDMA0_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA0_UCODE_DATA 0x0001 +#define mmSDMA0_UCODE_DATA_BASE_IDX 0 +#define mmSDMA0_VM_CNTL 0x0004 +#define mmSDMA0_VM_CNTL_BASE_IDX 0 +#define mmSDMA0_VM_CTX_LO 0x0005 +#define mmSDMA0_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA0_VM_CTX_HI 0x0006 +#define mmSDMA0_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA0_ACTIVE_FCN_ID 0x0007 +#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA0_VM_CTX_CNTL 0x0008 +#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA0_VIRT_RESET_REQ 0x0009 +#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA0_VF_ENABLE 0x000a +#define mmSDMA0_VF_ENABLE_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE0 0x000f +#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE1 0x0010 +#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE2 0x0011 +#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA0_PUB_REG_TYPE3 0x0012 +#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA0_MMHUB_CNTL 0x0013 +#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL 0x001a +#define mmSDMA0_POWER_CNTL_BASE_IDX 0 +#define mmSDMA0_CLK_CTRL 0x001b +#define mmSDMA0_CLK_CTRL_BASE_IDX 0 +#define mmSDMA0_CNTL 0x001c +#define mmSDMA0_CNTL_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS 0x001d +#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG 0x001e +#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA0_RB_RPTR_FETCH 0x0022 +#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA0_IB_OFFSET_FETCH 0x0023 +#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA0_PROGRAM 0x0024 +#define mmSDMA0_PROGRAM_BASE_IDX 0 +#define mmSDMA0_STATUS_REG 0x0025 +#define mmSDMA0_STATUS_REG_BASE_IDX 0 +#define mmSDMA0_STATUS1_REG 0x0026 +#define mmSDMA0_STATUS1_REG_BASE_IDX 0 +#define mmSDMA0_RD_BURST_CNTL 0x0027 +#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA0_UCODE_CHECKSUM 0x0029 +#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA0_F32_CNTL 0x002a +#define mmSDMA0_F32_CNTL_BASE_IDX 0 +#define mmSDMA0_FREEZE 0x002b +#define mmSDMA0_FREEZE_BASE_IDX 0 +#define mmSDMA0_PHASE0_QUANTUM 0x002c +#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA0_PHASE1_QUANTUM 0x002d +#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA_POWER_GATING 0x002e +#define mmSDMA_POWER_GATING_BASE_IDX 0 +#define mmSDMA_PGFSM_CONFIG 0x002f +#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 +#define mmSDMA_PGFSM_WRITE 0x0030 +#define mmSDMA_PGFSM_WRITE_BASE_IDX 0 +#define mmSDMA_PGFSM_READ 0x0031 +#define mmSDMA_PGFSM_READ_BASE_IDX 0 +#define mmSDMA0_EDC_CONFIG 0x0032 +#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA0_BA_THRESHOLD 0x0033 +#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA0_ID 0x0034 +#define mmSDMA0_ID_BASE_IDX 0 +#define mmSDMA0_VERSION 0x0035 +#define mmSDMA0_VERSION_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER 0x0036 +#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA0_STATUS2_REG 0x0038 +#define mmSDMA0_STATUS2_REG_BASE_IDX 0 +#define mmSDMA0_ATOMIC_CNTL 0x0039 +#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_LO 0x003a +#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA0_ATOMIC_PREOP_HI 0x003b +#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA0_UTCL1_CNTL 0x003c +#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA0_UTCL1_WATERMK 0x003d +#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_STATUS 0x003e +#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_STATUS 0x003f +#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV0 0x0040 +#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV1 0x0041 +#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA0_UTCL1_INV2 0x0042 +#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA0_UTCL1_TIMEOUT 0x0047 +#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA0_UTCL1_PAGE 0x0048 +#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA0_POWER_CNTL_IDLE 0x0049 +#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA0_RELAX_ORDERING_LUT 0x004a +#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA0_CHICKEN_BITS_2 0x004b +#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA0_STATUS3_REG 0x004c +#define mmSDMA0_STATUS3_REG_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PHASE2_QUANTUM 0x004f +#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 +#define mmSDMA0_ERROR_LOG 0x0050 +#define mmSDMA0_ERROR_LOG_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG0 0x0051 +#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG1 0x0052 +#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG2 0x0053 +#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA0_PUB_DUMMY_REG3 0x0054 +#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA0_F32_COUNTER 0x0055 +#define mmSDMA0_F32_COUNTER_BASE_IDX 0 +#define mmSDMA0_UNBREAKABLE 0x0056 +#define mmSDMA0_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA0_PERFMON_CNTL 0x0057 +#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA0_CRD_CNTL 0x005b +#define mmSDMA0_CRD_CNTL_BASE_IDX 0 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA0_ULV_CNTL 0x005e +#define mmSDMA0_ULV_CNTL_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define mmSDMA0_GFX_RB_CNTL 0x0080 +#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE 0x0081 +#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA0_GFX_RB_BASE_HI 0x0082 +#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR 0x0083 +#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR 0x0085 +#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_CNTL 0x008a +#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_IB_RPTR 0x008b +#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_GFX_IB_OFFSET 0x008c +#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_LO 0x008d +#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_GFX_IB_BASE_HI 0x008e +#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SIZE 0x008f +#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_GFX_SKIP_CNTL 0x0090 +#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL 0x0092 +#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_STATUS 0x00a8 +#define mmSDMA0_GFX_STATUS_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_GFX_WATERMARK 0x00aa +#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_GFX_PREEMPT 0x00b0 +#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA0_GFX_DUMMY_REG 0x00b1 +#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_CNTL 0x00d8 +#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_BASE 0x00d9 +#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_BASE_HI 0x00da +#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR 0x00db +#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR 0x00dd +#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_CNTL 0x00e2 +#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_RPTR 0x00e3 +#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_SIZE 0x00e7 +#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL 0x00ea +#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 +#define mmSDMA0_PAGE_STATUS 0x0100 +#define mmSDMA0_PAGE_STATUS_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_PAGE_WATERMARK 0x0102 +#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 +#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_PAGE_PREEMPT 0x0108 +#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 +#define mmSDMA0_PAGE_DUMMY_REG 0x0109 +#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_CNTL 0x0130 +#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE 0x0131 +#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR 0x0133 +#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR 0x0135 +#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_CNTL 0x013a +#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_RPTR 0x013b +#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_OFFSET 0x013c +#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_LO 0x013d +#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_BASE_HI 0x013e +#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SIZE 0x013f +#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL 0x0142 +#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC0_STATUS 0x0158 +#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC0_WATERMARK 0x015a +#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC0_PREEMPT 0x0160 +#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC0_DUMMY_REG 0x0161 +#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_CNTL 0x0188 +#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE 0x0189 +#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_BASE_HI 0x018a +#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR 0x018b +#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR 0x018d +#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_CNTL 0x0192 +#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_RPTR 0x0193 +#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_OFFSET 0x0194 +#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SIZE 0x0197 +#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL 0x019a +#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC1_STATUS 0x01b0 +#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC1_WATERMARK 0x01b2 +#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC1_PREEMPT 0x01b8 +#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_CNTL 0x01e0 +#define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_BASE 0x01e1 +#define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_RPTR 0x01e3 +#define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR 0x01e5 +#define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_CNTL 0x01ea +#define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_RPTR 0x01eb +#define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_OFFSET 0x01ec +#define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_SIZE 0x01ef +#define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC2_DOORBELL 0x01f2 +#define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC2_STATUS 0x0208 +#define mmSDMA0_RLC2_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC2_WATERMARK 0x020a +#define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC2_PREEMPT 0x0210 +#define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC2_DUMMY_REG 0x0211 +#define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_CNTL 0x0238 +#define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_BASE 0x0239 +#define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_BASE_HI 0x023a +#define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_RPTR 0x023b +#define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR 0x023d +#define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_CNTL 0x0242 +#define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_RPTR 0x0243 +#define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_OFFSET 0x0244 +#define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_SIZE 0x0247 +#define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC3_DOORBELL 0x024a +#define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC3_STATUS 0x0260 +#define mmSDMA0_RLC3_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC3_WATERMARK 0x0262 +#define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC3_PREEMPT 0x0268 +#define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC3_DUMMY_REG 0x0269 +#define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_CNTL 0x0290 +#define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_BASE 0x0291 +#define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_RPTR 0x0293 +#define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR 0x0295 +#define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_CNTL 0x029a +#define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_RPTR 0x029b +#define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_OFFSET 0x029c +#define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_BASE_LO 0x029d +#define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_BASE_HI 0x029e +#define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_SIZE 0x029f +#define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC4_DOORBELL 0x02a2 +#define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC4_STATUS 0x02b8 +#define mmSDMA0_RLC4_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC4_WATERMARK 0x02ba +#define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC4_PREEMPT 0x02c0 +#define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_CNTL 0x02e8 +#define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_BASE 0x02e9 +#define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_RPTR 0x02eb +#define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR 0x02ed +#define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_CNTL 0x02f2 +#define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_RPTR 0x02f3 +#define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_SIZE 0x02f7 +#define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC5_DOORBELL 0x02fa +#define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC5_STATUS 0x0310 +#define mmSDMA0_RLC5_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC5_WATERMARK 0x0312 +#define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC5_PREEMPT 0x0318 +#define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC5_DUMMY_REG 0x0319 +#define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_CNTL 0x0340 +#define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_BASE 0x0341 +#define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_RPTR 0x0343 +#define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR 0x0345 +#define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_CNTL 0x034a +#define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_RPTR 0x034b +#define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_OFFSET 0x034c +#define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_BASE_LO 0x034d +#define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_BASE_HI 0x034e +#define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_SIZE 0x034f +#define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC6_DOORBELL 0x0352 +#define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC6_STATUS 0x0368 +#define mmSDMA0_RLC6_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC6_WATERMARK 0x036a +#define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC6_PREEMPT 0x0370 +#define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC6_DUMMY_REG 0x0371 +#define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_CNTL 0x0398 +#define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_BASE 0x0399 +#define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_BASE_HI 0x039a +#define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_RPTR 0x039b +#define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR 0x039d +#define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_CNTL 0x03a2 +#define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_RPTR 0x03a3 +#define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_SIZE 0x03a7 +#define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0 +#define mmSDMA0_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC7_DOORBELL 0x03aa +#define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0 +#define mmSDMA0_RLC7_STATUS 0x03c0 +#define mmSDMA0_RLC7_STATUS_BASE_IDX 0 +#define mmSDMA0_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA0_RLC7_WATERMARK 0x03c2 +#define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0 +#define mmSDMA0_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA0_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA0_RLC7_PREEMPT 0x03c8 +#define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0 +#define mmSDMA0_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA0_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA0_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h new file mode 100644 index 000000000000..9feb67b09b63 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h @@ -0,0 +1,3002 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma0_4_2_2_SH_MASK_HEADER +#define _sdma0_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma0_sdma0dec +//SDMA0_UCODE_ADDR +#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA0_UCODE_DATA +#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_VM_CNTL +#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA0_VM_CTX_LO +#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_VM_CTX_HI +#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_ACTIVE_FCN_ID +#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA0_VM_CTX_CNTL +#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA0_VIRT_RESET_REQ +#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA0_VF_ENABLE +#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA0_CONTEXT_REG_TYPE0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA0_CONTEXT_REG_TYPE1 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA0_CONTEXT_REG_TYPE2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA0_CONTEXT_REG_TYPE3 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_PUB_REG_TYPE0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b +#define SDMA0_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e +#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L +#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L +#define SDMA0_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L +#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA0_PUB_REG_TYPE3 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA0_MMHUB_CNTL +#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA0_CONTEXT_GROUP_BOUNDARY +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_POWER_CNTL +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a +#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L +#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L +#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L +//SDMA0_CLK_CTRL +#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA0_CNTL +#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA0_CHICKEN_BITS +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA0_GB_ADDR_CONFIG +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_GB_ADDR_CONFIG_READ +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA0_RB_RPTR_FETCH_HI +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA0_RB_RPTR_FETCH +#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_IB_OFFSET_FETCH +#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_PROGRAM +#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_STATUS_REG +#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_STATUS1_REG +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA0_RD_BURST_CNTL +#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA0_HBM_PAGE_CONFIG +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_UCODE_CHECKSUM +#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA0_F32_CNTL +#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L +//SDMA0_FREEZE +#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA0_PHASE0_QUANTUM +#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_PHASE1_QUANTUM +#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA_POWER_GATING +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 +#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L +#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L +#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L +#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L +//SDMA_PGFSM_CONFIG +#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 +#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 +#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 +#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa +#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb +#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc +#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b +#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c +#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL +#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L +#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L +#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L +#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L +#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L +#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L +#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L +#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L +//SDMA_PGFSM_WRITE +#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL +//SDMA_PGFSM_READ +#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 +#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL +//SDMA0_EDC_CONFIG +#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA0_BA_THRESHOLD +#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA0_ID +#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_VERSION +#define SDMA0_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_VERSION__REV__SHIFT 0x10 +#define SDMA0_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_VERSION__REV_MASK 0x003F0000L +//SDMA0_EDC_COUNTER +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA0_EDC_COUNTER_CLEAR +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA0_STATUS2_REG +#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_ATOMIC_CNTL +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_ATOMIC_PREOP_LO +#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_ATOMIC_PREOP_HI +#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_CNTL +#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA0_UTCL1_WATERMK +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA0_UTCL1_RD_STATUS +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA0_UTCL1_WR_STATUS +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA0_UTCL1_INV0 +#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA0_UTCL1_INV1 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_INV2 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_RD_XNACK1 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_WR_XNACK0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_UTCL1_WR_XNACK1 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA0_UTCL1_TIMEOUT +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA0_UTCL1_PAGE +#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA0_POWER_CNTL_IDLE +#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA0_RELAX_ORDERING_LUT +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA0_CHICKEN_BITS_2 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA0_STATUS3_REG +#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA0_PHYSICAL_ADDR_LO +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA0_PHYSICAL_ADDR_HI +#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA0_PHASE2_QUANTUM +#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA0_ERROR_LOG +#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_PUB_DUMMY_REG0 +#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG1 +#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG2 +#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_PUB_DUMMY_REG3 +#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_F32_COUNTER +#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_UNBREAKABLE +#define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA0_PERFMON_CNTL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA0_PERFCOUNTER0_RESULT +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER1_RESULT +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA0_CRD_CNTL +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA0_GPU_IOV_VIOLATION_LOG +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA0_ULV_CNTL +#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA0_EA_DBIT_ADDR_DATA +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA0_EA_DBIT_ADDR_INDEX +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA0_GPU_IOV_VIOLATION_LOG2 +#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA0_GFX_RB_CNTL +#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_GFX_RB_BASE +#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_BASE_HI +#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_GFX_RB_RPTR +#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_HI +#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR +#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_HI +#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_CNTL +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_GFX_RB_RPTR_ADDR_HI +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_RPTR_ADDR_LO +#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_IB_CNTL +#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_GFX_IB_RPTR +#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_OFFSET +#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_GFX_IB_BASE_LO +#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_GFX_IB_BASE_HI +#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SIZE +#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_SKIP_CNTL +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_GFX_CONTEXT_STATUS +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_GFX_DOORBELL +#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_GFX_CONTEXT_CNTL +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA0_GFX_STATUS +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_GFX_DOORBELL_LOG +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_GFX_WATERMARK +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_GFX_DOORBELL_OFFSET +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_GFX_CSA_ADDR_LO +#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_CSA_ADDR_HI +#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_IB_SUB_REMAIN +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_GFX_PREEMPT +#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_GFX_DUMMY_REG +#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_GFX_RB_AQL_CNTL +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_GFX_MINOR_PTR_UPDATE +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_GFX_MIDCMD_DATA0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA1 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA2 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA3 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA4 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA5 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA6 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA7 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_DATA8 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_GFX_MIDCMD_CNTL +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_PAGE_RB_CNTL +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_PAGE_RB_BASE +#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_BASE_HI +#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_PAGE_RB_RPTR +#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_HI +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR +#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_HI +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_CNTL +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_PAGE_RB_RPTR_ADDR_HI +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_RPTR_ADDR_LO +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_IB_CNTL +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_PAGE_IB_RPTR +#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_OFFSET +#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_PAGE_IB_BASE_LO +#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_PAGE_IB_BASE_HI +#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SIZE +#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_PAGE_SKIP_CNTL +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_PAGE_CONTEXT_STATUS +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_PAGE_DOORBELL +#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_PAGE_STATUS +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_PAGE_DOORBELL_LOG +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_PAGE_WATERMARK +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_PAGE_DOORBELL_OFFSET +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_PAGE_CSA_ADDR_LO +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_CSA_ADDR_HI +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_IB_SUB_REMAIN +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_PAGE_PREEMPT +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_PAGE_DUMMY_REG +#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_PAGE_RB_AQL_CNTL +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_PAGE_MINOR_PTR_UPDATE +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_PAGE_MIDCMD_DATA0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA1 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA2 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA3 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA4 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA5 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA6 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA7 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_DATA8 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_PAGE_MIDCMD_CNTL +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC0_RB_CNTL +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC0_RB_BASE +#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_BASE_HI +#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC0_RB_RPTR +#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_HI +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR +#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_HI +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_CNTL +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC0_RB_RPTR_ADDR_HI +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_RPTR_ADDR_LO +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_IB_CNTL +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC0_IB_RPTR +#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_OFFSET +#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC0_IB_BASE_LO +#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC0_IB_BASE_HI +#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SIZE +#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_SKIP_CNTL +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC0_CONTEXT_STATUS +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC0_DOORBELL +#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC0_STATUS +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC0_DOORBELL_LOG +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC0_WATERMARK +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC0_DOORBELL_OFFSET +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC0_CSA_ADDR_LO +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_CSA_ADDR_HI +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_IB_SUB_REMAIN +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC0_PREEMPT +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC0_DUMMY_REG +#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC0_RB_AQL_CNTL +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC0_MINOR_PTR_UPDATE +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC0_MIDCMD_DATA0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA1 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA2 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA3 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA4 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA5 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA6 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA7 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_DATA8 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC0_MIDCMD_CNTL +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC1_RB_CNTL +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC1_RB_BASE +#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_BASE_HI +#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC1_RB_RPTR +#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_HI +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR +#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_HI +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_CNTL +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC1_RB_RPTR_ADDR_HI +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_RPTR_ADDR_LO +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_IB_CNTL +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC1_IB_RPTR +#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_OFFSET +#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC1_IB_BASE_LO +#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC1_IB_BASE_HI +#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SIZE +#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_SKIP_CNTL +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC1_CONTEXT_STATUS +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC1_DOORBELL +#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC1_STATUS +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC1_DOORBELL_LOG +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC1_WATERMARK +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC1_DOORBELL_OFFSET +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC1_CSA_ADDR_LO +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_CSA_ADDR_HI +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_IB_SUB_REMAIN +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC1_PREEMPT +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC1_DUMMY_REG +#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC1_RB_AQL_CNTL +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC1_MINOR_PTR_UPDATE +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC1_MIDCMD_DATA0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA1 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA2 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA3 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA4 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA5 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA6 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA7 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_DATA8 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC1_MIDCMD_CNTL +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC2_RB_CNTL +#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC2_RB_BASE +#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_BASE_HI +#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC2_RB_RPTR +#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_RPTR_HI +#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR +#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_HI +#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_CNTL +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC2_RB_RPTR_ADDR_HI +#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_RPTR_ADDR_LO +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_IB_CNTL +#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC2_IB_RPTR +#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC2_IB_OFFSET +#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC2_IB_BASE_LO +#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC2_IB_BASE_HI +#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_IB_SIZE +#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC2_SKIP_CNTL +#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC2_CONTEXT_STATUS +#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC2_DOORBELL +#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC2_STATUS +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC2_DOORBELL_LOG +#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC2_WATERMARK +#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC2_DOORBELL_OFFSET +#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC2_CSA_ADDR_LO +#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_CSA_ADDR_HI +#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_IB_SUB_REMAIN +#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC2_PREEMPT +#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC2_DUMMY_REG +#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC2_RB_AQL_CNTL +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC2_MINOR_PTR_UPDATE +#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC2_MIDCMD_DATA0 +#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA1 +#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA2 +#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA3 +#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA4 +#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA5 +#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA6 +#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA7 +#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_DATA8 +#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC2_MIDCMD_CNTL +#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC3_RB_CNTL +#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC3_RB_BASE +#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_BASE_HI +#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC3_RB_RPTR +#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_RPTR_HI +#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR +#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_HI +#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_CNTL +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC3_RB_RPTR_ADDR_HI +#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_RPTR_ADDR_LO +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_IB_CNTL +#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC3_IB_RPTR +#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC3_IB_OFFSET +#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC3_IB_BASE_LO +#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC3_IB_BASE_HI +#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_IB_SIZE +#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC3_SKIP_CNTL +#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC3_CONTEXT_STATUS +#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC3_DOORBELL +#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC3_STATUS +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC3_DOORBELL_LOG +#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC3_WATERMARK +#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC3_DOORBELL_OFFSET +#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC3_CSA_ADDR_LO +#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_CSA_ADDR_HI +#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_IB_SUB_REMAIN +#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC3_PREEMPT +#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC3_DUMMY_REG +#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC3_RB_AQL_CNTL +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC3_MINOR_PTR_UPDATE +#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC3_MIDCMD_DATA0 +#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA1 +#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA2 +#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA3 +#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA4 +#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA5 +#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA6 +#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA7 +#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_DATA8 +#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC3_MIDCMD_CNTL +#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC4_RB_CNTL +#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC4_RB_BASE +#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_BASE_HI +#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC4_RB_RPTR +#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_RPTR_HI +#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR +#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_HI +#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_CNTL +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC4_RB_RPTR_ADDR_HI +#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_RPTR_ADDR_LO +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_IB_CNTL +#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC4_IB_RPTR +#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC4_IB_OFFSET +#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC4_IB_BASE_LO +#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC4_IB_BASE_HI +#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_IB_SIZE +#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC4_SKIP_CNTL +#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC4_CONTEXT_STATUS +#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC4_DOORBELL +#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC4_STATUS +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC4_DOORBELL_LOG +#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC4_WATERMARK +#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC4_DOORBELL_OFFSET +#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC4_CSA_ADDR_LO +#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_CSA_ADDR_HI +#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_IB_SUB_REMAIN +#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC4_PREEMPT +#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC4_DUMMY_REG +#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC4_RB_AQL_CNTL +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC4_MINOR_PTR_UPDATE +#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC4_MIDCMD_DATA0 +#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA1 +#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA2 +#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA3 +#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA4 +#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA5 +#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA6 +#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA7 +#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_DATA8 +#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC4_MIDCMD_CNTL +#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC5_RB_CNTL +#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC5_RB_BASE +#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_BASE_HI +#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC5_RB_RPTR +#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_RPTR_HI +#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR +#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_HI +#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_CNTL +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC5_RB_RPTR_ADDR_HI +#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_RPTR_ADDR_LO +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_IB_CNTL +#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC5_IB_RPTR +#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC5_IB_OFFSET +#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC5_IB_BASE_LO +#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC5_IB_BASE_HI +#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_IB_SIZE +#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC5_SKIP_CNTL +#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC5_CONTEXT_STATUS +#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC5_DOORBELL +#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC5_STATUS +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC5_DOORBELL_LOG +#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC5_WATERMARK +#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC5_DOORBELL_OFFSET +#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC5_CSA_ADDR_LO +#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_CSA_ADDR_HI +#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_IB_SUB_REMAIN +#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC5_PREEMPT +#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC5_DUMMY_REG +#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC5_RB_AQL_CNTL +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC5_MINOR_PTR_UPDATE +#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC5_MIDCMD_DATA0 +#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA1 +#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA2 +#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA3 +#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA4 +#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA5 +#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA6 +#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA7 +#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_DATA8 +#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC5_MIDCMD_CNTL +#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC6_RB_CNTL +#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC6_RB_BASE +#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_BASE_HI +#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC6_RB_RPTR +#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_RPTR_HI +#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR +#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_HI +#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_CNTL +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC6_RB_RPTR_ADDR_HI +#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_RPTR_ADDR_LO +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_IB_CNTL +#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC6_IB_RPTR +#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC6_IB_OFFSET +#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC6_IB_BASE_LO +#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC6_IB_BASE_HI +#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_IB_SIZE +#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC6_SKIP_CNTL +#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC6_CONTEXT_STATUS +#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC6_DOORBELL +#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC6_STATUS +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC6_DOORBELL_LOG +#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC6_WATERMARK +#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC6_DOORBELL_OFFSET +#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC6_CSA_ADDR_LO +#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_CSA_ADDR_HI +#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_IB_SUB_REMAIN +#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC6_PREEMPT +#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC6_DUMMY_REG +#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC6_RB_AQL_CNTL +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC6_MINOR_PTR_UPDATE +#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC6_MIDCMD_DATA0 +#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA1 +#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA2 +#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA3 +#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA4 +#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA5 +#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA6 +#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA7 +#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_DATA8 +#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC6_MIDCMD_CNTL +#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_RLC7_RB_CNTL +#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_RLC7_RB_BASE +#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_BASE_HI +#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_RLC7_RB_RPTR +#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_RPTR_HI +#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR +#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_HI +#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_CNTL +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA0_RLC7_RB_RPTR_ADDR_HI +#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_RPTR_ADDR_LO +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_IB_CNTL +#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA0_RLC7_IB_RPTR +#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC7_IB_OFFSET +#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_RLC7_IB_BASE_LO +#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA0_RLC7_IB_BASE_HI +#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_IB_SIZE +#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC7_SKIP_CNTL +#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA0_RLC7_CONTEXT_STATUS +#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA0_RLC7_DOORBELL +#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_RLC7_STATUS +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA0_RLC7_DOORBELL_LOG +#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_RLC7_WATERMARK +#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA0_RLC7_DOORBELL_OFFSET +#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_RLC7_CSA_ADDR_LO +#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_CSA_ADDR_HI +#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_IB_SUB_REMAIN +#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA0_RLC7_PREEMPT +#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_RLC7_DUMMY_REG +#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_RLC7_RB_AQL_CNTL +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA0_RLC7_MINOR_PTR_UPDATE +#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_RLC7_MIDCMD_DATA0 +#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA1 +#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA2 +#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA3 +#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA4 +#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA5 +#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA6 +#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA7 +#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_DATA8 +#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_RLC7_MIDCMD_CNTL +#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h new file mode 100644 index 000000000000..681233a55a1d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_2_2_OFFSET_HEADER +#define _sdma1_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma1_sdma1dec +// base address: 0x6180 +#define mmSDMA1_UCODE_ADDR 0x0000 +#define mmSDMA1_UCODE_ADDR_BASE_IDX 0 +#define mmSDMA1_UCODE_DATA 0x0001 +#define mmSDMA1_UCODE_DATA_BASE_IDX 0 +#define mmSDMA1_VM_CNTL 0x0004 +#define mmSDMA1_VM_CNTL_BASE_IDX 0 +#define mmSDMA1_VM_CTX_LO 0x0005 +#define mmSDMA1_VM_CTX_LO_BASE_IDX 0 +#define mmSDMA1_VM_CTX_HI 0x0006 +#define mmSDMA1_VM_CTX_HI_BASE_IDX 0 +#define mmSDMA1_ACTIVE_FCN_ID 0x0007 +#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 +#define mmSDMA1_VM_CTX_CNTL 0x0008 +#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 +#define mmSDMA1_VIRT_RESET_REQ 0x0009 +#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 +#define mmSDMA1_VF_ENABLE 0x000a +#define mmSDMA1_VF_ENABLE_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 +#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE0 0x000f +#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE1 0x0010 +#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE2 0x0011 +#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 +#define mmSDMA1_PUB_REG_TYPE3 0x0012 +#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 +#define mmSDMA1_MMHUB_CNTL 0x0013 +#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 +#define mmSDMA1_POWER_CNTL 0x001a +#define mmSDMA1_POWER_CNTL_BASE_IDX 0 +#define mmSDMA1_CLK_CTRL 0x001b +#define mmSDMA1_CLK_CTRL_BASE_IDX 0 +#define mmSDMA1_CNTL 0x001c +#define mmSDMA1_CNTL_BASE_IDX 0 +#define mmSDMA1_CHICKEN_BITS 0x001d +#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 +#define mmSDMA1_GB_ADDR_CONFIG 0x001e +#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 +#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 +#define mmSDMA1_RB_RPTR_FETCH 0x0022 +#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 +#define mmSDMA1_IB_OFFSET_FETCH 0x0023 +#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 +#define mmSDMA1_PROGRAM 0x0024 +#define mmSDMA1_PROGRAM_BASE_IDX 0 +#define mmSDMA1_STATUS_REG 0x0025 +#define mmSDMA1_STATUS_REG_BASE_IDX 0 +#define mmSDMA1_STATUS1_REG 0x0026 +#define mmSDMA1_STATUS1_REG_BASE_IDX 0 +#define mmSDMA1_RD_BURST_CNTL 0x0027 +#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 +#define mmSDMA1_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 +#define mmSDMA1_UCODE_CHECKSUM 0x0029 +#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 +#define mmSDMA1_F32_CNTL 0x002a +#define mmSDMA1_F32_CNTL_BASE_IDX 0 +#define mmSDMA1_FREEZE 0x002b +#define mmSDMA1_FREEZE_BASE_IDX 0 +#define mmSDMA1_PHASE0_QUANTUM 0x002c +#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 +#define mmSDMA1_PHASE1_QUANTUM 0x002d +#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 +#define mmSDMA1_EDC_CONFIG 0x0032 +#define mmSDMA1_EDC_CONFIG_BASE_IDX 0 +#define mmSDMA1_BA_THRESHOLD 0x0033 +#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 +#define mmSDMA1_ID 0x0034 +#define mmSDMA1_ID_BASE_IDX 0 +#define mmSDMA1_VERSION 0x0035 +#define mmSDMA1_VERSION_BASE_IDX 0 +#define mmSDMA1_EDC_COUNTER 0x0036 +#define mmSDMA1_EDC_COUNTER_BASE_IDX 0 +#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 +#define mmSDMA1_STATUS2_REG 0x0038 +#define mmSDMA1_STATUS2_REG_BASE_IDX 0 +#define mmSDMA1_ATOMIC_CNTL 0x0039 +#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 +#define mmSDMA1_ATOMIC_PREOP_LO 0x003a +#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 +#define mmSDMA1_ATOMIC_PREOP_HI 0x003b +#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 +#define mmSDMA1_UTCL1_CNTL 0x003c +#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 +#define mmSDMA1_UTCL1_WATERMK 0x003d +#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_STATUS 0x003e +#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_STATUS 0x003f +#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV0 0x0040 +#define mmSDMA1_UTCL1_INV0_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV1 0x0041 +#define mmSDMA1_UTCL1_INV1_BASE_IDX 0 +#define mmSDMA1_UTCL1_INV2 0x0042 +#define mmSDMA1_UTCL1_INV2_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 +#define mmSDMA1_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 +#define mmSDMA1_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 +#define mmSDMA1_UTCL1_TIMEOUT 0x0047 +#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 +#define mmSDMA1_UTCL1_PAGE 0x0048 +#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 +#define mmSDMA1_POWER_CNTL_IDLE 0x0049 +#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 +#define mmSDMA1_RELAX_ORDERING_LUT 0x004a +#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 +#define mmSDMA1_CHICKEN_BITS_2 0x004b +#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 +#define mmSDMA1_STATUS3_REG 0x004c +#define mmSDMA1_STATUS3_REG_BASE_IDX 0 +#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PHASE2_QUANTUM 0x004f +#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 +#define mmSDMA1_ERROR_LOG 0x0050 +#define mmSDMA1_ERROR_LOG_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG0 0x0051 +#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG1 0x0052 +#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG2 0x0053 +#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 +#define mmSDMA1_PUB_DUMMY_REG3 0x0054 +#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 +#define mmSDMA1_F32_COUNTER 0x0055 +#define mmSDMA1_F32_COUNTER_BASE_IDX 0 +#define mmSDMA1_UNBREAKABLE 0x0056 +#define mmSDMA1_UNBREAKABLE_BASE_IDX 0 +#define mmSDMA1_PERFMON_CNTL 0x0057 +#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 +#define mmSDMA1_CRD_CNTL 0x005b +#define mmSDMA1_CRD_CNTL_BASE_IDX 0 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define mmSDMA1_ULV_CNTL 0x005e +#define mmSDMA1_ULV_CNTL_BASE_IDX 0 +#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 +#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA1_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define mmSDMA1_GFX_RB_CNTL 0x0080 +#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_RB_BASE 0x0081 +#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 +#define mmSDMA1_GFX_RB_BASE_HI 0x0082 +#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR 0x0083 +#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR 0x0085 +#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_IB_CNTL 0x008a +#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_IB_RPTR 0x008b +#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_GFX_IB_OFFSET 0x008c +#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_GFX_IB_BASE_LO 0x008d +#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_GFX_IB_BASE_HI 0x008e +#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_GFX_IB_SIZE 0x008f +#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_GFX_SKIP_CNTL 0x0090 +#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL 0x0092 +#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 +#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_STATUS 0x00a8 +#define mmSDMA1_GFX_STATUS_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_GFX_WATERMARK 0x00aa +#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 +#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_GFX_PREEMPT 0x00b0 +#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 +#define mmSDMA1_GFX_DUMMY_REG 0x00b1 +#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_CNTL 0x00d8 +#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_BASE 0x00d9 +#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_BASE_HI 0x00da +#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR 0x00db +#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR 0x00dd +#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_CNTL 0x00e2 +#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_RPTR 0x00e3 +#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_SIZE 0x00e7 +#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL 0x00ea +#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 +#define mmSDMA1_PAGE_STATUS 0x0100 +#define mmSDMA1_PAGE_STATUS_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_PAGE_WATERMARK 0x0102 +#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 +#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_PAGE_PREEMPT 0x0108 +#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 +#define mmSDMA1_PAGE_DUMMY_REG 0x0109 +#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_CNTL 0x0130 +#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_BASE 0x0131 +#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR 0x0133 +#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR 0x0135 +#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_CNTL 0x013a +#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_RPTR 0x013b +#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_OFFSET 0x013c +#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_BASE_LO 0x013d +#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_BASE_HI 0x013e +#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_SIZE 0x013f +#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL 0x0142 +#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC0_STATUS 0x0158 +#define mmSDMA1_RLC0_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC0_WATERMARK 0x015a +#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC0_PREEMPT 0x0160 +#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC0_DUMMY_REG 0x0161 +#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_CNTL 0x0188 +#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_BASE 0x0189 +#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_BASE_HI 0x018a +#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR 0x018b +#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR 0x018d +#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_CNTL 0x0192 +#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_RPTR 0x0193 +#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_OFFSET 0x0194 +#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_SIZE 0x0197 +#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL 0x019a +#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC1_STATUS 0x01b0 +#define mmSDMA1_RLC1_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC1_WATERMARK 0x01b2 +#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC1_PREEMPT 0x01b8 +#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_CNTL 0x01e0 +#define mmSDMA1_RLC2_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_BASE 0x01e1 +#define mmSDMA1_RLC2_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_RPTR 0x01e3 +#define mmSDMA1_RLC2_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR 0x01e5 +#define mmSDMA1_RLC2_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_CNTL 0x01ea +#define mmSDMA1_RLC2_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_RPTR 0x01eb +#define mmSDMA1_RLC2_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_OFFSET 0x01ec +#define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_SIZE 0x01ef +#define mmSDMA1_RLC2_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC2_DOORBELL 0x01f2 +#define mmSDMA1_RLC2_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC2_STATUS 0x0208 +#define mmSDMA1_RLC2_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC2_WATERMARK 0x020a +#define mmSDMA1_RLC2_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC2_PREEMPT 0x0210 +#define mmSDMA1_RLC2_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC2_DUMMY_REG 0x0211 +#define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_CNTL 0x0238 +#define mmSDMA1_RLC3_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_BASE 0x0239 +#define mmSDMA1_RLC3_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_BASE_HI 0x023a +#define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_RPTR 0x023b +#define mmSDMA1_RLC3_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR 0x023d +#define mmSDMA1_RLC3_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_CNTL 0x0242 +#define mmSDMA1_RLC3_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_RPTR 0x0243 +#define mmSDMA1_RLC3_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_OFFSET 0x0244 +#define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_SIZE 0x0247 +#define mmSDMA1_RLC3_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC3_DOORBELL 0x024a +#define mmSDMA1_RLC3_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC3_STATUS 0x0260 +#define mmSDMA1_RLC3_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC3_WATERMARK 0x0262 +#define mmSDMA1_RLC3_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC3_PREEMPT 0x0268 +#define mmSDMA1_RLC3_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC3_DUMMY_REG 0x0269 +#define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_CNTL 0x0290 +#define mmSDMA1_RLC4_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_BASE 0x0291 +#define mmSDMA1_RLC4_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_RPTR 0x0293 +#define mmSDMA1_RLC4_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR 0x0295 +#define mmSDMA1_RLC4_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_CNTL 0x029a +#define mmSDMA1_RLC4_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_RPTR 0x029b +#define mmSDMA1_RLC4_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_OFFSET 0x029c +#define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_BASE_LO 0x029d +#define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_BASE_HI 0x029e +#define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_SIZE 0x029f +#define mmSDMA1_RLC4_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC4_DOORBELL 0x02a2 +#define mmSDMA1_RLC4_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC4_STATUS 0x02b8 +#define mmSDMA1_RLC4_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC4_WATERMARK 0x02ba +#define mmSDMA1_RLC4_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC4_PREEMPT 0x02c0 +#define mmSDMA1_RLC4_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_CNTL 0x02e8 +#define mmSDMA1_RLC5_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_BASE 0x02e9 +#define mmSDMA1_RLC5_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_RPTR 0x02eb +#define mmSDMA1_RLC5_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR 0x02ed +#define mmSDMA1_RLC5_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_CNTL 0x02f2 +#define mmSDMA1_RLC5_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_RPTR 0x02f3 +#define mmSDMA1_RLC5_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_SIZE 0x02f7 +#define mmSDMA1_RLC5_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC5_DOORBELL 0x02fa +#define mmSDMA1_RLC5_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC5_STATUS 0x0310 +#define mmSDMA1_RLC5_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC5_WATERMARK 0x0312 +#define mmSDMA1_RLC5_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC5_PREEMPT 0x0318 +#define mmSDMA1_RLC5_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC5_DUMMY_REG 0x0319 +#define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_CNTL 0x0340 +#define mmSDMA1_RLC6_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_BASE 0x0341 +#define mmSDMA1_RLC6_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_RPTR 0x0343 +#define mmSDMA1_RLC6_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR 0x0345 +#define mmSDMA1_RLC6_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_CNTL 0x034a +#define mmSDMA1_RLC6_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_RPTR 0x034b +#define mmSDMA1_RLC6_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_OFFSET 0x034c +#define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_BASE_LO 0x034d +#define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_BASE_HI 0x034e +#define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_SIZE 0x034f +#define mmSDMA1_RLC6_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC6_DOORBELL 0x0352 +#define mmSDMA1_RLC6_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC6_STATUS 0x0368 +#define mmSDMA1_RLC6_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC6_WATERMARK 0x036a +#define mmSDMA1_RLC6_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC6_PREEMPT 0x0370 +#define mmSDMA1_RLC6_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC6_DUMMY_REG 0x0371 +#define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_CNTL 0x0398 +#define mmSDMA1_RLC7_RB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_BASE 0x0399 +#define mmSDMA1_RLC7_RB_BASE_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_BASE_HI 0x039a +#define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_RPTR 0x039b +#define mmSDMA1_RLC7_RB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR 0x039d +#define mmSDMA1_RLC7_RB_WPTR_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_CNTL 0x03a2 +#define mmSDMA1_RLC7_IB_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_RPTR 0x03a3 +#define mmSDMA1_RLC7_IB_RPTR_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_SIZE 0x03a7 +#define mmSDMA1_RLC7_IB_SIZE_BASE_IDX 0 +#define mmSDMA1_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC7_DOORBELL 0x03aa +#define mmSDMA1_RLC7_DOORBELL_BASE_IDX 0 +#define mmSDMA1_RLC7_STATUS 0x03c0 +#define mmSDMA1_RLC7_STATUS_BASE_IDX 0 +#define mmSDMA1_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX 0 +#define mmSDMA1_RLC7_WATERMARK 0x03c2 +#define mmSDMA1_RLC7_WATERMARK_BASE_IDX 0 +#define mmSDMA1_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0 +#define mmSDMA1_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0 +#define mmSDMA1_RLC7_PREEMPT 0x03c8 +#define mmSDMA1_RLC7_PREEMPT_BASE_IDX 0 +#define mmSDMA1_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define mmSDMA1_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0 +#define mmSDMA1_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0 +#define mmSDMA1_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h new file mode 100644 index 000000000000..ac2468e6bc46 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma1_4_2_2_SH_MASK_HEADER +#define _sdma1_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma1_sdma1dec +//SDMA1_UCODE_ADDR +#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA1_UCODE_DATA +#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_VM_CNTL +#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA1_VM_CTX_LO +#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_VM_CTX_HI +#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_ACTIVE_FCN_ID +#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA1_VM_CTX_CNTL +#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA1_VIRT_RESET_REQ +#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA1_VF_ENABLE +#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA1_CONTEXT_REG_TYPE0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L +#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA1_CONTEXT_REG_TYPE1 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA1_CONTEXT_REG_TYPE2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA1_CONTEXT_REG_TYPE3 +#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_PUB_REG_TYPE0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE2 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 +#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 +#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b +#define SDMA1_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e +#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L +#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L +#define SDMA1_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L +#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA1_PUB_REG_TYPE3 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA1_PUB_REG_TYPE3__SDMA1_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA1_PUB_REG_TYPE3__SDMA1_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA1_MMHUB_CNTL +#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA1_CONTEXT_GROUP_BOUNDARY +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_POWER_CNTL +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA1_CLK_CTRL +#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA1_CNTL +#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA1_CHICKEN_BITS +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA1_GB_ADDR_CONFIG +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_GB_ADDR_CONFIG_READ +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA1_RB_RPTR_FETCH_HI +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA1_RB_RPTR_FETCH +#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA1_IB_OFFSET_FETCH +#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA1_PROGRAM +#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA1_STATUS_REG +#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA1_STATUS1_REG +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA1_RD_BURST_CNTL +#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA1_HBM_PAGE_CONFIG +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA1_UCODE_CHECKSUM +#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA1_F32_CNTL +#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L +//SDMA1_FREEZE +#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA1_PHASE0_QUANTUM +#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_PHASE1_QUANTUM +#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_EDC_CONFIG +#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA1_BA_THRESHOLD +#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA1_ID +#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA1_VERSION +#define SDMA1_VERSION__MINVER__SHIFT 0x0 +#define SDMA1_VERSION__MAJVER__SHIFT 0x8 +#define SDMA1_VERSION__REV__SHIFT 0x10 +#define SDMA1_VERSION__MINVER_MASK 0x0000007FL +#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA1_VERSION__REV_MASK 0x003F0000L +//SDMA1_EDC_COUNTER +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA1_EDC_COUNTER_CLEAR +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA1_STATUS2_REG +#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA1_ATOMIC_CNTL +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA1_ATOMIC_PREOP_LO +#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_ATOMIC_PREOP_HI +#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_CNTL +#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA1_UTCL1_WATERMK +#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA1_UTCL1_RD_STATUS +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA1_UTCL1_WR_STATUS +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA1_UTCL1_INV0 +#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA1_UTCL1_INV1 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_INV2 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_RD_XNACK1 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_WR_XNACK0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_UTCL1_WR_XNACK1 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA1_UTCL1_TIMEOUT +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA1_UTCL1_PAGE +#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA1_POWER_CNTL_IDLE +#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA1_RELAX_ORDERING_LUT +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA1_CHICKEN_BITS_2 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA1_STATUS3_REG +#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA1_PHYSICAL_ADDR_LO +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA1_PHYSICAL_ADDR_HI +#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA1_PHASE2_QUANTUM +#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA1_ERROR_LOG +#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA1_PUB_DUMMY_REG0 +#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG1 +#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG2 +#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA1_PUB_DUMMY_REG3 +#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA1_F32_COUNTER +#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA1_UNBREAKABLE +#define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA1_PERFMON_CNTL +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA1_PERFCOUNTER0_RESULT +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER1_RESULT +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA1_CRD_CNTL +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA1_GPU_IOV_VIOLATION_LOG +#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA1_ULV_CNTL +#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA1_EA_DBIT_ADDR_DATA +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA1_EA_DBIT_ADDR_INDEX +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA1_GPU_IOV_VIOLATION_LOG2 +#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA1_GFX_RB_CNTL +#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_GFX_RB_BASE +#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_BASE_HI +#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_GFX_RB_RPTR +#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_HI +#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR +#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_HI +#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_CNTL +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_GFX_RB_RPTR_ADDR_HI +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_RPTR_ADDR_LO +#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_IB_CNTL +#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_GFX_IB_RPTR +#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_OFFSET +#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_GFX_IB_BASE_LO +#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_GFX_IB_BASE_HI +#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SIZE +#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_GFX_SKIP_CNTL +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_GFX_CONTEXT_STATUS +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_GFX_DOORBELL +#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_GFX_CONTEXT_CNTL +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA1_GFX_STATUS +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_GFX_DOORBELL_LOG +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_GFX_WATERMARK +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_GFX_DOORBELL_OFFSET +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_GFX_CSA_ADDR_LO +#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_CSA_ADDR_HI +#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_IB_SUB_REMAIN +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_GFX_PREEMPT +#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_GFX_DUMMY_REG +#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_GFX_RB_AQL_CNTL +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_GFX_MINOR_PTR_UPDATE +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_GFX_MIDCMD_DATA0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA1 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA2 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA3 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA4 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA5 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA6 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA7 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_DATA8 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_GFX_MIDCMD_CNTL +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_PAGE_RB_CNTL +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_PAGE_RB_BASE +#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_BASE_HI +#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_PAGE_RB_RPTR +#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_HI +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR +#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_HI +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_CNTL +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_PAGE_RB_RPTR_ADDR_HI +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_RPTR_ADDR_LO +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_IB_CNTL +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_PAGE_IB_RPTR +#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_OFFSET +#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_PAGE_IB_BASE_LO +#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_PAGE_IB_BASE_HI +#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SIZE +#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_PAGE_SKIP_CNTL +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_PAGE_CONTEXT_STATUS +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_PAGE_DOORBELL +#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_PAGE_STATUS +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_PAGE_DOORBELL_LOG +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_PAGE_WATERMARK +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_PAGE_DOORBELL_OFFSET +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_PAGE_CSA_ADDR_LO +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_CSA_ADDR_HI +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_IB_SUB_REMAIN +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_PAGE_PREEMPT +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_PAGE_DUMMY_REG +#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_PAGE_RB_AQL_CNTL +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_PAGE_MINOR_PTR_UPDATE +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_PAGE_MIDCMD_DATA0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA1 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA2 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA3 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA4 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA5 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA6 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA7 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_DATA8 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_PAGE_MIDCMD_CNTL +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC0_RB_CNTL +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC0_RB_BASE +#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_BASE_HI +#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC0_RB_RPTR +#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_HI +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR +#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_HI +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_CNTL +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC0_RB_RPTR_ADDR_HI +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_RPTR_ADDR_LO +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_IB_CNTL +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC0_IB_RPTR +#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_OFFSET +#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC0_IB_BASE_LO +#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC0_IB_BASE_HI +#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SIZE +#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC0_SKIP_CNTL +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC0_CONTEXT_STATUS +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC0_DOORBELL +#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC0_STATUS +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC0_DOORBELL_LOG +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC0_WATERMARK +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC0_DOORBELL_OFFSET +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC0_CSA_ADDR_LO +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_CSA_ADDR_HI +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_IB_SUB_REMAIN +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC0_PREEMPT +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC0_DUMMY_REG +#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC0_RB_AQL_CNTL +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC0_MINOR_PTR_UPDATE +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC0_MIDCMD_DATA0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA1 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA2 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA3 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA4 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA5 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA6 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA7 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_DATA8 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC0_MIDCMD_CNTL +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC1_RB_CNTL +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC1_RB_BASE +#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_BASE_HI +#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC1_RB_RPTR +#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_HI +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR +#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_HI +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_CNTL +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC1_RB_RPTR_ADDR_HI +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_RPTR_ADDR_LO +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_IB_CNTL +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC1_IB_RPTR +#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_OFFSET +#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC1_IB_BASE_LO +#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC1_IB_BASE_HI +#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SIZE +#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC1_SKIP_CNTL +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC1_CONTEXT_STATUS +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC1_DOORBELL +#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC1_STATUS +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC1_DOORBELL_LOG +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC1_WATERMARK +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC1_DOORBELL_OFFSET +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC1_CSA_ADDR_LO +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_CSA_ADDR_HI +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_IB_SUB_REMAIN +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC1_PREEMPT +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC1_DUMMY_REG +#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC1_RB_AQL_CNTL +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC1_MINOR_PTR_UPDATE +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC1_MIDCMD_DATA0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA1 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA2 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA3 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA4 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA5 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA6 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA7 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_DATA8 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC1_MIDCMD_CNTL +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC2_RB_CNTL +#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC2_RB_BASE +#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_BASE_HI +#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC2_RB_RPTR +#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_RPTR_HI +#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR +#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_HI +#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_CNTL +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC2_RB_RPTR_ADDR_HI +#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_RPTR_ADDR_LO +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_IB_CNTL +#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC2_IB_RPTR +#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC2_IB_OFFSET +#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC2_IB_BASE_LO +#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC2_IB_BASE_HI +#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_IB_SIZE +#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC2_SKIP_CNTL +#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC2_CONTEXT_STATUS +#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC2_DOORBELL +#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC2_STATUS +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC2_DOORBELL_LOG +#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC2_WATERMARK +#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC2_DOORBELL_OFFSET +#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC2_CSA_ADDR_LO +#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_CSA_ADDR_HI +#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_IB_SUB_REMAIN +#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC2_PREEMPT +#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC2_DUMMY_REG +#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC2_RB_AQL_CNTL +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC2_MINOR_PTR_UPDATE +#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC2_MIDCMD_DATA0 +#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA1 +#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA2 +#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA3 +#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA4 +#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA5 +#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA6 +#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA7 +#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_DATA8 +#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC2_MIDCMD_CNTL +#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC3_RB_CNTL +#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC3_RB_BASE +#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_BASE_HI +#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC3_RB_RPTR +#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_RPTR_HI +#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR +#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_HI +#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_CNTL +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC3_RB_RPTR_ADDR_HI +#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_RPTR_ADDR_LO +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_IB_CNTL +#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC3_IB_RPTR +#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC3_IB_OFFSET +#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC3_IB_BASE_LO +#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC3_IB_BASE_HI +#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_IB_SIZE +#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC3_SKIP_CNTL +#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC3_CONTEXT_STATUS +#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC3_DOORBELL +#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC3_STATUS +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC3_DOORBELL_LOG +#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC3_WATERMARK +#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC3_DOORBELL_OFFSET +#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC3_CSA_ADDR_LO +#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_CSA_ADDR_HI +#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_IB_SUB_REMAIN +#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC3_PREEMPT +#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC3_DUMMY_REG +#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC3_RB_AQL_CNTL +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC3_MINOR_PTR_UPDATE +#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC3_MIDCMD_DATA0 +#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA1 +#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA2 +#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA3 +#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA4 +#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA5 +#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA6 +#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA7 +#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_DATA8 +#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC3_MIDCMD_CNTL +#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC4_RB_CNTL +#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC4_RB_BASE +#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_BASE_HI +#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC4_RB_RPTR +#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_RPTR_HI +#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR +#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_HI +#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_CNTL +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC4_RB_RPTR_ADDR_HI +#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_RPTR_ADDR_LO +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_IB_CNTL +#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC4_IB_RPTR +#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC4_IB_OFFSET +#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC4_IB_BASE_LO +#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC4_IB_BASE_HI +#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_IB_SIZE +#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC4_SKIP_CNTL +#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC4_CONTEXT_STATUS +#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC4_DOORBELL +#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC4_STATUS +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC4_DOORBELL_LOG +#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC4_WATERMARK +#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC4_DOORBELL_OFFSET +#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC4_CSA_ADDR_LO +#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_CSA_ADDR_HI +#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_IB_SUB_REMAIN +#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC4_PREEMPT +#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC4_DUMMY_REG +#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC4_RB_AQL_CNTL +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC4_MINOR_PTR_UPDATE +#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC4_MIDCMD_DATA0 +#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA1 +#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA2 +#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA3 +#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA4 +#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA5 +#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA6 +#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA7 +#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_DATA8 +#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC4_MIDCMD_CNTL +#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC5_RB_CNTL +#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC5_RB_BASE +#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_BASE_HI +#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC5_RB_RPTR +#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_RPTR_HI +#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR +#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_HI +#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_CNTL +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC5_RB_RPTR_ADDR_HI +#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_RPTR_ADDR_LO +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_IB_CNTL +#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC5_IB_RPTR +#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC5_IB_OFFSET +#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC5_IB_BASE_LO +#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC5_IB_BASE_HI +#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_IB_SIZE +#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC5_SKIP_CNTL +#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC5_CONTEXT_STATUS +#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC5_DOORBELL +#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC5_STATUS +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC5_DOORBELL_LOG +#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC5_WATERMARK +#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC5_DOORBELL_OFFSET +#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC5_CSA_ADDR_LO +#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_CSA_ADDR_HI +#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_IB_SUB_REMAIN +#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC5_PREEMPT +#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC5_DUMMY_REG +#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC5_RB_AQL_CNTL +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC5_MINOR_PTR_UPDATE +#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC5_MIDCMD_DATA0 +#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA1 +#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA2 +#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA3 +#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA4 +#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA5 +#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA6 +#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA7 +#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_DATA8 +#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC5_MIDCMD_CNTL +#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC6_RB_CNTL +#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC6_RB_BASE +#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_BASE_HI +#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC6_RB_RPTR +#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_RPTR_HI +#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR +#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_HI +#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_CNTL +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC6_RB_RPTR_ADDR_HI +#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_RPTR_ADDR_LO +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_IB_CNTL +#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC6_IB_RPTR +#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC6_IB_OFFSET +#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC6_IB_BASE_LO +#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC6_IB_BASE_HI +#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_IB_SIZE +#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC6_SKIP_CNTL +#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC6_CONTEXT_STATUS +#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC6_DOORBELL +#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC6_STATUS +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC6_DOORBELL_LOG +#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC6_WATERMARK +#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC6_DOORBELL_OFFSET +#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC6_CSA_ADDR_LO +#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_CSA_ADDR_HI +#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_IB_SUB_REMAIN +#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC6_PREEMPT +#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC6_DUMMY_REG +#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC6_RB_AQL_CNTL +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC6_MINOR_PTR_UPDATE +#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC6_MIDCMD_DATA0 +#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA1 +#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA2 +#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA3 +#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA4 +#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA5 +#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA6 +#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA7 +#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_DATA8 +#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC6_MIDCMD_CNTL +#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_RLC7_RB_CNTL +#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_RLC7_RB_BASE +#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_BASE_HI +#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_RLC7_RB_RPTR +#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_RPTR_HI +#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR +#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_HI +#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_CNTL +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA1_RLC7_RB_RPTR_ADDR_HI +#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_RPTR_ADDR_LO +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_IB_CNTL +#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA1_RLC7_IB_RPTR +#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC7_IB_OFFSET +#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_RLC7_IB_BASE_LO +#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA1_RLC7_IB_BASE_HI +#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_IB_SIZE +#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC7_SKIP_CNTL +#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA1_RLC7_CONTEXT_STATUS +#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA1_RLC7_DOORBELL +#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_RLC7_STATUS +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA1_RLC7_DOORBELL_LOG +#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_RLC7_WATERMARK +#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA1_RLC7_DOORBELL_OFFSET +#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_RLC7_CSA_ADDR_LO +#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_CSA_ADDR_HI +#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_IB_SUB_REMAIN +#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA1_RLC7_PREEMPT +#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_RLC7_DUMMY_REG +#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_RLC7_RB_AQL_CNTL +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA1_RLC7_MINOR_PTR_UPDATE +#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_RLC7_MIDCMD_DATA0 +#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA1 +#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA2 +#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA3 +#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA4 +#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA5 +#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA6 +#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA7 +#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_DATA8 +#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_RLC7_MIDCMD_CNTL +#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h new file mode 100644 index 000000000000..6aa0813915c2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma2_4_2_2_OFFSET_HEADER +#define _sdma2_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma2_sdma2dec +// base address: 0x78000 +#define mmSDMA2_UCODE_ADDR 0x0000 +#define mmSDMA2_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA2_UCODE_DATA 0x0001 +#define mmSDMA2_UCODE_DATA_BASE_IDX 1 +#define mmSDMA2_VM_CNTL 0x0004 +#define mmSDMA2_VM_CNTL_BASE_IDX 1 +#define mmSDMA2_VM_CTX_LO 0x0005 +#define mmSDMA2_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA2_VM_CTX_HI 0x0006 +#define mmSDMA2_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA2_ACTIVE_FCN_ID 0x0007 +#define mmSDMA2_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA2_VM_CTX_CNTL 0x0008 +#define mmSDMA2_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA2_VIRT_RESET_REQ 0x0009 +#define mmSDMA2_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA2_VF_ENABLE 0x000a +#define mmSDMA2_VF_ENABLE_BASE_IDX 1 +#define mmSDMA2_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA2_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA2_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA2_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA2_PUB_REG_TYPE0 0x000f +#define mmSDMA2_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA2_PUB_REG_TYPE1 0x0010 +#define mmSDMA2_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA2_PUB_REG_TYPE2 0x0011 +#define mmSDMA2_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA2_PUB_REG_TYPE3 0x0012 +#define mmSDMA2_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA2_MMHUB_CNTL 0x0013 +#define mmSDMA2_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA2_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA2_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA2_POWER_CNTL 0x001a +#define mmSDMA2_POWER_CNTL_BASE_IDX 1 +#define mmSDMA2_CLK_CTRL 0x001b +#define mmSDMA2_CLK_CTRL_BASE_IDX 1 +#define mmSDMA2_CNTL 0x001c +#define mmSDMA2_CNTL_BASE_IDX 1 +#define mmSDMA2_CHICKEN_BITS 0x001d +#define mmSDMA2_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA2_GB_ADDR_CONFIG 0x001e +#define mmSDMA2_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA2_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA2_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA2_RB_RPTR_FETCH 0x0022 +#define mmSDMA2_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA2_IB_OFFSET_FETCH 0x0023 +#define mmSDMA2_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA2_PROGRAM 0x0024 +#define mmSDMA2_PROGRAM_BASE_IDX 1 +#define mmSDMA2_STATUS_REG 0x0025 +#define mmSDMA2_STATUS_REG_BASE_IDX 1 +#define mmSDMA2_STATUS1_REG 0x0026 +#define mmSDMA2_STATUS1_REG_BASE_IDX 1 +#define mmSDMA2_RD_BURST_CNTL 0x0027 +#define mmSDMA2_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA2_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA2_UCODE_CHECKSUM 0x0029 +#define mmSDMA2_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA2_F32_CNTL 0x002a +#define mmSDMA2_F32_CNTL_BASE_IDX 1 +#define mmSDMA2_FREEZE 0x002b +#define mmSDMA2_FREEZE_BASE_IDX 1 +#define mmSDMA2_PHASE0_QUANTUM 0x002c +#define mmSDMA2_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA2_PHASE1_QUANTUM 0x002d +#define mmSDMA2_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA2_EDC_CONFIG 0x0032 +#define mmSDMA2_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA2_BA_THRESHOLD 0x0033 +#define mmSDMA2_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA2_ID 0x0034 +#define mmSDMA2_ID_BASE_IDX 1 +#define mmSDMA2_VERSION 0x0035 +#define mmSDMA2_VERSION_BASE_IDX 1 +#define mmSDMA2_EDC_COUNTER 0x0036 +#define mmSDMA2_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA2_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA2_STATUS2_REG 0x0038 +#define mmSDMA2_STATUS2_REG_BASE_IDX 1 +#define mmSDMA2_ATOMIC_CNTL 0x0039 +#define mmSDMA2_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA2_ATOMIC_PREOP_LO 0x003a +#define mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA2_ATOMIC_PREOP_HI 0x003b +#define mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA2_UTCL1_CNTL 0x003c +#define mmSDMA2_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA2_UTCL1_WATERMK 0x003d +#define mmSDMA2_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA2_UTCL1_RD_STATUS 0x003e +#define mmSDMA2_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA2_UTCL1_WR_STATUS 0x003f +#define mmSDMA2_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA2_UTCL1_INV0 0x0040 +#define mmSDMA2_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA2_UTCL1_INV1 0x0041 +#define mmSDMA2_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA2_UTCL1_INV2 0x0042 +#define mmSDMA2_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA2_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA2_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA2_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA2_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA2_UTCL1_TIMEOUT 0x0047 +#define mmSDMA2_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA2_UTCL1_PAGE 0x0048 +#define mmSDMA2_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA2_POWER_CNTL_IDLE 0x0049 +#define mmSDMA2_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA2_RELAX_ORDERING_LUT 0x004a +#define mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA2_CHICKEN_BITS_2 0x004b +#define mmSDMA2_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA2_STATUS3_REG 0x004c +#define mmSDMA2_STATUS3_REG_BASE_IDX 1 +#define mmSDMA2_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_PHASE2_QUANTUM 0x004f +#define mmSDMA2_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA2_ERROR_LOG 0x0050 +#define mmSDMA2_ERROR_LOG_BASE_IDX 1 +#define mmSDMA2_PUB_DUMMY_REG0 0x0051 +#define mmSDMA2_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA2_PUB_DUMMY_REG1 0x0052 +#define mmSDMA2_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA2_PUB_DUMMY_REG2 0x0053 +#define mmSDMA2_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA2_PUB_DUMMY_REG3 0x0054 +#define mmSDMA2_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA2_F32_COUNTER 0x0055 +#define mmSDMA2_F32_COUNTER_BASE_IDX 1 +#define mmSDMA2_UNBREAKABLE 0x0056 +#define mmSDMA2_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA2_PERFMON_CNTL 0x0057 +#define mmSDMA2_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA2_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA2_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA2_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA2_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA2_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA2_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA2_CRD_CNTL 0x005b +#define mmSDMA2_CRD_CNTL_BASE_IDX 1 +#define mmSDMA2_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA2_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA2_ULV_CNTL 0x005e +#define mmSDMA2_ULV_CNTL_BASE_IDX 1 +#define mmSDMA2_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA2_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA2_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA2_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA2_GFX_RB_CNTL 0x0080 +#define mmSDMA2_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_RB_BASE 0x0081 +#define mmSDMA2_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA2_GFX_RB_BASE_HI 0x0082 +#define mmSDMA2_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_RPTR 0x0083 +#define mmSDMA2_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR 0x0085 +#define mmSDMA2_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_GFX_IB_CNTL 0x008a +#define mmSDMA2_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_IB_RPTR 0x008b +#define mmSDMA2_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_GFX_IB_OFFSET 0x008c +#define mmSDMA2_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_GFX_IB_BASE_LO 0x008d +#define mmSDMA2_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_GFX_IB_BASE_HI 0x008e +#define mmSDMA2_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_GFX_IB_SIZE 0x008f +#define mmSDMA2_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_GFX_SKIP_CNTL 0x0090 +#define mmSDMA2_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_GFX_DOORBELL 0x0092 +#define mmSDMA2_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA2_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_STATUS 0x00a8 +#define mmSDMA2_GFX_STATUS_BASE_IDX 1 +#define mmSDMA2_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_GFX_WATERMARK 0x00aa +#define mmSDMA2_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA2_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_GFX_PREEMPT 0x00b0 +#define mmSDMA2_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA2_GFX_DUMMY_REG 0x00b1 +#define mmSDMA2_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_CNTL 0x00d8 +#define mmSDMA2_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_BASE 0x00d9 +#define mmSDMA2_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_BASE_HI 0x00da +#define mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_RPTR 0x00db +#define mmSDMA2_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR 0x00dd +#define mmSDMA2_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_CNTL 0x00e2 +#define mmSDMA2_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_RPTR 0x00e3 +#define mmSDMA2_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA2_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_SIZE 0x00e7 +#define mmSDMA2_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_PAGE_DOORBELL 0x00ea +#define mmSDMA2_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA2_PAGE_STATUS 0x0100 +#define mmSDMA2_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA2_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_PAGE_WATERMARK 0x0102 +#define mmSDMA2_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA2_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_PAGE_PREEMPT 0x0108 +#define mmSDMA2_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA2_PAGE_DUMMY_REG 0x0109 +#define mmSDMA2_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_CNTL 0x0130 +#define mmSDMA2_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_BASE 0x0131 +#define mmSDMA2_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_RPTR 0x0133 +#define mmSDMA2_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR 0x0135 +#define mmSDMA2_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_CNTL 0x013a +#define mmSDMA2_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_RPTR 0x013b +#define mmSDMA2_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_OFFSET 0x013c +#define mmSDMA2_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_BASE_LO 0x013d +#define mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_BASE_HI 0x013e +#define mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_SIZE 0x013f +#define mmSDMA2_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC0_DOORBELL 0x0142 +#define mmSDMA2_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC0_STATUS 0x0158 +#define mmSDMA2_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC0_WATERMARK 0x015a +#define mmSDMA2_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC0_PREEMPT 0x0160 +#define mmSDMA2_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC0_DUMMY_REG 0x0161 +#define mmSDMA2_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_CNTL 0x0188 +#define mmSDMA2_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_BASE 0x0189 +#define mmSDMA2_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_BASE_HI 0x018a +#define mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_RPTR 0x018b +#define mmSDMA2_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR 0x018d +#define mmSDMA2_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_CNTL 0x0192 +#define mmSDMA2_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_RPTR 0x0193 +#define mmSDMA2_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_OFFSET 0x0194 +#define mmSDMA2_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_SIZE 0x0197 +#define mmSDMA2_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC1_DOORBELL 0x019a +#define mmSDMA2_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC1_STATUS 0x01b0 +#define mmSDMA2_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC1_WATERMARK 0x01b2 +#define mmSDMA2_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC1_PREEMPT 0x01b8 +#define mmSDMA2_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA2_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_CNTL 0x01e0 +#define mmSDMA2_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_BASE 0x01e1 +#define mmSDMA2_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_RPTR 0x01e3 +#define mmSDMA2_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR 0x01e5 +#define mmSDMA2_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_CNTL 0x01ea +#define mmSDMA2_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_RPTR 0x01eb +#define mmSDMA2_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_OFFSET 0x01ec +#define mmSDMA2_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_SIZE 0x01ef +#define mmSDMA2_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC2_DOORBELL 0x01f2 +#define mmSDMA2_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC2_STATUS 0x0208 +#define mmSDMA2_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC2_WATERMARK 0x020a +#define mmSDMA2_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC2_PREEMPT 0x0210 +#define mmSDMA2_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC2_DUMMY_REG 0x0211 +#define mmSDMA2_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_CNTL 0x0238 +#define mmSDMA2_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_BASE 0x0239 +#define mmSDMA2_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_BASE_HI 0x023a +#define mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_RPTR 0x023b +#define mmSDMA2_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR 0x023d +#define mmSDMA2_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_CNTL 0x0242 +#define mmSDMA2_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_RPTR 0x0243 +#define mmSDMA2_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_OFFSET 0x0244 +#define mmSDMA2_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_SIZE 0x0247 +#define mmSDMA2_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC3_DOORBELL 0x024a +#define mmSDMA2_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC3_STATUS 0x0260 +#define mmSDMA2_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC3_WATERMARK 0x0262 +#define mmSDMA2_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC3_PREEMPT 0x0268 +#define mmSDMA2_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC3_DUMMY_REG 0x0269 +#define mmSDMA2_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_CNTL 0x0290 +#define mmSDMA2_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_BASE 0x0291 +#define mmSDMA2_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_RPTR 0x0293 +#define mmSDMA2_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR 0x0295 +#define mmSDMA2_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_CNTL 0x029a +#define mmSDMA2_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_RPTR 0x029b +#define mmSDMA2_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_OFFSET 0x029c +#define mmSDMA2_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_BASE_LO 0x029d +#define mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_BASE_HI 0x029e +#define mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_SIZE 0x029f +#define mmSDMA2_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC4_DOORBELL 0x02a2 +#define mmSDMA2_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC4_STATUS 0x02b8 +#define mmSDMA2_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC4_WATERMARK 0x02ba +#define mmSDMA2_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC4_PREEMPT 0x02c0 +#define mmSDMA2_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA2_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_CNTL 0x02e8 +#define mmSDMA2_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_BASE 0x02e9 +#define mmSDMA2_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_RPTR 0x02eb +#define mmSDMA2_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR 0x02ed +#define mmSDMA2_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_CNTL 0x02f2 +#define mmSDMA2_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_RPTR 0x02f3 +#define mmSDMA2_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA2_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_SIZE 0x02f7 +#define mmSDMA2_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC5_DOORBELL 0x02fa +#define mmSDMA2_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC5_STATUS 0x0310 +#define mmSDMA2_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC5_WATERMARK 0x0312 +#define mmSDMA2_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC5_PREEMPT 0x0318 +#define mmSDMA2_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC5_DUMMY_REG 0x0319 +#define mmSDMA2_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_CNTL 0x0340 +#define mmSDMA2_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_BASE 0x0341 +#define mmSDMA2_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_RPTR 0x0343 +#define mmSDMA2_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR 0x0345 +#define mmSDMA2_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_CNTL 0x034a +#define mmSDMA2_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_RPTR 0x034b +#define mmSDMA2_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_OFFSET 0x034c +#define mmSDMA2_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_BASE_LO 0x034d +#define mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_BASE_HI 0x034e +#define mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_SIZE 0x034f +#define mmSDMA2_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC6_DOORBELL 0x0352 +#define mmSDMA2_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC6_STATUS 0x0368 +#define mmSDMA2_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC6_WATERMARK 0x036a +#define mmSDMA2_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC6_PREEMPT 0x0370 +#define mmSDMA2_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC6_DUMMY_REG 0x0371 +#define mmSDMA2_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_CNTL 0x0398 +#define mmSDMA2_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_BASE 0x0399 +#define mmSDMA2_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_BASE_HI 0x039a +#define mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_RPTR 0x039b +#define mmSDMA2_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR 0x039d +#define mmSDMA2_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_CNTL 0x03a2 +#define mmSDMA2_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_RPTR 0x03a3 +#define mmSDMA2_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA2_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_SIZE 0x03a7 +#define mmSDMA2_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA2_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC7_DOORBELL 0x03aa +#define mmSDMA2_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA2_RLC7_STATUS 0x03c0 +#define mmSDMA2_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA2_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA2_RLC7_WATERMARK 0x03c2 +#define mmSDMA2_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA2_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA2_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA2_RLC7_PREEMPT 0x03c8 +#define mmSDMA2_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA2_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA2_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA2_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA2_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA2_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h new file mode 100644 index 000000000000..be10d5d3347e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma2_4_2_2_SH_MASK_HEADER +#define _sdma2_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma2_sdma2dec +//SDMA2_UCODE_ADDR +#define SDMA2_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA2_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA2_UCODE_DATA +#define SDMA2_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA2_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA2_VM_CNTL +#define SDMA2_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA2_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA2_VM_CTX_LO +#define SDMA2_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA2_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_VM_CTX_HI +#define SDMA2_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA2_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_ACTIVE_FCN_ID +#define SDMA2_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA2_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA2_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA2_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA2_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA2_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA2_VM_CTX_CNTL +#define SDMA2_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA2_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA2_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA2_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA2_VIRT_RESET_REQ +#define SDMA2_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA2_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA2_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA2_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA2_VF_ENABLE +#define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA2_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA2_CONTEXT_REG_TYPE0 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE__SHIFT 0x1 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL__SHIFT 0xa +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR__SHIFT 0xb +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE__SHIFT 0xf +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL__SHIFT 0x12 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_MASK 0x00000002L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL_MASK 0x00040000L +#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA2_CONTEXT_REG_TYPE1 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS__SHIFT 0x8 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK__SHIFT 0xa +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT__SHIFT 0x10 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA2_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS_MASK 0x00000100L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK_MASK 0x00000400L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT_MASK 0x00010000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA2_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA2_CONTEXT_REG_TYPE2 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA2_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA2_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA2_CONTEXT_REG_TYPE3 +#define SDMA2_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA2_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA2_PUB_REG_TYPE0 +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL__SHIFT 0x4 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO__SHIFT 0x5 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI__SHIFT 0x6 +#define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA2_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA2_PUB_REG_TYPE0__SDMA2_MMHUB_CNTL__SHIFT 0x13 +#define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL__SHIFT 0x1a +#define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL__SHIFT 0x1b +#define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL__SHIFT 0x1c +#define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS__SHIFT 0x1d +#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK 0x00000002L +#define SDMA2_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL_MASK 0x00000010L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO_MASK 0x00000020L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI_MASK 0x00000040L +#define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA2_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_MMHUB_CNTL_MASK 0x00080000L +#define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL_MASK 0x04000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL_MASK 0x08000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL_MASK 0x10000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS_MASK 0x20000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA2_PUB_REG_TYPE1 +#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM__SHIFT 0x4 +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG__SHIFT 0x5 +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG__SHIFT 0x6 +#define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL__SHIFT 0xa +#define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE__SHIFT 0xb +#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA2_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG__SHIFT 0x12 +#define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD__SHIFT 0x13 +#define SDMA2_PUB_REG_TYPE1__SDMA2_ID__SHIFT 0x14 +#define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION__SHIFT 0x15 +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER__SHIFT 0x16 +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG__SHIFT 0x18 +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL__SHIFT 0x1c +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM_MASK 0x00000010L +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG_MASK 0x00000020L +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG_MASK 0x00000040L +#define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL_MASK 0x00000400L +#define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE_MASK 0x00000800L +#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA2_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG_MASK 0x00040000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD_MASK 0x00080000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_ID_MASK 0x00100000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION_MASK 0x00200000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_MASK 0x00400000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG_MASK 0x01000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL_MASK 0x10000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA2_PUB_REG_TYPE2 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2__SHIFT 0x2 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE__SHIFT 0x8 +#define SDMA2_PUB_REG_TYPE2__SDMA2_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG__SHIFT 0xc +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG__SHIFT 0x10 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER__SHIFT 0x15 +#define SDMA2_PUB_REG_TYPE2__SDMA2_UNBREAKABLE__SHIFT 0x16 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFMON_CNTL__SHIFT 0x17 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL__SHIFT 0x1b +#define SDMA2_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA2_PUB_REG_TYPE2__SDMA2_ULV_CNTL__SHIFT 0x1e +#define SDMA2_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1_MASK 0x00000002L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2_MASK 0x00000004L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE_MASK 0x00000100L +#define SDMA2_PUB_REG_TYPE2__SDMA2_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG_MASK 0x00001000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG_MASK 0x00010000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER_MASK 0x00200000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_UNBREAKABLE_MASK 0x00400000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFMON_CNTL_MASK 0x00800000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL_MASK 0x08000000L +#define SDMA2_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA2_PUB_REG_TYPE2__SDMA2_ULV_CNTL_MASK 0x40000000L +#define SDMA2_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA2_PUB_REG_TYPE3 +#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA2_PUB_REG_TYPE3__SDMA2_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA2_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA2_PUB_REG_TYPE3__SDMA2_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA2_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA2_MMHUB_CNTL +#define SDMA2_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA2_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA2_CONTEXT_GROUP_BOUNDARY +#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA2_POWER_CNTL +#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA2_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA2_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA2_CLK_CTRL +#define SDMA2_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA2_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA2_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA2_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA2_CNTL +#define SDMA2_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA2_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA2_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA2_CHICKEN_BITS +#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA2_GB_ADDR_CONFIG +#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA2_GB_ADDR_CONFIG_READ +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA2_RB_RPTR_FETCH_HI +#define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA2_RB_RPTR_FETCH +#define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA2_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA2_IB_OFFSET_FETCH +#define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA2_PROGRAM +#define SDMA2_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA2_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA2_STATUS_REG +#define SDMA2_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA2_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA2_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA2_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA2_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA2_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA2_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA2_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA2_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA2_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA2_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA2_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA2_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA2_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA2_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA2_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA2_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA2_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA2_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA2_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA2_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA2_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA2_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA2_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA2_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA2_STATUS1_REG +#define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA2_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA2_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA2_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA2_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA2_RD_BURST_CNTL +#define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA2_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA2_HBM_PAGE_CONFIG +#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA2_UCODE_CHECKSUM +#define SDMA2_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA2_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA2_F32_CNTL +#define SDMA2_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA2_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA2_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA2_F32_CNTL__STEP_MASK 0x00000002L +//SDMA2_FREEZE +#define SDMA2_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA2_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA2_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA2_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA2_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA2_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA2_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA2_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA2_PHASE0_QUANTUM +#define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA2_PHASE1_QUANTUM +#define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA2_EDC_CONFIG +#define SDMA2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA2_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA2_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA2_BA_THRESHOLD +#define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA2_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA2_ID +#define SDMA2_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA2_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA2_VERSION +#define SDMA2_VERSION__MINVER__SHIFT 0x0 +#define SDMA2_VERSION__MAJVER__SHIFT 0x8 +#define SDMA2_VERSION__REV__SHIFT 0x10 +#define SDMA2_VERSION__MINVER_MASK 0x0000007FL +#define SDMA2_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA2_VERSION__REV_MASK 0x003F0000L +//SDMA2_EDC_COUNTER +#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA2_EDC_COUNTER_CLEAR +#define SDMA2_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA2_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA2_STATUS2_REG +#define SDMA2_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA2_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA2_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA2_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA2_ATOMIC_CNTL +#define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA2_ATOMIC_PREOP_LO +#define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA2_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA2_ATOMIC_PREOP_HI +#define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA2_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_CNTL +#define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA2_UTCL1_WATERMK +#define SDMA2_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA2_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA2_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA2_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA2_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA2_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA2_UTCL1_RD_STATUS +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA2_UTCL1_WR_STATUS +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA2_UTCL1_INV0 +#define SDMA2_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA2_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA2_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA2_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA2_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA2_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA2_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA2_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA2_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA2_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA2_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA2_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA2_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA2_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA2_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA2_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA2_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA2_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA2_UTCL1_INV1 +#define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_INV2 +#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_RD_XNACK0 +#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_RD_XNACK1 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA2_UTCL1_WR_XNACK0 +#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA2_UTCL1_WR_XNACK1 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA2_UTCL1_TIMEOUT +#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA2_UTCL1_PAGE +#define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA2_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA2_POWER_CNTL_IDLE +#define SDMA2_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA2_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA2_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA2_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA2_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA2_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA2_RELAX_ORDERING_LUT +#define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA2_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA2_CHICKEN_BITS_2 +#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA2_STATUS3_REG +#define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA2_PHYSICAL_ADDR_LO +#define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA2_PHYSICAL_ADDR_HI +#define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA2_PHASE2_QUANTUM +#define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA2_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA2_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA2_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA2_ERROR_LOG +#define SDMA2_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA2_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA2_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA2_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA2_PUB_DUMMY_REG0 +#define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG1 +#define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG2 +#define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA2_PUB_DUMMY_REG3 +#define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA2_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA2_F32_COUNTER +#define SDMA2_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA2_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA2_UNBREAKABLE +#define SDMA2_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA2_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA2_PERFMON_CNTL +#define SDMA2_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA2_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA2_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA2_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA2_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA2_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA2_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA2_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA2_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA2_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA2_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA2_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA2_PERFCOUNTER0_RESULT +#define SDMA2_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA2_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA2_PERFCOUNTER1_RESULT +#define SDMA2_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA2_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA2_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA2_CRD_CNTL +#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA2_GPU_IOV_VIOLATION_LOG +#define SDMA2_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA2_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA2_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA2_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA2_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA2_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA2_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA2_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA2_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA2_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA2_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA2_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA2_ULV_CNTL +#define SDMA2_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA2_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA2_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA2_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA2_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA2_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA2_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA2_EA_DBIT_ADDR_DATA +#define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA2_EA_DBIT_ADDR_INDEX +#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA2_GPU_IOV_VIOLATION_LOG2 +#define SDMA2_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA2_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA2_GFX_RB_CNTL +#define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_GFX_RB_BASE +#define SDMA2_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_BASE_HI +#define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_GFX_RB_RPTR +#define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_RPTR_HI +#define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR +#define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_HI +#define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_CNTL +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_GFX_RB_RPTR_ADDR_HI +#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_RPTR_ADDR_LO +#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_IB_CNTL +#define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_GFX_IB_RPTR +#define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_GFX_IB_OFFSET +#define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_GFX_IB_BASE_LO +#define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_GFX_IB_BASE_HI +#define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_IB_SIZE +#define SDMA2_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_GFX_SKIP_CNTL +#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_GFX_CONTEXT_STATUS +#define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_GFX_DOORBELL +#define SDMA2_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_GFX_CONTEXT_CNTL +#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA2_GFX_STATUS +#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_GFX_DOORBELL_LOG +#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_GFX_WATERMARK +#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_GFX_DOORBELL_OFFSET +#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_GFX_CSA_ADDR_LO +#define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_CSA_ADDR_HI +#define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_IB_SUB_REMAIN +#define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_GFX_PREEMPT +#define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_GFX_DUMMY_REG +#define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_GFX_RB_AQL_CNTL +#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_GFX_MINOR_PTR_UPDATE +#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_GFX_MIDCMD_DATA0 +#define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA1 +#define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA2 +#define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA3 +#define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA4 +#define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA5 +#define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA6 +#define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA7 +#define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_DATA8 +#define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_GFX_MIDCMD_CNTL +#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_PAGE_RB_CNTL +#define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_PAGE_RB_BASE +#define SDMA2_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_BASE_HI +#define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_PAGE_RB_RPTR +#define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_RPTR_HI +#define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR +#define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_HI +#define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_CNTL +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_PAGE_RB_RPTR_ADDR_HI +#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_RPTR_ADDR_LO +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_IB_CNTL +#define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_PAGE_IB_RPTR +#define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_PAGE_IB_OFFSET +#define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_PAGE_IB_BASE_LO +#define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_PAGE_IB_BASE_HI +#define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_IB_SIZE +#define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_PAGE_SKIP_CNTL +#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_PAGE_CONTEXT_STATUS +#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_PAGE_DOORBELL +#define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_PAGE_STATUS +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_PAGE_DOORBELL_LOG +#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_PAGE_WATERMARK +#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_PAGE_DOORBELL_OFFSET +#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_PAGE_CSA_ADDR_LO +#define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_CSA_ADDR_HI +#define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_IB_SUB_REMAIN +#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_PAGE_PREEMPT +#define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_PAGE_DUMMY_REG +#define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_PAGE_RB_AQL_CNTL +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_PAGE_MINOR_PTR_UPDATE +#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_PAGE_MIDCMD_DATA0 +#define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA1 +#define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA2 +#define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA3 +#define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA4 +#define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA5 +#define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA6 +#define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA7 +#define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_DATA8 +#define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_PAGE_MIDCMD_CNTL +#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC0_RB_CNTL +#define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC0_RB_BASE +#define SDMA2_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_BASE_HI +#define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC0_RB_RPTR +#define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_RPTR_HI +#define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR +#define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_HI +#define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_CNTL +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC0_RB_RPTR_ADDR_HI +#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_RPTR_ADDR_LO +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_IB_CNTL +#define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC0_IB_RPTR +#define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC0_IB_OFFSET +#define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC0_IB_BASE_LO +#define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC0_IB_BASE_HI +#define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_IB_SIZE +#define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC0_SKIP_CNTL +#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC0_CONTEXT_STATUS +#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC0_DOORBELL +#define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC0_STATUS +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC0_DOORBELL_LOG +#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC0_WATERMARK +#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC0_DOORBELL_OFFSET +#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC0_CSA_ADDR_LO +#define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_CSA_ADDR_HI +#define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_IB_SUB_REMAIN +#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC0_PREEMPT +#define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC0_DUMMY_REG +#define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC0_RB_AQL_CNTL +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC0_MINOR_PTR_UPDATE +#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC0_MIDCMD_DATA0 +#define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA1 +#define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA2 +#define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA3 +#define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA4 +#define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA5 +#define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA6 +#define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA7 +#define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_DATA8 +#define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC0_MIDCMD_CNTL +#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC1_RB_CNTL +#define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC1_RB_BASE +#define SDMA2_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_BASE_HI +#define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC1_RB_RPTR +#define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_RPTR_HI +#define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR +#define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_HI +#define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_CNTL +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC1_RB_RPTR_ADDR_HI +#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_RPTR_ADDR_LO +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_IB_CNTL +#define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC1_IB_RPTR +#define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC1_IB_OFFSET +#define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC1_IB_BASE_LO +#define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC1_IB_BASE_HI +#define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_IB_SIZE +#define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC1_SKIP_CNTL +#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC1_CONTEXT_STATUS +#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC1_DOORBELL +#define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC1_STATUS +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC1_DOORBELL_LOG +#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC1_WATERMARK +#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC1_DOORBELL_OFFSET +#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC1_CSA_ADDR_LO +#define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_CSA_ADDR_HI +#define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_IB_SUB_REMAIN +#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC1_PREEMPT +#define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC1_DUMMY_REG +#define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC1_RB_AQL_CNTL +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC1_MINOR_PTR_UPDATE +#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC1_MIDCMD_DATA0 +#define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA1 +#define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA2 +#define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA3 +#define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA4 +#define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA5 +#define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA6 +#define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA7 +#define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_DATA8 +#define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC1_MIDCMD_CNTL +#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC2_RB_CNTL +#define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC2_RB_BASE +#define SDMA2_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_BASE_HI +#define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC2_RB_RPTR +#define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_RPTR_HI +#define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR +#define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_HI +#define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_CNTL +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC2_RB_RPTR_ADDR_HI +#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_RPTR_ADDR_LO +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_IB_CNTL +#define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC2_IB_RPTR +#define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC2_IB_OFFSET +#define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC2_IB_BASE_LO +#define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC2_IB_BASE_HI +#define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_IB_SIZE +#define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC2_SKIP_CNTL +#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC2_CONTEXT_STATUS +#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC2_DOORBELL +#define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC2_STATUS +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC2_DOORBELL_LOG +#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC2_WATERMARK +#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC2_DOORBELL_OFFSET +#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC2_CSA_ADDR_LO +#define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_CSA_ADDR_HI +#define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_IB_SUB_REMAIN +#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC2_PREEMPT +#define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC2_DUMMY_REG +#define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC2_RB_AQL_CNTL +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC2_MINOR_PTR_UPDATE +#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC2_MIDCMD_DATA0 +#define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA1 +#define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA2 +#define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA3 +#define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA4 +#define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA5 +#define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA6 +#define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA7 +#define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_DATA8 +#define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC2_MIDCMD_CNTL +#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC3_RB_CNTL +#define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC3_RB_BASE +#define SDMA2_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_BASE_HI +#define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC3_RB_RPTR +#define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_RPTR_HI +#define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR +#define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_HI +#define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_CNTL +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC3_RB_RPTR_ADDR_HI +#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_RPTR_ADDR_LO +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_IB_CNTL +#define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC3_IB_RPTR +#define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC3_IB_OFFSET +#define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC3_IB_BASE_LO +#define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC3_IB_BASE_HI +#define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_IB_SIZE +#define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC3_SKIP_CNTL +#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC3_CONTEXT_STATUS +#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC3_DOORBELL +#define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC3_STATUS +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC3_DOORBELL_LOG +#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC3_WATERMARK +#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC3_DOORBELL_OFFSET +#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC3_CSA_ADDR_LO +#define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_CSA_ADDR_HI +#define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_IB_SUB_REMAIN +#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC3_PREEMPT +#define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC3_DUMMY_REG +#define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC3_RB_AQL_CNTL +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC3_MINOR_PTR_UPDATE +#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC3_MIDCMD_DATA0 +#define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA1 +#define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA2 +#define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA3 +#define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA4 +#define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA5 +#define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA6 +#define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA7 +#define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_DATA8 +#define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC3_MIDCMD_CNTL +#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC4_RB_CNTL +#define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC4_RB_BASE +#define SDMA2_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_BASE_HI +#define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC4_RB_RPTR +#define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_RPTR_HI +#define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR +#define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_HI +#define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_CNTL +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC4_RB_RPTR_ADDR_HI +#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_RPTR_ADDR_LO +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_IB_CNTL +#define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC4_IB_RPTR +#define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC4_IB_OFFSET +#define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC4_IB_BASE_LO +#define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC4_IB_BASE_HI +#define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_IB_SIZE +#define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC4_SKIP_CNTL +#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC4_CONTEXT_STATUS +#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC4_DOORBELL +#define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC4_STATUS +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC4_DOORBELL_LOG +#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC4_WATERMARK +#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC4_DOORBELL_OFFSET +#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC4_CSA_ADDR_LO +#define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_CSA_ADDR_HI +#define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_IB_SUB_REMAIN +#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC4_PREEMPT +#define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC4_DUMMY_REG +#define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC4_RB_AQL_CNTL +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC4_MINOR_PTR_UPDATE +#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC4_MIDCMD_DATA0 +#define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA1 +#define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA2 +#define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA3 +#define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA4 +#define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA5 +#define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA6 +#define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA7 +#define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_DATA8 +#define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC4_MIDCMD_CNTL +#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC5_RB_CNTL +#define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC5_RB_BASE +#define SDMA2_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_BASE_HI +#define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC5_RB_RPTR +#define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_RPTR_HI +#define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR +#define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_HI +#define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_CNTL +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC5_RB_RPTR_ADDR_HI +#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_RPTR_ADDR_LO +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_IB_CNTL +#define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC5_IB_RPTR +#define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC5_IB_OFFSET +#define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC5_IB_BASE_LO +#define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC5_IB_BASE_HI +#define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_IB_SIZE +#define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC5_SKIP_CNTL +#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC5_CONTEXT_STATUS +#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC5_DOORBELL +#define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC5_STATUS +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC5_DOORBELL_LOG +#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC5_WATERMARK +#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC5_DOORBELL_OFFSET +#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC5_CSA_ADDR_LO +#define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_CSA_ADDR_HI +#define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_IB_SUB_REMAIN +#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC5_PREEMPT +#define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC5_DUMMY_REG +#define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC5_RB_AQL_CNTL +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC5_MINOR_PTR_UPDATE +#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC5_MIDCMD_DATA0 +#define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA1 +#define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA2 +#define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA3 +#define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA4 +#define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA5 +#define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA6 +#define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA7 +#define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_DATA8 +#define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC5_MIDCMD_CNTL +#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC6_RB_CNTL +#define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC6_RB_BASE +#define SDMA2_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_BASE_HI +#define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC6_RB_RPTR +#define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_RPTR_HI +#define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR +#define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_HI +#define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_CNTL +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC6_RB_RPTR_ADDR_HI +#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_RPTR_ADDR_LO +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_IB_CNTL +#define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC6_IB_RPTR +#define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC6_IB_OFFSET +#define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC6_IB_BASE_LO +#define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC6_IB_BASE_HI +#define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_IB_SIZE +#define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC6_SKIP_CNTL +#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC6_CONTEXT_STATUS +#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC6_DOORBELL +#define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC6_STATUS +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC6_DOORBELL_LOG +#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC6_WATERMARK +#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC6_DOORBELL_OFFSET +#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC6_CSA_ADDR_LO +#define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_CSA_ADDR_HI +#define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_IB_SUB_REMAIN +#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC6_PREEMPT +#define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC6_DUMMY_REG +#define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC6_RB_AQL_CNTL +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC6_MINOR_PTR_UPDATE +#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC6_MIDCMD_DATA0 +#define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA1 +#define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA2 +#define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA3 +#define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA4 +#define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA5 +#define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA6 +#define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA7 +#define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_DATA8 +#define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC6_MIDCMD_CNTL +#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA2_RLC7_RB_CNTL +#define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA2_RLC7_RB_BASE +#define SDMA2_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_BASE_HI +#define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA2_RLC7_RB_RPTR +#define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_RPTR_HI +#define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR +#define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_HI +#define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_CNTL +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA2_RLC7_RB_RPTR_ADDR_HI +#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_RPTR_ADDR_LO +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_IB_CNTL +#define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA2_RLC7_IB_RPTR +#define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC7_IB_OFFSET +#define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA2_RLC7_IB_BASE_LO +#define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA2_RLC7_IB_BASE_HI +#define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_IB_SIZE +#define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA2_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC7_SKIP_CNTL +#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA2_RLC7_CONTEXT_STATUS +#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA2_RLC7_DOORBELL +#define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA2_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA2_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA2_RLC7_STATUS +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA2_RLC7_DOORBELL_LOG +#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA2_RLC7_WATERMARK +#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA2_RLC7_DOORBELL_OFFSET +#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA2_RLC7_CSA_ADDR_LO +#define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_CSA_ADDR_HI +#define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_IB_SUB_REMAIN +#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA2_RLC7_PREEMPT +#define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA2_RLC7_DUMMY_REG +#define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA2_RLC7_RB_AQL_CNTL +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA2_RLC7_MINOR_PTR_UPDATE +#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA2_RLC7_MIDCMD_DATA0 +#define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA1 +#define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA2 +#define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA3 +#define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA4 +#define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA5 +#define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA6 +#define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA7 +#define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_DATA8 +#define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA2_RLC7_MIDCMD_CNTL +#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h new file mode 100644 index 000000000000..09e8302715cb --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma3_4_2_2_OFFSET_HEADER +#define _sdma3_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma3_sdma3dec +// base address: 0x79000 +#define mmSDMA3_UCODE_ADDR 0x0000 +#define mmSDMA3_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA3_UCODE_DATA 0x0001 +#define mmSDMA3_UCODE_DATA_BASE_IDX 1 +#define mmSDMA3_VM_CNTL 0x0004 +#define mmSDMA3_VM_CNTL_BASE_IDX 1 +#define mmSDMA3_VM_CTX_LO 0x0005 +#define mmSDMA3_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA3_VM_CTX_HI 0x0006 +#define mmSDMA3_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA3_ACTIVE_FCN_ID 0x0007 +#define mmSDMA3_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA3_VM_CTX_CNTL 0x0008 +#define mmSDMA3_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA3_VIRT_RESET_REQ 0x0009 +#define mmSDMA3_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA3_VF_ENABLE 0x000a +#define mmSDMA3_VF_ENABLE_BASE_IDX 1 +#define mmSDMA3_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA3_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA3_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA3_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA3_PUB_REG_TYPE0 0x000f +#define mmSDMA3_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA3_PUB_REG_TYPE1 0x0010 +#define mmSDMA3_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA3_PUB_REG_TYPE2 0x0011 +#define mmSDMA3_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA3_PUB_REG_TYPE3 0x0012 +#define mmSDMA3_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA3_MMHUB_CNTL 0x0013 +#define mmSDMA3_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA3_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA3_POWER_CNTL 0x001a +#define mmSDMA3_POWER_CNTL_BASE_IDX 1 +#define mmSDMA3_CLK_CTRL 0x001b +#define mmSDMA3_CLK_CTRL_BASE_IDX 1 +#define mmSDMA3_CNTL 0x001c +#define mmSDMA3_CNTL_BASE_IDX 1 +#define mmSDMA3_CHICKEN_BITS 0x001d +#define mmSDMA3_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA3_GB_ADDR_CONFIG 0x001e +#define mmSDMA3_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA3_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA3_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA3_RB_RPTR_FETCH 0x0022 +#define mmSDMA3_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA3_IB_OFFSET_FETCH 0x0023 +#define mmSDMA3_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA3_PROGRAM 0x0024 +#define mmSDMA3_PROGRAM_BASE_IDX 1 +#define mmSDMA3_STATUS_REG 0x0025 +#define mmSDMA3_STATUS_REG_BASE_IDX 1 +#define mmSDMA3_STATUS1_REG 0x0026 +#define mmSDMA3_STATUS1_REG_BASE_IDX 1 +#define mmSDMA3_RD_BURST_CNTL 0x0027 +#define mmSDMA3_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA3_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA3_UCODE_CHECKSUM 0x0029 +#define mmSDMA3_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA3_F32_CNTL 0x002a +#define mmSDMA3_F32_CNTL_BASE_IDX 1 +#define mmSDMA3_FREEZE 0x002b +#define mmSDMA3_FREEZE_BASE_IDX 1 +#define mmSDMA3_PHASE0_QUANTUM 0x002c +#define mmSDMA3_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA3_PHASE1_QUANTUM 0x002d +#define mmSDMA3_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA3_EDC_CONFIG 0x0032 +#define mmSDMA3_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA3_BA_THRESHOLD 0x0033 +#define mmSDMA3_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA3_ID 0x0034 +#define mmSDMA3_ID_BASE_IDX 1 +#define mmSDMA3_VERSION 0x0035 +#define mmSDMA3_VERSION_BASE_IDX 1 +#define mmSDMA3_EDC_COUNTER 0x0036 +#define mmSDMA3_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA3_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA3_STATUS2_REG 0x0038 +#define mmSDMA3_STATUS2_REG_BASE_IDX 1 +#define mmSDMA3_ATOMIC_CNTL 0x0039 +#define mmSDMA3_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA3_ATOMIC_PREOP_LO 0x003a +#define mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA3_ATOMIC_PREOP_HI 0x003b +#define mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA3_UTCL1_CNTL 0x003c +#define mmSDMA3_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA3_UTCL1_WATERMK 0x003d +#define mmSDMA3_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA3_UTCL1_RD_STATUS 0x003e +#define mmSDMA3_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA3_UTCL1_WR_STATUS 0x003f +#define mmSDMA3_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA3_UTCL1_INV0 0x0040 +#define mmSDMA3_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA3_UTCL1_INV1 0x0041 +#define mmSDMA3_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA3_UTCL1_INV2 0x0042 +#define mmSDMA3_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA3_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA3_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA3_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA3_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA3_UTCL1_TIMEOUT 0x0047 +#define mmSDMA3_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA3_UTCL1_PAGE 0x0048 +#define mmSDMA3_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA3_POWER_CNTL_IDLE 0x0049 +#define mmSDMA3_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA3_RELAX_ORDERING_LUT 0x004a +#define mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA3_CHICKEN_BITS_2 0x004b +#define mmSDMA3_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA3_STATUS3_REG 0x004c +#define mmSDMA3_STATUS3_REG_BASE_IDX 1 +#define mmSDMA3_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_PHASE2_QUANTUM 0x004f +#define mmSDMA3_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA3_ERROR_LOG 0x0050 +#define mmSDMA3_ERROR_LOG_BASE_IDX 1 +#define mmSDMA3_PUB_DUMMY_REG0 0x0051 +#define mmSDMA3_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA3_PUB_DUMMY_REG1 0x0052 +#define mmSDMA3_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA3_PUB_DUMMY_REG2 0x0053 +#define mmSDMA3_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA3_PUB_DUMMY_REG3 0x0054 +#define mmSDMA3_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA3_F32_COUNTER 0x0055 +#define mmSDMA3_F32_COUNTER_BASE_IDX 1 +#define mmSDMA3_UNBREAKABLE 0x0056 +#define mmSDMA3_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA3_PERFMON_CNTL 0x0057 +#define mmSDMA3_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA3_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA3_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA3_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA3_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA3_CRD_CNTL 0x005b +#define mmSDMA3_CRD_CNTL_BASE_IDX 1 +#define mmSDMA3_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA3_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA3_ULV_CNTL 0x005e +#define mmSDMA3_ULV_CNTL_BASE_IDX 1 +#define mmSDMA3_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA3_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA3_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA3_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA3_GFX_RB_CNTL 0x0080 +#define mmSDMA3_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_RB_BASE 0x0081 +#define mmSDMA3_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA3_GFX_RB_BASE_HI 0x0082 +#define mmSDMA3_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_RPTR 0x0083 +#define mmSDMA3_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR 0x0085 +#define mmSDMA3_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_GFX_IB_CNTL 0x008a +#define mmSDMA3_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_IB_RPTR 0x008b +#define mmSDMA3_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_GFX_IB_OFFSET 0x008c +#define mmSDMA3_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_GFX_IB_BASE_LO 0x008d +#define mmSDMA3_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_GFX_IB_BASE_HI 0x008e +#define mmSDMA3_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_GFX_IB_SIZE 0x008f +#define mmSDMA3_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_GFX_SKIP_CNTL 0x0090 +#define mmSDMA3_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_GFX_DOORBELL 0x0092 +#define mmSDMA3_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA3_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_STATUS 0x00a8 +#define mmSDMA3_GFX_STATUS_BASE_IDX 1 +#define mmSDMA3_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_GFX_WATERMARK 0x00aa +#define mmSDMA3_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA3_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_GFX_PREEMPT 0x00b0 +#define mmSDMA3_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA3_GFX_DUMMY_REG 0x00b1 +#define mmSDMA3_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_CNTL 0x00d8 +#define mmSDMA3_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_BASE 0x00d9 +#define mmSDMA3_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_BASE_HI 0x00da +#define mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_RPTR 0x00db +#define mmSDMA3_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR 0x00dd +#define mmSDMA3_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_CNTL 0x00e2 +#define mmSDMA3_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_RPTR 0x00e3 +#define mmSDMA3_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA3_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_SIZE 0x00e7 +#define mmSDMA3_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_PAGE_DOORBELL 0x00ea +#define mmSDMA3_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA3_PAGE_STATUS 0x0100 +#define mmSDMA3_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA3_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_PAGE_WATERMARK 0x0102 +#define mmSDMA3_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA3_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_PAGE_PREEMPT 0x0108 +#define mmSDMA3_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA3_PAGE_DUMMY_REG 0x0109 +#define mmSDMA3_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_CNTL 0x0130 +#define mmSDMA3_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_BASE 0x0131 +#define mmSDMA3_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_RPTR 0x0133 +#define mmSDMA3_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR 0x0135 +#define mmSDMA3_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_CNTL 0x013a +#define mmSDMA3_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_RPTR 0x013b +#define mmSDMA3_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_OFFSET 0x013c +#define mmSDMA3_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_BASE_LO 0x013d +#define mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_BASE_HI 0x013e +#define mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_SIZE 0x013f +#define mmSDMA3_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC0_DOORBELL 0x0142 +#define mmSDMA3_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC0_STATUS 0x0158 +#define mmSDMA3_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC0_WATERMARK 0x015a +#define mmSDMA3_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC0_PREEMPT 0x0160 +#define mmSDMA3_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC0_DUMMY_REG 0x0161 +#define mmSDMA3_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_CNTL 0x0188 +#define mmSDMA3_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_BASE 0x0189 +#define mmSDMA3_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_BASE_HI 0x018a +#define mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_RPTR 0x018b +#define mmSDMA3_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR 0x018d +#define mmSDMA3_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_CNTL 0x0192 +#define mmSDMA3_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_RPTR 0x0193 +#define mmSDMA3_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_OFFSET 0x0194 +#define mmSDMA3_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_SIZE 0x0197 +#define mmSDMA3_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC1_DOORBELL 0x019a +#define mmSDMA3_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC1_STATUS 0x01b0 +#define mmSDMA3_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC1_WATERMARK 0x01b2 +#define mmSDMA3_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC1_PREEMPT 0x01b8 +#define mmSDMA3_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA3_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_CNTL 0x01e0 +#define mmSDMA3_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_BASE 0x01e1 +#define mmSDMA3_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_RPTR 0x01e3 +#define mmSDMA3_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR 0x01e5 +#define mmSDMA3_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_CNTL 0x01ea +#define mmSDMA3_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_RPTR 0x01eb +#define mmSDMA3_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_OFFSET 0x01ec +#define mmSDMA3_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_SIZE 0x01ef +#define mmSDMA3_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC2_DOORBELL 0x01f2 +#define mmSDMA3_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC2_STATUS 0x0208 +#define mmSDMA3_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC2_WATERMARK 0x020a +#define mmSDMA3_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC2_PREEMPT 0x0210 +#define mmSDMA3_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC2_DUMMY_REG 0x0211 +#define mmSDMA3_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_CNTL 0x0238 +#define mmSDMA3_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_BASE 0x0239 +#define mmSDMA3_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_BASE_HI 0x023a +#define mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_RPTR 0x023b +#define mmSDMA3_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR 0x023d +#define mmSDMA3_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_CNTL 0x0242 +#define mmSDMA3_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_RPTR 0x0243 +#define mmSDMA3_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_OFFSET 0x0244 +#define mmSDMA3_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_SIZE 0x0247 +#define mmSDMA3_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC3_DOORBELL 0x024a +#define mmSDMA3_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC3_STATUS 0x0260 +#define mmSDMA3_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC3_WATERMARK 0x0262 +#define mmSDMA3_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC3_PREEMPT 0x0268 +#define mmSDMA3_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC3_DUMMY_REG 0x0269 +#define mmSDMA3_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_CNTL 0x0290 +#define mmSDMA3_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_BASE 0x0291 +#define mmSDMA3_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_RPTR 0x0293 +#define mmSDMA3_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR 0x0295 +#define mmSDMA3_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_CNTL 0x029a +#define mmSDMA3_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_RPTR 0x029b +#define mmSDMA3_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_OFFSET 0x029c +#define mmSDMA3_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_BASE_LO 0x029d +#define mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_BASE_HI 0x029e +#define mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_SIZE 0x029f +#define mmSDMA3_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC4_DOORBELL 0x02a2 +#define mmSDMA3_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC4_STATUS 0x02b8 +#define mmSDMA3_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC4_WATERMARK 0x02ba +#define mmSDMA3_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC4_PREEMPT 0x02c0 +#define mmSDMA3_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA3_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_CNTL 0x02e8 +#define mmSDMA3_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_BASE 0x02e9 +#define mmSDMA3_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_RPTR 0x02eb +#define mmSDMA3_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR 0x02ed +#define mmSDMA3_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_CNTL 0x02f2 +#define mmSDMA3_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_RPTR 0x02f3 +#define mmSDMA3_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA3_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_SIZE 0x02f7 +#define mmSDMA3_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC5_DOORBELL 0x02fa +#define mmSDMA3_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC5_STATUS 0x0310 +#define mmSDMA3_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC5_WATERMARK 0x0312 +#define mmSDMA3_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC5_PREEMPT 0x0318 +#define mmSDMA3_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC5_DUMMY_REG 0x0319 +#define mmSDMA3_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_CNTL 0x0340 +#define mmSDMA3_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_BASE 0x0341 +#define mmSDMA3_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_RPTR 0x0343 +#define mmSDMA3_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR 0x0345 +#define mmSDMA3_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_CNTL 0x034a +#define mmSDMA3_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_RPTR 0x034b +#define mmSDMA3_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_OFFSET 0x034c +#define mmSDMA3_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_BASE_LO 0x034d +#define mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_BASE_HI 0x034e +#define mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_SIZE 0x034f +#define mmSDMA3_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC6_DOORBELL 0x0352 +#define mmSDMA3_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC6_STATUS 0x0368 +#define mmSDMA3_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC6_WATERMARK 0x036a +#define mmSDMA3_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC6_PREEMPT 0x0370 +#define mmSDMA3_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC6_DUMMY_REG 0x0371 +#define mmSDMA3_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_CNTL 0x0398 +#define mmSDMA3_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_BASE 0x0399 +#define mmSDMA3_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_BASE_HI 0x039a +#define mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_RPTR 0x039b +#define mmSDMA3_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR 0x039d +#define mmSDMA3_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_CNTL 0x03a2 +#define mmSDMA3_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_RPTR 0x03a3 +#define mmSDMA3_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA3_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_SIZE 0x03a7 +#define mmSDMA3_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA3_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC7_DOORBELL 0x03aa +#define mmSDMA3_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA3_RLC7_STATUS 0x03c0 +#define mmSDMA3_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA3_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA3_RLC7_WATERMARK 0x03c2 +#define mmSDMA3_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA3_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA3_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA3_RLC7_PREEMPT 0x03c8 +#define mmSDMA3_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA3_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA3_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA3_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA3_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA3_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h new file mode 100644 index 000000000000..6f2d5ad00488 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma3_4_2_2_SH_MASK_HEADER +#define _sdma3_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma3_sdma3dec +//SDMA3_UCODE_ADDR +#define SDMA3_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA3_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA3_UCODE_DATA +#define SDMA3_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA3_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA3_VM_CNTL +#define SDMA3_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA3_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA3_VM_CTX_LO +#define SDMA3_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA3_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_VM_CTX_HI +#define SDMA3_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA3_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_ACTIVE_FCN_ID +#define SDMA3_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA3_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA3_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA3_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA3_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA3_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA3_VM_CTX_CNTL +#define SDMA3_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA3_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA3_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA3_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA3_VIRT_RESET_REQ +#define SDMA3_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA3_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA3_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA3_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA3_VF_ENABLE +#define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA3_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA3_CONTEXT_REG_TYPE0 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE__SHIFT 0x1 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL__SHIFT 0xa +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR__SHIFT 0xb +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE__SHIFT 0xf +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL__SHIFT 0x12 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_MASK 0x00000002L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL_MASK 0x00040000L +#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA3_CONTEXT_REG_TYPE1 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS__SHIFT 0x8 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK__SHIFT 0xa +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT__SHIFT 0x10 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA3_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS_MASK 0x00000100L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK_MASK 0x00000400L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT_MASK 0x00010000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA3_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA3_CONTEXT_REG_TYPE2 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA3_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA3_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA3_CONTEXT_REG_TYPE3 +#define SDMA3_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA3_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA3_PUB_REG_TYPE0 +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL__SHIFT 0x4 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO__SHIFT 0x5 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI__SHIFT 0x6 +#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA3_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA3_PUB_REG_TYPE0__SDMA3_MMHUB_CNTL__SHIFT 0x13 +#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL__SHIFT 0x1a +#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL__SHIFT 0x1b +#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL__SHIFT 0x1c +#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS__SHIFT 0x1d +#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK 0x00000002L +#define SDMA3_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL_MASK 0x00000010L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO_MASK 0x00000020L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI_MASK 0x00000040L +#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA3_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_MMHUB_CNTL_MASK 0x00080000L +#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL_MASK 0x04000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL_MASK 0x08000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL_MASK 0x10000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS_MASK 0x20000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA3_PUB_REG_TYPE1 +#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM__SHIFT 0x4 +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG__SHIFT 0x5 +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG__SHIFT 0x6 +#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL__SHIFT 0xa +#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE__SHIFT 0xb +#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA3_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG__SHIFT 0x12 +#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD__SHIFT 0x13 +#define SDMA3_PUB_REG_TYPE1__SDMA3_ID__SHIFT 0x14 +#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION__SHIFT 0x15 +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER__SHIFT 0x16 +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG__SHIFT 0x18 +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL__SHIFT 0x1c +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM_MASK 0x00000010L +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG_MASK 0x00000020L +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG_MASK 0x00000040L +#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL_MASK 0x00000400L +#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE_MASK 0x00000800L +#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA3_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG_MASK 0x00040000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD_MASK 0x00080000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_ID_MASK 0x00100000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION_MASK 0x00200000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_MASK 0x00400000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG_MASK 0x01000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL_MASK 0x10000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA3_PUB_REG_TYPE2 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2__SHIFT 0x2 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE__SHIFT 0x8 +#define SDMA3_PUB_REG_TYPE2__SDMA3_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG__SHIFT 0xc +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG__SHIFT 0x10 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER__SHIFT 0x15 +#define SDMA3_PUB_REG_TYPE2__SDMA3_UNBREAKABLE__SHIFT 0x16 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFMON_CNTL__SHIFT 0x17 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL__SHIFT 0x1b +#define SDMA3_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA3_PUB_REG_TYPE2__SDMA3_ULV_CNTL__SHIFT 0x1e +#define SDMA3_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1_MASK 0x00000002L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2_MASK 0x00000004L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE_MASK 0x00000100L +#define SDMA3_PUB_REG_TYPE2__SDMA3_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG_MASK 0x00001000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG_MASK 0x00010000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER_MASK 0x00200000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_UNBREAKABLE_MASK 0x00400000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFMON_CNTL_MASK 0x00800000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL_MASK 0x08000000L +#define SDMA3_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA3_PUB_REG_TYPE2__SDMA3_ULV_CNTL_MASK 0x40000000L +#define SDMA3_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA3_PUB_REG_TYPE3 +#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA3_PUB_REG_TYPE3__SDMA3_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA3_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA3_PUB_REG_TYPE3__SDMA3_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA3_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA3_MMHUB_CNTL +#define SDMA3_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA3_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA3_CONTEXT_GROUP_BOUNDARY +#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA3_POWER_CNTL +#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA3_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA3_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA3_CLK_CTRL +#define SDMA3_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA3_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA3_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA3_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA3_CNTL +#define SDMA3_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA3_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA3_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA3_CHICKEN_BITS +#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA3_GB_ADDR_CONFIG +#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA3_GB_ADDR_CONFIG_READ +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA3_RB_RPTR_FETCH_HI +#define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA3_RB_RPTR_FETCH +#define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA3_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA3_IB_OFFSET_FETCH +#define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA3_PROGRAM +#define SDMA3_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA3_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA3_STATUS_REG +#define SDMA3_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA3_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA3_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA3_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA3_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA3_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA3_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA3_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA3_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA3_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA3_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA3_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA3_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA3_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA3_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA3_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA3_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA3_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA3_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA3_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA3_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA3_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA3_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA3_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA3_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA3_STATUS1_REG +#define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA3_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA3_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA3_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA3_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA3_RD_BURST_CNTL +#define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA3_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA3_HBM_PAGE_CONFIG +#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA3_UCODE_CHECKSUM +#define SDMA3_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA3_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA3_F32_CNTL +#define SDMA3_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA3_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA3_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA3_F32_CNTL__STEP_MASK 0x00000002L +//SDMA3_FREEZE +#define SDMA3_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA3_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA3_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA3_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA3_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA3_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA3_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA3_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA3_PHASE0_QUANTUM +#define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA3_PHASE1_QUANTUM +#define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA3_EDC_CONFIG +#define SDMA3_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA3_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA3_BA_THRESHOLD +#define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA3_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA3_ID +#define SDMA3_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA3_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA3_VERSION +#define SDMA3_VERSION__MINVER__SHIFT 0x0 +#define SDMA3_VERSION__MAJVER__SHIFT 0x8 +#define SDMA3_VERSION__REV__SHIFT 0x10 +#define SDMA3_VERSION__MINVER_MASK 0x0000007FL +#define SDMA3_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA3_VERSION__REV_MASK 0x003F0000L +//SDMA3_EDC_COUNTER +#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA3_EDC_COUNTER_CLEAR +#define SDMA3_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA3_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA3_STATUS2_REG +#define SDMA3_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA3_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA3_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA3_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA3_ATOMIC_CNTL +#define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA3_ATOMIC_PREOP_LO +#define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA3_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA3_ATOMIC_PREOP_HI +#define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA3_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_CNTL +#define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA3_UTCL1_WATERMK +#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA3_UTCL1_RD_STATUS +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA3_UTCL1_WR_STATUS +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA3_UTCL1_INV0 +#define SDMA3_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA3_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA3_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA3_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA3_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA3_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA3_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA3_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA3_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA3_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA3_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA3_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA3_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA3_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA3_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA3_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA3_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA3_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA3_UTCL1_INV1 +#define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_INV2 +#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_RD_XNACK0 +#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_RD_XNACK1 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA3_UTCL1_WR_XNACK0 +#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA3_UTCL1_WR_XNACK1 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA3_UTCL1_TIMEOUT +#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA3_UTCL1_PAGE +#define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA3_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA3_POWER_CNTL_IDLE +#define SDMA3_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA3_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA3_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA3_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA3_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA3_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA3_RELAX_ORDERING_LUT +#define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA3_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA3_CHICKEN_BITS_2 +#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA3_STATUS3_REG +#define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA3_PHYSICAL_ADDR_LO +#define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA3_PHYSICAL_ADDR_HI +#define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA3_PHASE2_QUANTUM +#define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA3_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA3_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA3_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA3_ERROR_LOG +#define SDMA3_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA3_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA3_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA3_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA3_PUB_DUMMY_REG0 +#define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG1 +#define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG2 +#define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA3_PUB_DUMMY_REG3 +#define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA3_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA3_F32_COUNTER +#define SDMA3_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA3_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA3_UNBREAKABLE +#define SDMA3_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA3_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA3_PERFMON_CNTL +#define SDMA3_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA3_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA3_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA3_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA3_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA3_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA3_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA3_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA3_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA3_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA3_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA3_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA3_PERFCOUNTER0_RESULT +#define SDMA3_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA3_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA3_PERFCOUNTER1_RESULT +#define SDMA3_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA3_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA3_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA3_CRD_CNTL +#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA3_GPU_IOV_VIOLATION_LOG +#define SDMA3_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA3_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA3_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA3_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA3_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA3_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA3_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA3_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA3_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA3_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA3_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA3_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA3_ULV_CNTL +#define SDMA3_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA3_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA3_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA3_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA3_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA3_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA3_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA3_EA_DBIT_ADDR_DATA +#define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA3_EA_DBIT_ADDR_INDEX +#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA3_GPU_IOV_VIOLATION_LOG2 +#define SDMA3_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA3_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA3_GFX_RB_CNTL +#define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_GFX_RB_BASE +#define SDMA3_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_BASE_HI +#define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_GFX_RB_RPTR +#define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_RPTR_HI +#define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR +#define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_HI +#define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_CNTL +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_GFX_RB_RPTR_ADDR_HI +#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_RPTR_ADDR_LO +#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_IB_CNTL +#define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_GFX_IB_RPTR +#define SDMA3_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_GFX_IB_OFFSET +#define SDMA3_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_GFX_IB_BASE_LO +#define SDMA3_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_GFX_IB_BASE_HI +#define SDMA3_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_IB_SIZE +#define SDMA3_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_GFX_SKIP_CNTL +#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_GFX_CONTEXT_STATUS +#define SDMA3_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_GFX_DOORBELL +#define SDMA3_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_GFX_CONTEXT_CNTL +#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA3_GFX_STATUS +#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_GFX_DOORBELL_LOG +#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_GFX_WATERMARK +#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_GFX_DOORBELL_OFFSET +#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_GFX_CSA_ADDR_LO +#define SDMA3_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_CSA_ADDR_HI +#define SDMA3_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_IB_SUB_REMAIN +#define SDMA3_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_GFX_PREEMPT +#define SDMA3_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_GFX_DUMMY_REG +#define SDMA3_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_GFX_RB_AQL_CNTL +#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_GFX_MINOR_PTR_UPDATE +#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_GFX_MIDCMD_DATA0 +#define SDMA3_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA1 +#define SDMA3_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA2 +#define SDMA3_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA3 +#define SDMA3_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA4 +#define SDMA3_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA5 +#define SDMA3_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA6 +#define SDMA3_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA7 +#define SDMA3_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_DATA8 +#define SDMA3_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_GFX_MIDCMD_CNTL +#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_PAGE_RB_CNTL +#define SDMA3_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_PAGE_RB_BASE +#define SDMA3_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_BASE_HI +#define SDMA3_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_PAGE_RB_RPTR +#define SDMA3_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_RPTR_HI +#define SDMA3_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR +#define SDMA3_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_HI +#define SDMA3_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_CNTL +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_PAGE_RB_RPTR_ADDR_HI +#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_RPTR_ADDR_LO +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_IB_CNTL +#define SDMA3_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_PAGE_IB_RPTR +#define SDMA3_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_PAGE_IB_OFFSET +#define SDMA3_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_PAGE_IB_BASE_LO +#define SDMA3_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_PAGE_IB_BASE_HI +#define SDMA3_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_IB_SIZE +#define SDMA3_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_PAGE_SKIP_CNTL +#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_PAGE_CONTEXT_STATUS +#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_PAGE_DOORBELL +#define SDMA3_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_PAGE_STATUS +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_PAGE_DOORBELL_LOG +#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_PAGE_WATERMARK +#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_PAGE_DOORBELL_OFFSET +#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_PAGE_CSA_ADDR_LO +#define SDMA3_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_CSA_ADDR_HI +#define SDMA3_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_IB_SUB_REMAIN +#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_PAGE_PREEMPT +#define SDMA3_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_PAGE_DUMMY_REG +#define SDMA3_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_PAGE_RB_AQL_CNTL +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_PAGE_MINOR_PTR_UPDATE +#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_PAGE_MIDCMD_DATA0 +#define SDMA3_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA1 +#define SDMA3_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA2 +#define SDMA3_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA3 +#define SDMA3_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA4 +#define SDMA3_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA5 +#define SDMA3_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA6 +#define SDMA3_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA7 +#define SDMA3_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_DATA8 +#define SDMA3_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_PAGE_MIDCMD_CNTL +#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC0_RB_CNTL +#define SDMA3_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC0_RB_BASE +#define SDMA3_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_BASE_HI +#define SDMA3_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC0_RB_RPTR +#define SDMA3_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_RPTR_HI +#define SDMA3_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR +#define SDMA3_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_HI +#define SDMA3_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_CNTL +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC0_RB_RPTR_ADDR_HI +#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_RPTR_ADDR_LO +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_IB_CNTL +#define SDMA3_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC0_IB_RPTR +#define SDMA3_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC0_IB_OFFSET +#define SDMA3_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC0_IB_BASE_LO +#define SDMA3_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC0_IB_BASE_HI +#define SDMA3_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_IB_SIZE +#define SDMA3_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC0_SKIP_CNTL +#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC0_CONTEXT_STATUS +#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC0_DOORBELL +#define SDMA3_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC0_STATUS +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC0_DOORBELL_LOG +#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC0_WATERMARK +#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC0_DOORBELL_OFFSET +#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC0_CSA_ADDR_LO +#define SDMA3_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_CSA_ADDR_HI +#define SDMA3_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_IB_SUB_REMAIN +#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC0_PREEMPT +#define SDMA3_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC0_DUMMY_REG +#define SDMA3_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC0_RB_AQL_CNTL +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC0_MINOR_PTR_UPDATE +#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC0_MIDCMD_DATA0 +#define SDMA3_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA1 +#define SDMA3_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA2 +#define SDMA3_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA3 +#define SDMA3_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA4 +#define SDMA3_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA5 +#define SDMA3_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA6 +#define SDMA3_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA7 +#define SDMA3_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_DATA8 +#define SDMA3_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC0_MIDCMD_CNTL +#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC1_RB_CNTL +#define SDMA3_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC1_RB_BASE +#define SDMA3_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_BASE_HI +#define SDMA3_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC1_RB_RPTR +#define SDMA3_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_RPTR_HI +#define SDMA3_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR +#define SDMA3_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_HI +#define SDMA3_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_CNTL +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC1_RB_RPTR_ADDR_HI +#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_RPTR_ADDR_LO +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_IB_CNTL +#define SDMA3_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC1_IB_RPTR +#define SDMA3_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC1_IB_OFFSET +#define SDMA3_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC1_IB_BASE_LO +#define SDMA3_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC1_IB_BASE_HI +#define SDMA3_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_IB_SIZE +#define SDMA3_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC1_SKIP_CNTL +#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC1_CONTEXT_STATUS +#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC1_DOORBELL +#define SDMA3_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC1_STATUS +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC1_DOORBELL_LOG +#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC1_WATERMARK +#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC1_DOORBELL_OFFSET +#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC1_CSA_ADDR_LO +#define SDMA3_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_CSA_ADDR_HI +#define SDMA3_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_IB_SUB_REMAIN +#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC1_PREEMPT +#define SDMA3_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC1_DUMMY_REG +#define SDMA3_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC1_RB_AQL_CNTL +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC1_MINOR_PTR_UPDATE +#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC1_MIDCMD_DATA0 +#define SDMA3_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA1 +#define SDMA3_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA2 +#define SDMA3_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA3 +#define SDMA3_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA4 +#define SDMA3_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA5 +#define SDMA3_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA6 +#define SDMA3_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA7 +#define SDMA3_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_DATA8 +#define SDMA3_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC1_MIDCMD_CNTL +#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC2_RB_CNTL +#define SDMA3_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC2_RB_BASE +#define SDMA3_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_BASE_HI +#define SDMA3_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC2_RB_RPTR +#define SDMA3_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_RPTR_HI +#define SDMA3_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR +#define SDMA3_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_HI +#define SDMA3_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_CNTL +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC2_RB_RPTR_ADDR_HI +#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_RPTR_ADDR_LO +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_IB_CNTL +#define SDMA3_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC2_IB_RPTR +#define SDMA3_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC2_IB_OFFSET +#define SDMA3_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC2_IB_BASE_LO +#define SDMA3_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC2_IB_BASE_HI +#define SDMA3_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_IB_SIZE +#define SDMA3_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC2_SKIP_CNTL +#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC2_CONTEXT_STATUS +#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC2_DOORBELL +#define SDMA3_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC2_STATUS +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC2_DOORBELL_LOG +#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC2_WATERMARK +#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC2_DOORBELL_OFFSET +#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC2_CSA_ADDR_LO +#define SDMA3_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_CSA_ADDR_HI +#define SDMA3_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_IB_SUB_REMAIN +#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC2_PREEMPT +#define SDMA3_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC2_DUMMY_REG +#define SDMA3_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC2_RB_AQL_CNTL +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC2_MINOR_PTR_UPDATE +#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC2_MIDCMD_DATA0 +#define SDMA3_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA1 +#define SDMA3_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA2 +#define SDMA3_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA3 +#define SDMA3_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA4 +#define SDMA3_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA5 +#define SDMA3_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA6 +#define SDMA3_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA7 +#define SDMA3_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_DATA8 +#define SDMA3_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC2_MIDCMD_CNTL +#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC3_RB_CNTL +#define SDMA3_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC3_RB_BASE +#define SDMA3_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_BASE_HI +#define SDMA3_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC3_RB_RPTR +#define SDMA3_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_RPTR_HI +#define SDMA3_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR +#define SDMA3_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_HI +#define SDMA3_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_CNTL +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC3_RB_RPTR_ADDR_HI +#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_RPTR_ADDR_LO +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_IB_CNTL +#define SDMA3_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC3_IB_RPTR +#define SDMA3_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC3_IB_OFFSET +#define SDMA3_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC3_IB_BASE_LO +#define SDMA3_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC3_IB_BASE_HI +#define SDMA3_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_IB_SIZE +#define SDMA3_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC3_SKIP_CNTL +#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC3_CONTEXT_STATUS +#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC3_DOORBELL +#define SDMA3_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC3_STATUS +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC3_DOORBELL_LOG +#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC3_WATERMARK +#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC3_DOORBELL_OFFSET +#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC3_CSA_ADDR_LO +#define SDMA3_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_CSA_ADDR_HI +#define SDMA3_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_IB_SUB_REMAIN +#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC3_PREEMPT +#define SDMA3_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC3_DUMMY_REG +#define SDMA3_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC3_RB_AQL_CNTL +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC3_MINOR_PTR_UPDATE +#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC3_MIDCMD_DATA0 +#define SDMA3_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA1 +#define SDMA3_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA2 +#define SDMA3_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA3 +#define SDMA3_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA4 +#define SDMA3_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA5 +#define SDMA3_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA6 +#define SDMA3_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA7 +#define SDMA3_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_DATA8 +#define SDMA3_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC3_MIDCMD_CNTL +#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC4_RB_CNTL +#define SDMA3_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC4_RB_BASE +#define SDMA3_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_BASE_HI +#define SDMA3_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC4_RB_RPTR +#define SDMA3_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_RPTR_HI +#define SDMA3_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR +#define SDMA3_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_HI +#define SDMA3_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_CNTL +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC4_RB_RPTR_ADDR_HI +#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_RPTR_ADDR_LO +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_IB_CNTL +#define SDMA3_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC4_IB_RPTR +#define SDMA3_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC4_IB_OFFSET +#define SDMA3_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC4_IB_BASE_LO +#define SDMA3_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC4_IB_BASE_HI +#define SDMA3_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_IB_SIZE +#define SDMA3_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC4_SKIP_CNTL +#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC4_CONTEXT_STATUS +#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC4_DOORBELL +#define SDMA3_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC4_STATUS +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC4_DOORBELL_LOG +#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC4_WATERMARK +#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC4_DOORBELL_OFFSET +#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC4_CSA_ADDR_LO +#define SDMA3_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_CSA_ADDR_HI +#define SDMA3_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_IB_SUB_REMAIN +#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC4_PREEMPT +#define SDMA3_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC4_DUMMY_REG +#define SDMA3_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC4_RB_AQL_CNTL +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC4_MINOR_PTR_UPDATE +#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC4_MIDCMD_DATA0 +#define SDMA3_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA1 +#define SDMA3_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA2 +#define SDMA3_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA3 +#define SDMA3_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA4 +#define SDMA3_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA5 +#define SDMA3_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA6 +#define SDMA3_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA7 +#define SDMA3_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_DATA8 +#define SDMA3_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC4_MIDCMD_CNTL +#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC5_RB_CNTL +#define SDMA3_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC5_RB_BASE +#define SDMA3_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_BASE_HI +#define SDMA3_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC5_RB_RPTR +#define SDMA3_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_RPTR_HI +#define SDMA3_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR +#define SDMA3_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_HI +#define SDMA3_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_CNTL +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC5_RB_RPTR_ADDR_HI +#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_RPTR_ADDR_LO +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_IB_CNTL +#define SDMA3_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC5_IB_RPTR +#define SDMA3_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC5_IB_OFFSET +#define SDMA3_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC5_IB_BASE_LO +#define SDMA3_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC5_IB_BASE_HI +#define SDMA3_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_IB_SIZE +#define SDMA3_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC5_SKIP_CNTL +#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC5_CONTEXT_STATUS +#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC5_DOORBELL +#define SDMA3_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC5_STATUS +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC5_DOORBELL_LOG +#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC5_WATERMARK +#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC5_DOORBELL_OFFSET +#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC5_CSA_ADDR_LO +#define SDMA3_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_CSA_ADDR_HI +#define SDMA3_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_IB_SUB_REMAIN +#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC5_PREEMPT +#define SDMA3_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC5_DUMMY_REG +#define SDMA3_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC5_RB_AQL_CNTL +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC5_MINOR_PTR_UPDATE +#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC5_MIDCMD_DATA0 +#define SDMA3_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA1 +#define SDMA3_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA2 +#define SDMA3_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA3 +#define SDMA3_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA4 +#define SDMA3_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA5 +#define SDMA3_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA6 +#define SDMA3_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA7 +#define SDMA3_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_DATA8 +#define SDMA3_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC5_MIDCMD_CNTL +#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC6_RB_CNTL +#define SDMA3_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC6_RB_BASE +#define SDMA3_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_BASE_HI +#define SDMA3_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC6_RB_RPTR +#define SDMA3_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_RPTR_HI +#define SDMA3_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR +#define SDMA3_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_HI +#define SDMA3_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_CNTL +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC6_RB_RPTR_ADDR_HI +#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_RPTR_ADDR_LO +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_IB_CNTL +#define SDMA3_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC6_IB_RPTR +#define SDMA3_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC6_IB_OFFSET +#define SDMA3_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC6_IB_BASE_LO +#define SDMA3_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC6_IB_BASE_HI +#define SDMA3_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_IB_SIZE +#define SDMA3_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC6_SKIP_CNTL +#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC6_CONTEXT_STATUS +#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC6_DOORBELL +#define SDMA3_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC6_STATUS +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC6_DOORBELL_LOG +#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC6_WATERMARK +#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC6_DOORBELL_OFFSET +#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC6_CSA_ADDR_LO +#define SDMA3_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_CSA_ADDR_HI +#define SDMA3_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_IB_SUB_REMAIN +#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC6_PREEMPT +#define SDMA3_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC6_DUMMY_REG +#define SDMA3_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC6_RB_AQL_CNTL +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC6_MINOR_PTR_UPDATE +#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC6_MIDCMD_DATA0 +#define SDMA3_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA1 +#define SDMA3_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA2 +#define SDMA3_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA3 +#define SDMA3_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA4 +#define SDMA3_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA5 +#define SDMA3_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA6 +#define SDMA3_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA7 +#define SDMA3_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_DATA8 +#define SDMA3_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC6_MIDCMD_CNTL +#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA3_RLC7_RB_CNTL +#define SDMA3_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA3_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA3_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA3_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA3_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA3_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA3_RLC7_RB_BASE +#define SDMA3_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_BASE_HI +#define SDMA3_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA3_RLC7_RB_RPTR +#define SDMA3_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_RPTR_HI +#define SDMA3_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR +#define SDMA3_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_HI +#define SDMA3_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_CNTL +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA3_RLC7_RB_RPTR_ADDR_HI +#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_RPTR_ADDR_LO +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_IB_CNTL +#define SDMA3_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA3_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA3_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA3_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA3_RLC7_IB_RPTR +#define SDMA3_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC7_IB_OFFSET +#define SDMA3_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA3_RLC7_IB_BASE_LO +#define SDMA3_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA3_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA3_RLC7_IB_BASE_HI +#define SDMA3_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_IB_SIZE +#define SDMA3_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA3_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC7_SKIP_CNTL +#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA3_RLC7_CONTEXT_STATUS +#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA3_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA3_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA3_RLC7_DOORBELL +#define SDMA3_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA3_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA3_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA3_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA3_RLC7_STATUS +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA3_RLC7_DOORBELL_LOG +#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA3_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA3_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA3_RLC7_WATERMARK +#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA3_RLC7_DOORBELL_OFFSET +#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA3_RLC7_CSA_ADDR_LO +#define SDMA3_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_CSA_ADDR_HI +#define SDMA3_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_IB_SUB_REMAIN +#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA3_RLC7_PREEMPT +#define SDMA3_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA3_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA3_RLC7_DUMMY_REG +#define SDMA3_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA3_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA3_RLC7_RB_AQL_CNTL +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA3_RLC7_MINOR_PTR_UPDATE +#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA3_RLC7_MIDCMD_DATA0 +#define SDMA3_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA1 +#define SDMA3_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA2 +#define SDMA3_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA3 +#define SDMA3_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA4 +#define SDMA3_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA5 +#define SDMA3_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA6 +#define SDMA3_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA7 +#define SDMA3_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_DATA8 +#define SDMA3_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA3_RLC7_MIDCMD_CNTL +#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h new file mode 100644 index 000000000000..755ffa5781de --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma4_4_2_2_OFFSET_HEADER +#define _sdma4_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma4_sdma4dec +// base address: 0x7a000 +#define mmSDMA4_UCODE_ADDR 0x0000 +#define mmSDMA4_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA4_UCODE_DATA 0x0001 +#define mmSDMA4_UCODE_DATA_BASE_IDX 1 +#define mmSDMA4_VM_CNTL 0x0004 +#define mmSDMA4_VM_CNTL_BASE_IDX 1 +#define mmSDMA4_VM_CTX_LO 0x0005 +#define mmSDMA4_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA4_VM_CTX_HI 0x0006 +#define mmSDMA4_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA4_ACTIVE_FCN_ID 0x0007 +#define mmSDMA4_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA4_VM_CTX_CNTL 0x0008 +#define mmSDMA4_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA4_VIRT_RESET_REQ 0x0009 +#define mmSDMA4_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA4_VF_ENABLE 0x000a +#define mmSDMA4_VF_ENABLE_BASE_IDX 1 +#define mmSDMA4_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA4_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA4_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA4_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA4_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA4_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA4_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA4_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA4_PUB_REG_TYPE0 0x000f +#define mmSDMA4_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA4_PUB_REG_TYPE1 0x0010 +#define mmSDMA4_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA4_PUB_REG_TYPE2 0x0011 +#define mmSDMA4_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA4_PUB_REG_TYPE3 0x0012 +#define mmSDMA4_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA4_MMHUB_CNTL 0x0013 +#define mmSDMA4_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA4_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA4_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA4_POWER_CNTL 0x001a +#define mmSDMA4_POWER_CNTL_BASE_IDX 1 +#define mmSDMA4_CLK_CTRL 0x001b +#define mmSDMA4_CLK_CTRL_BASE_IDX 1 +#define mmSDMA4_CNTL 0x001c +#define mmSDMA4_CNTL_BASE_IDX 1 +#define mmSDMA4_CHICKEN_BITS 0x001d +#define mmSDMA4_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA4_GB_ADDR_CONFIG 0x001e +#define mmSDMA4_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA4_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA4_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA4_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA4_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA4_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA4_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA4_RB_RPTR_FETCH 0x0022 +#define mmSDMA4_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA4_IB_OFFSET_FETCH 0x0023 +#define mmSDMA4_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA4_PROGRAM 0x0024 +#define mmSDMA4_PROGRAM_BASE_IDX 1 +#define mmSDMA4_STATUS_REG 0x0025 +#define mmSDMA4_STATUS_REG_BASE_IDX 1 +#define mmSDMA4_STATUS1_REG 0x0026 +#define mmSDMA4_STATUS1_REG_BASE_IDX 1 +#define mmSDMA4_RD_BURST_CNTL 0x0027 +#define mmSDMA4_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA4_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA4_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA4_UCODE_CHECKSUM 0x0029 +#define mmSDMA4_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA4_F32_CNTL 0x002a +#define mmSDMA4_F32_CNTL_BASE_IDX 1 +#define mmSDMA4_FREEZE 0x002b +#define mmSDMA4_FREEZE_BASE_IDX 1 +#define mmSDMA4_PHASE0_QUANTUM 0x002c +#define mmSDMA4_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA4_PHASE1_QUANTUM 0x002d +#define mmSDMA4_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA4_EDC_CONFIG 0x0032 +#define mmSDMA4_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA4_BA_THRESHOLD 0x0033 +#define mmSDMA4_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA4_ID 0x0034 +#define mmSDMA4_ID_BASE_IDX 1 +#define mmSDMA4_VERSION 0x0035 +#define mmSDMA4_VERSION_BASE_IDX 1 +#define mmSDMA4_EDC_COUNTER 0x0036 +#define mmSDMA4_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA4_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA4_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA4_STATUS2_REG 0x0038 +#define mmSDMA4_STATUS2_REG_BASE_IDX 1 +#define mmSDMA4_ATOMIC_CNTL 0x0039 +#define mmSDMA4_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA4_ATOMIC_PREOP_LO 0x003a +#define mmSDMA4_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA4_ATOMIC_PREOP_HI 0x003b +#define mmSDMA4_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA4_UTCL1_CNTL 0x003c +#define mmSDMA4_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA4_UTCL1_WATERMK 0x003d +#define mmSDMA4_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA4_UTCL1_RD_STATUS 0x003e +#define mmSDMA4_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA4_UTCL1_WR_STATUS 0x003f +#define mmSDMA4_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA4_UTCL1_INV0 0x0040 +#define mmSDMA4_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA4_UTCL1_INV1 0x0041 +#define mmSDMA4_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA4_UTCL1_INV2 0x0042 +#define mmSDMA4_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA4_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA4_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA4_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA4_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA4_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA4_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA4_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA4_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA4_UTCL1_TIMEOUT 0x0047 +#define mmSDMA4_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA4_UTCL1_PAGE 0x0048 +#define mmSDMA4_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA4_POWER_CNTL_IDLE 0x0049 +#define mmSDMA4_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA4_RELAX_ORDERING_LUT 0x004a +#define mmSDMA4_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA4_CHICKEN_BITS_2 0x004b +#define mmSDMA4_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA4_STATUS3_REG 0x004c +#define mmSDMA4_STATUS3_REG_BASE_IDX 1 +#define mmSDMA4_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA4_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA4_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_PHASE2_QUANTUM 0x004f +#define mmSDMA4_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA4_ERROR_LOG 0x0050 +#define mmSDMA4_ERROR_LOG_BASE_IDX 1 +#define mmSDMA4_PUB_DUMMY_REG0 0x0051 +#define mmSDMA4_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA4_PUB_DUMMY_REG1 0x0052 +#define mmSDMA4_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA4_PUB_DUMMY_REG2 0x0053 +#define mmSDMA4_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA4_PUB_DUMMY_REG3 0x0054 +#define mmSDMA4_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA4_F32_COUNTER 0x0055 +#define mmSDMA4_F32_COUNTER_BASE_IDX 1 +#define mmSDMA4_UNBREAKABLE 0x0056 +#define mmSDMA4_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA4_PERFMON_CNTL 0x0057 +#define mmSDMA4_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA4_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA4_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA4_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA4_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA4_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA4_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA4_CRD_CNTL 0x005b +#define mmSDMA4_CRD_CNTL_BASE_IDX 1 +#define mmSDMA4_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA4_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA4_ULV_CNTL 0x005e +#define mmSDMA4_ULV_CNTL_BASE_IDX 1 +#define mmSDMA4_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA4_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA4_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA4_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA4_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA4_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA4_GFX_RB_CNTL 0x0080 +#define mmSDMA4_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_RB_BASE 0x0081 +#define mmSDMA4_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA4_GFX_RB_BASE_HI 0x0082 +#define mmSDMA4_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_RPTR 0x0083 +#define mmSDMA4_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA4_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR 0x0085 +#define mmSDMA4_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA4_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA4_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA4_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA4_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_GFX_IB_CNTL 0x008a +#define mmSDMA4_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_IB_RPTR 0x008b +#define mmSDMA4_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_GFX_IB_OFFSET 0x008c +#define mmSDMA4_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_GFX_IB_BASE_LO 0x008d +#define mmSDMA4_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_GFX_IB_BASE_HI 0x008e +#define mmSDMA4_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_GFX_IB_SIZE 0x008f +#define mmSDMA4_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_GFX_SKIP_CNTL 0x0090 +#define mmSDMA4_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA4_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_GFX_DOORBELL 0x0092 +#define mmSDMA4_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA4_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA4_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_STATUS 0x00a8 +#define mmSDMA4_GFX_STATUS_BASE_IDX 1 +#define mmSDMA4_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA4_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_GFX_WATERMARK 0x00aa +#define mmSDMA4_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA4_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA4_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA4_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA4_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA4_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_GFX_PREEMPT 0x00b0 +#define mmSDMA4_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA4_GFX_DUMMY_REG 0x00b1 +#define mmSDMA4_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA4_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA4_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA4_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA4_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA4_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA4_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA4_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA4_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA4_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA4_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA4_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA4_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_CNTL 0x00d8 +#define mmSDMA4_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_BASE 0x00d9 +#define mmSDMA4_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_BASE_HI 0x00da +#define mmSDMA4_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_RPTR 0x00db +#define mmSDMA4_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA4_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR 0x00dd +#define mmSDMA4_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA4_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA4_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA4_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA4_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_CNTL 0x00e2 +#define mmSDMA4_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_RPTR 0x00e3 +#define mmSDMA4_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA4_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA4_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA4_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_SIZE 0x00e7 +#define mmSDMA4_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA4_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA4_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_PAGE_DOORBELL 0x00ea +#define mmSDMA4_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA4_PAGE_STATUS 0x0100 +#define mmSDMA4_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA4_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA4_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_PAGE_WATERMARK 0x0102 +#define mmSDMA4_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA4_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA4_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA4_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA4_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA4_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_PAGE_PREEMPT 0x0108 +#define mmSDMA4_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA4_PAGE_DUMMY_REG 0x0109 +#define mmSDMA4_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA4_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA4_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA4_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA4_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA4_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA4_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA4_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA4_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA4_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA4_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA4_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA4_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_CNTL 0x0130 +#define mmSDMA4_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_BASE 0x0131 +#define mmSDMA4_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA4_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_RPTR 0x0133 +#define mmSDMA4_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA4_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR 0x0135 +#define mmSDMA4_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA4_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA4_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA4_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA4_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_CNTL 0x013a +#define mmSDMA4_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_RPTR 0x013b +#define mmSDMA4_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_OFFSET 0x013c +#define mmSDMA4_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_BASE_LO 0x013d +#define mmSDMA4_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_BASE_HI 0x013e +#define mmSDMA4_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_SIZE 0x013f +#define mmSDMA4_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA4_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA4_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC0_DOORBELL 0x0142 +#define mmSDMA4_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC0_STATUS 0x0158 +#define mmSDMA4_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA4_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC0_WATERMARK 0x015a +#define mmSDMA4_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA4_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA4_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA4_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA4_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC0_PREEMPT 0x0160 +#define mmSDMA4_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC0_DUMMY_REG 0x0161 +#define mmSDMA4_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA4_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA4_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA4_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA4_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA4_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA4_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA4_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA4_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA4_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA4_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA4_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA4_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_CNTL 0x0188 +#define mmSDMA4_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_BASE 0x0189 +#define mmSDMA4_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_BASE_HI 0x018a +#define mmSDMA4_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_RPTR 0x018b +#define mmSDMA4_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA4_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR 0x018d +#define mmSDMA4_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA4_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA4_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA4_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA4_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_CNTL 0x0192 +#define mmSDMA4_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_RPTR 0x0193 +#define mmSDMA4_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_OFFSET 0x0194 +#define mmSDMA4_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA4_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA4_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_SIZE 0x0197 +#define mmSDMA4_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA4_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA4_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC1_DOORBELL 0x019a +#define mmSDMA4_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC1_STATUS 0x01b0 +#define mmSDMA4_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA4_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC1_WATERMARK 0x01b2 +#define mmSDMA4_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA4_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA4_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA4_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA4_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC1_PREEMPT 0x01b8 +#define mmSDMA4_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA4_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA4_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA4_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA4_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA4_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA4_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA4_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA4_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA4_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA4_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA4_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA4_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA4_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_CNTL 0x01e0 +#define mmSDMA4_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_BASE 0x01e1 +#define mmSDMA4_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA4_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_RPTR 0x01e3 +#define mmSDMA4_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA4_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR 0x01e5 +#define mmSDMA4_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA4_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA4_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA4_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA4_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_CNTL 0x01ea +#define mmSDMA4_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_RPTR 0x01eb +#define mmSDMA4_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_OFFSET 0x01ec +#define mmSDMA4_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA4_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA4_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_SIZE 0x01ef +#define mmSDMA4_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA4_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA4_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC2_DOORBELL 0x01f2 +#define mmSDMA4_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC2_STATUS 0x0208 +#define mmSDMA4_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA4_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC2_WATERMARK 0x020a +#define mmSDMA4_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA4_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA4_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA4_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA4_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC2_PREEMPT 0x0210 +#define mmSDMA4_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC2_DUMMY_REG 0x0211 +#define mmSDMA4_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA4_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA4_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA4_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA4_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA4_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA4_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA4_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA4_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA4_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA4_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA4_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA4_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_CNTL 0x0238 +#define mmSDMA4_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_BASE 0x0239 +#define mmSDMA4_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_BASE_HI 0x023a +#define mmSDMA4_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_RPTR 0x023b +#define mmSDMA4_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA4_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR 0x023d +#define mmSDMA4_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA4_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA4_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA4_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA4_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_CNTL 0x0242 +#define mmSDMA4_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_RPTR 0x0243 +#define mmSDMA4_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_OFFSET 0x0244 +#define mmSDMA4_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA4_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA4_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_SIZE 0x0247 +#define mmSDMA4_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA4_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA4_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC3_DOORBELL 0x024a +#define mmSDMA4_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC3_STATUS 0x0260 +#define mmSDMA4_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA4_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC3_WATERMARK 0x0262 +#define mmSDMA4_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA4_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA4_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA4_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA4_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC3_PREEMPT 0x0268 +#define mmSDMA4_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC3_DUMMY_REG 0x0269 +#define mmSDMA4_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA4_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA4_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA4_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA4_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA4_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA4_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA4_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA4_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA4_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA4_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA4_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA4_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_CNTL 0x0290 +#define mmSDMA4_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_BASE 0x0291 +#define mmSDMA4_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA4_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_RPTR 0x0293 +#define mmSDMA4_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA4_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR 0x0295 +#define mmSDMA4_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA4_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA4_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA4_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA4_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_CNTL 0x029a +#define mmSDMA4_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_RPTR 0x029b +#define mmSDMA4_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_OFFSET 0x029c +#define mmSDMA4_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_BASE_LO 0x029d +#define mmSDMA4_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_BASE_HI 0x029e +#define mmSDMA4_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_SIZE 0x029f +#define mmSDMA4_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA4_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA4_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC4_DOORBELL 0x02a2 +#define mmSDMA4_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC4_STATUS 0x02b8 +#define mmSDMA4_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA4_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC4_WATERMARK 0x02ba +#define mmSDMA4_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA4_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA4_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA4_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA4_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC4_PREEMPT 0x02c0 +#define mmSDMA4_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA4_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA4_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA4_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA4_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA4_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA4_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA4_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA4_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA4_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA4_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA4_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA4_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA4_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_CNTL 0x02e8 +#define mmSDMA4_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_BASE 0x02e9 +#define mmSDMA4_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA4_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_RPTR 0x02eb +#define mmSDMA4_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA4_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR 0x02ed +#define mmSDMA4_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA4_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA4_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA4_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA4_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_CNTL 0x02f2 +#define mmSDMA4_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_RPTR 0x02f3 +#define mmSDMA4_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA4_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA4_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA4_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_SIZE 0x02f7 +#define mmSDMA4_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA4_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA4_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC5_DOORBELL 0x02fa +#define mmSDMA4_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC5_STATUS 0x0310 +#define mmSDMA4_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA4_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC5_WATERMARK 0x0312 +#define mmSDMA4_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA4_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA4_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA4_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA4_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC5_PREEMPT 0x0318 +#define mmSDMA4_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC5_DUMMY_REG 0x0319 +#define mmSDMA4_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA4_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA4_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA4_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA4_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA4_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA4_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA4_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA4_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA4_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA4_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA4_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA4_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_CNTL 0x0340 +#define mmSDMA4_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_BASE 0x0341 +#define mmSDMA4_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA4_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_RPTR 0x0343 +#define mmSDMA4_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA4_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR 0x0345 +#define mmSDMA4_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA4_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA4_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA4_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA4_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_CNTL 0x034a +#define mmSDMA4_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_RPTR 0x034b +#define mmSDMA4_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_OFFSET 0x034c +#define mmSDMA4_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_BASE_LO 0x034d +#define mmSDMA4_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_BASE_HI 0x034e +#define mmSDMA4_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_SIZE 0x034f +#define mmSDMA4_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA4_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA4_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC6_DOORBELL 0x0352 +#define mmSDMA4_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC6_STATUS 0x0368 +#define mmSDMA4_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA4_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC6_WATERMARK 0x036a +#define mmSDMA4_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA4_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA4_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA4_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA4_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC6_PREEMPT 0x0370 +#define mmSDMA4_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC6_DUMMY_REG 0x0371 +#define mmSDMA4_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA4_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA4_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA4_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA4_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA4_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA4_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA4_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA4_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA4_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA4_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA4_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA4_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_CNTL 0x0398 +#define mmSDMA4_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_BASE 0x0399 +#define mmSDMA4_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_BASE_HI 0x039a +#define mmSDMA4_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_RPTR 0x039b +#define mmSDMA4_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA4_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR 0x039d +#define mmSDMA4_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA4_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA4_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA4_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA4_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_CNTL 0x03a2 +#define mmSDMA4_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_RPTR 0x03a3 +#define mmSDMA4_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA4_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA4_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA4_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_SIZE 0x03a7 +#define mmSDMA4_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA4_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA4_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA4_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC7_DOORBELL 0x03aa +#define mmSDMA4_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA4_RLC7_STATUS 0x03c0 +#define mmSDMA4_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA4_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA4_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA4_RLC7_WATERMARK 0x03c2 +#define mmSDMA4_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA4_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA4_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA4_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA4_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA4_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA4_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA4_RLC7_PREEMPT 0x03c8 +#define mmSDMA4_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA4_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA4_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA4_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA4_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA4_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA4_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA4_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA4_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA4_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA4_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA4_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA4_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA4_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA4_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA4_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA4_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA4_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h new file mode 100644 index 000000000000..2cc510913214 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma4_4_2_2_SH_MASK_HEADER +#define _sdma4_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma4_sdma4dec +//SDMA4_UCODE_ADDR +#define SDMA4_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA4_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA4_UCODE_DATA +#define SDMA4_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA4_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA4_VM_CNTL +#define SDMA4_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA4_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA4_VM_CTX_LO +#define SDMA4_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA4_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_VM_CTX_HI +#define SDMA4_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA4_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_ACTIVE_FCN_ID +#define SDMA4_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA4_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA4_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA4_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA4_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA4_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA4_VM_CTX_CNTL +#define SDMA4_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA4_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA4_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA4_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA4_VIRT_RESET_REQ +#define SDMA4_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA4_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA4_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA4_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA4_VF_ENABLE +#define SDMA4_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA4_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA4_CONTEXT_REG_TYPE0 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE__SHIFT 0x1 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_CNTL__SHIFT 0xa +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_RPTR__SHIFT 0xb +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_SIZE__SHIFT 0xf +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_DOORBELL__SHIFT 0x12 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_MASK 0x00000002L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_DOORBELL_MASK 0x00040000L +#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA4_CONTEXT_REG_TYPE1 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_STATUS__SHIFT 0x8 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_WATERMARK__SHIFT 0xa +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA4_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_PREEMPT__SHIFT 0x10 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA4_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_STATUS_MASK 0x00000100L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_WATERMARK_MASK 0x00000400L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA4_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_PREEMPT_MASK 0x00010000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA4_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA4_CONTEXT_REG_TYPE2 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA4_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA4_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA4_CONTEXT_REG_TYPE3 +#define SDMA4_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA4_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA4_PUB_REG_TYPE0 +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CNTL__SHIFT 0x4 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_LO__SHIFT 0x5 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_HI__SHIFT 0x6 +#define SDMA4_PUB_REG_TYPE0__SDMA4_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA4_PUB_REG_TYPE0__SDMA4_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA4_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA4_PUB_REG_TYPE0__SDMA4_MMHUB_CNTL__SHIFT 0x13 +#define SDMA4_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA4_PUB_REG_TYPE0__SDMA4_POWER_CNTL__SHIFT 0x1a +#define SDMA4_PUB_REG_TYPE0__SDMA4_CLK_CTRL__SHIFT 0x1b +#define SDMA4_PUB_REG_TYPE0__SDMA4_CNTL__SHIFT 0x1c +#define SDMA4_PUB_REG_TYPE0__SDMA4_CHICKEN_BITS__SHIFT 0x1d +#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA_MASK 0x00000002L +#define SDMA4_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CNTL_MASK 0x00000010L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_LO_MASK 0x00000020L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_HI_MASK 0x00000040L +#define SDMA4_PUB_REG_TYPE0__SDMA4_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA4_PUB_REG_TYPE0__SDMA4_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA4_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_MMHUB_CNTL_MASK 0x00080000L +#define SDMA4_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_POWER_CNTL_MASK 0x04000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CLK_CTRL_MASK 0x08000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CNTL_MASK 0x10000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_CHICKEN_BITS_MASK 0x20000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA4_PUB_REG_TYPE1 +#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE1__SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA4_PUB_REG_TYPE1__SDMA4_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA4_PUB_REG_TYPE1__SDMA4_PROGRAM__SHIFT 0x4 +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS_REG__SHIFT 0x5 +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS1_REG__SHIFT 0x6 +#define SDMA4_PUB_REG_TYPE1__SDMA4_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA4_PUB_REG_TYPE1__SDMA4_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA4_PUB_REG_TYPE1__SDMA4_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA4_PUB_REG_TYPE1__SDMA4_F32_CNTL__SHIFT 0xa +#define SDMA4_PUB_REG_TYPE1__SDMA4_FREEZE__SHIFT 0xb +#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA4_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_CONFIG__SHIFT 0x12 +#define SDMA4_PUB_REG_TYPE1__SDMA4_BA_THRESHOLD__SHIFT 0x13 +#define SDMA4_PUB_REG_TYPE1__SDMA4_ID__SHIFT 0x14 +#define SDMA4_PUB_REG_TYPE1__SDMA4_VERSION__SHIFT 0x15 +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER__SHIFT 0x16 +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS2_REG__SHIFT 0x18 +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_CNTL__SHIFT 0x1c +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE1__SDMA4_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA4_PUB_REG_TYPE1__SDMA4_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA4_PUB_REG_TYPE1__SDMA4_PROGRAM_MASK 0x00000010L +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS_REG_MASK 0x00000020L +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS1_REG_MASK 0x00000040L +#define SDMA4_PUB_REG_TYPE1__SDMA4_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA4_PUB_REG_TYPE1__SDMA4_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA4_PUB_REG_TYPE1__SDMA4_F32_CNTL_MASK 0x00000400L +#define SDMA4_PUB_REG_TYPE1__SDMA4_FREEZE_MASK 0x00000800L +#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA4_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_CONFIG_MASK 0x00040000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_BA_THRESHOLD_MASK 0x00080000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_ID_MASK 0x00100000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_VERSION_MASK 0x00200000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_MASK 0x00400000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS2_REG_MASK 0x01000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_CNTL_MASK 0x10000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA4_PUB_REG_TYPE2 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV0__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV1__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV2__SHIFT 0x2 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_PAGE__SHIFT 0x8 +#define SDMA4_PUB_REG_TYPE2__SDMA4_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA4_PUB_REG_TYPE2__SDMA4_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA4_PUB_REG_TYPE2__SDMA4_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA4_PUB_REG_TYPE2__SDMA4_STATUS3_REG__SHIFT 0xc +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA4_PUB_REG_TYPE2__SDMA4_ERROR_LOG__SHIFT 0x10 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA4_PUB_REG_TYPE2__SDMA4_F32_COUNTER__SHIFT 0x15 +#define SDMA4_PUB_REG_TYPE2__SDMA4_UNBREAKABLE__SHIFT 0x16 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFMON_CNTL__SHIFT 0x17 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA4_PUB_REG_TYPE2__SDMA4_CRD_CNTL__SHIFT 0x1b +#define SDMA4_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA4_PUB_REG_TYPE2__SDMA4_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA4_PUB_REG_TYPE2__SDMA4_ULV_CNTL__SHIFT 0x1e +#define SDMA4_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV0_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV1_MASK 0x00000002L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV2_MASK 0x00000004L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_PAGE_MASK 0x00000100L +#define SDMA4_PUB_REG_TYPE2__SDMA4_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA4_PUB_REG_TYPE2__SDMA4_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA4_PUB_REG_TYPE2__SDMA4_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA4_PUB_REG_TYPE2__SDMA4_STATUS3_REG_MASK 0x00001000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_ERROR_LOG_MASK 0x00010000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_F32_COUNTER_MASK 0x00200000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_UNBREAKABLE_MASK 0x00400000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFMON_CNTL_MASK 0x00800000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_CRD_CNTL_MASK 0x08000000L +#define SDMA4_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA4_PUB_REG_TYPE2__SDMA4_ULV_CNTL_MASK 0x40000000L +#define SDMA4_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA4_PUB_REG_TYPE3 +#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA4_PUB_REG_TYPE3__SDMA4_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA4_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA4_PUB_REG_TYPE3__SDMA4_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA4_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA4_MMHUB_CNTL +#define SDMA4_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA4_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA4_CONTEXT_GROUP_BOUNDARY +#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA4_POWER_CNTL +#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA4_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA4_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA4_CLK_CTRL +#define SDMA4_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA4_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA4_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA4_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA4_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA4_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA4_CNTL +#define SDMA4_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA4_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA4_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA4_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA4_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA4_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA4_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA4_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA4_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA4_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA4_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA4_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA4_CHICKEN_BITS +#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA4_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA4_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA4_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA4_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA4_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA4_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA4_GB_ADDR_CONFIG +#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA4_GB_ADDR_CONFIG_READ +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA4_RB_RPTR_FETCH_HI +#define SDMA4_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA4_RB_RPTR_FETCH +#define SDMA4_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA4_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA4_IB_OFFSET_FETCH +#define SDMA4_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA4_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA4_PROGRAM +#define SDMA4_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA4_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA4_STATUS_REG +#define SDMA4_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA4_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA4_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA4_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA4_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA4_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA4_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA4_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA4_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA4_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA4_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA4_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA4_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA4_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA4_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA4_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA4_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA4_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA4_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA4_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA4_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA4_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA4_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA4_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA4_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA4_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA4_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA4_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA4_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA4_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA4_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA4_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA4_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA4_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA4_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA4_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA4_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA4_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA4_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA4_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA4_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA4_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA4_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA4_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA4_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA4_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA4_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA4_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA4_STATUS1_REG +#define SDMA4_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA4_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA4_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA4_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA4_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA4_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA4_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA4_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA4_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA4_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA4_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA4_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA4_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA4_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA4_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA4_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA4_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA4_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA4_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA4_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA4_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA4_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA4_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA4_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA4_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA4_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA4_RD_BURST_CNTL +#define SDMA4_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA4_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA4_HBM_PAGE_CONFIG +#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA4_UCODE_CHECKSUM +#define SDMA4_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA4_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA4_F32_CNTL +#define SDMA4_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA4_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA4_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA4_F32_CNTL__STEP_MASK 0x00000002L +//SDMA4_FREEZE +#define SDMA4_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA4_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA4_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA4_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA4_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA4_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA4_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA4_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA4_PHASE0_QUANTUM +#define SDMA4_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA4_PHASE1_QUANTUM +#define SDMA4_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA4_EDC_CONFIG +#define SDMA4_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA4_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA4_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA4_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA4_BA_THRESHOLD +#define SDMA4_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA4_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA4_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA4_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA4_ID +#define SDMA4_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA4_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA4_VERSION +#define SDMA4_VERSION__MINVER__SHIFT 0x0 +#define SDMA4_VERSION__MAJVER__SHIFT 0x8 +#define SDMA4_VERSION__REV__SHIFT 0x10 +#define SDMA4_VERSION__MINVER_MASK 0x0000007FL +#define SDMA4_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA4_VERSION__REV_MASK 0x003F0000L +//SDMA4_EDC_COUNTER +#define SDMA4_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA4_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA4_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA4_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA4_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA4_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA4_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA4_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA4_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA4_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA4_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA4_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA4_EDC_COUNTER_CLEAR +#define SDMA4_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA4_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA4_STATUS2_REG +#define SDMA4_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA4_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA4_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA4_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA4_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA4_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA4_ATOMIC_CNTL +#define SDMA4_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA4_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA4_ATOMIC_PREOP_LO +#define SDMA4_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA4_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA4_ATOMIC_PREOP_HI +#define SDMA4_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA4_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_CNTL +#define SDMA4_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA4_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA4_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA4_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA4_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA4_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA4_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA4_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA4_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA4_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA4_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA4_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA4_UTCL1_WATERMK +#define SDMA4_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA4_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA4_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA4_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA4_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA4_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA4_UTCL1_RD_STATUS +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA4_UTCL1_WR_STATUS +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA4_UTCL1_INV0 +#define SDMA4_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA4_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA4_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA4_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA4_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA4_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA4_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA4_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA4_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA4_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA4_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA4_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA4_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA4_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA4_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA4_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA4_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA4_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA4_UTCL1_INV1 +#define SDMA4_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_INV2 +#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_RD_XNACK0 +#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_RD_XNACK1 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA4_UTCL1_WR_XNACK0 +#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA4_UTCL1_WR_XNACK1 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA4_UTCL1_TIMEOUT +#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA4_UTCL1_PAGE +#define SDMA4_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA4_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA4_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA4_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA4_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA4_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA4_POWER_CNTL_IDLE +#define SDMA4_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA4_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA4_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA4_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA4_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA4_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA4_RELAX_ORDERING_LUT +#define SDMA4_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA4_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA4_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA4_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA4_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA4_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA4_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA4_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA4_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA4_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA4_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA4_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA4_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA4_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA4_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA4_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA4_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA4_CHICKEN_BITS_2 +#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA4_STATUS3_REG +#define SDMA4_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA4_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA4_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA4_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA4_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA4_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA4_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA4_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA4_PHYSICAL_ADDR_LO +#define SDMA4_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA4_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA4_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA4_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA4_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA4_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA4_PHYSICAL_ADDR_HI +#define SDMA4_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA4_PHASE2_QUANTUM +#define SDMA4_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA4_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA4_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA4_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA4_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA4_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA4_ERROR_LOG +#define SDMA4_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA4_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA4_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA4_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA4_PUB_DUMMY_REG0 +#define SDMA4_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG1 +#define SDMA4_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG2 +#define SDMA4_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA4_PUB_DUMMY_REG3 +#define SDMA4_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA4_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA4_F32_COUNTER +#define SDMA4_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA4_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA4_UNBREAKABLE +#define SDMA4_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA4_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA4_PERFMON_CNTL +#define SDMA4_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA4_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA4_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA4_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA4_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA4_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA4_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA4_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA4_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA4_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA4_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA4_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA4_PERFCOUNTER0_RESULT +#define SDMA4_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA4_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA4_PERFCOUNTER1_RESULT +#define SDMA4_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA4_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA4_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA4_CRD_CNTL +#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA4_GPU_IOV_VIOLATION_LOG +#define SDMA4_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA4_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA4_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA4_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA4_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA4_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA4_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA4_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA4_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA4_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA4_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA4_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA4_ULV_CNTL +#define SDMA4_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA4_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA4_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA4_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA4_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA4_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA4_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA4_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA4_EA_DBIT_ADDR_DATA +#define SDMA4_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA4_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA4_EA_DBIT_ADDR_INDEX +#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA4_GPU_IOV_VIOLATION_LOG2 +#define SDMA4_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA4_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA4_GFX_RB_CNTL +#define SDMA4_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_GFX_RB_BASE +#define SDMA4_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_BASE_HI +#define SDMA4_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_GFX_RB_RPTR +#define SDMA4_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_RPTR_HI +#define SDMA4_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR +#define SDMA4_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_HI +#define SDMA4_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_CNTL +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_GFX_RB_RPTR_ADDR_HI +#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_RPTR_ADDR_LO +#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_IB_CNTL +#define SDMA4_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_GFX_IB_RPTR +#define SDMA4_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_GFX_IB_OFFSET +#define SDMA4_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_GFX_IB_BASE_LO +#define SDMA4_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_GFX_IB_BASE_HI +#define SDMA4_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_IB_SIZE +#define SDMA4_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_GFX_SKIP_CNTL +#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_GFX_CONTEXT_STATUS +#define SDMA4_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_GFX_DOORBELL +#define SDMA4_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_GFX_CONTEXT_CNTL +#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA4_GFX_STATUS +#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_GFX_DOORBELL_LOG +#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_GFX_WATERMARK +#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_GFX_DOORBELL_OFFSET +#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_GFX_CSA_ADDR_LO +#define SDMA4_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_CSA_ADDR_HI +#define SDMA4_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_IB_SUB_REMAIN +#define SDMA4_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_GFX_PREEMPT +#define SDMA4_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_GFX_DUMMY_REG +#define SDMA4_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_GFX_RB_AQL_CNTL +#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_GFX_MINOR_PTR_UPDATE +#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_GFX_MIDCMD_DATA0 +#define SDMA4_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA1 +#define SDMA4_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA2 +#define SDMA4_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA3 +#define SDMA4_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA4 +#define SDMA4_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA5 +#define SDMA4_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA6 +#define SDMA4_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA7 +#define SDMA4_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_DATA8 +#define SDMA4_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_GFX_MIDCMD_CNTL +#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_PAGE_RB_CNTL +#define SDMA4_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_PAGE_RB_BASE +#define SDMA4_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_BASE_HI +#define SDMA4_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_PAGE_RB_RPTR +#define SDMA4_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_RPTR_HI +#define SDMA4_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR +#define SDMA4_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_HI +#define SDMA4_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_CNTL +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_PAGE_RB_RPTR_ADDR_HI +#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_RPTR_ADDR_LO +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_IB_CNTL +#define SDMA4_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_PAGE_IB_RPTR +#define SDMA4_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_PAGE_IB_OFFSET +#define SDMA4_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_PAGE_IB_BASE_LO +#define SDMA4_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_PAGE_IB_BASE_HI +#define SDMA4_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_IB_SIZE +#define SDMA4_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_PAGE_SKIP_CNTL +#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_PAGE_CONTEXT_STATUS +#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_PAGE_DOORBELL +#define SDMA4_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_PAGE_STATUS +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_PAGE_DOORBELL_LOG +#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_PAGE_WATERMARK +#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_PAGE_DOORBELL_OFFSET +#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_PAGE_CSA_ADDR_LO +#define SDMA4_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_CSA_ADDR_HI +#define SDMA4_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_IB_SUB_REMAIN +#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_PAGE_PREEMPT +#define SDMA4_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_PAGE_DUMMY_REG +#define SDMA4_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_PAGE_RB_AQL_CNTL +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_PAGE_MINOR_PTR_UPDATE +#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_PAGE_MIDCMD_DATA0 +#define SDMA4_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA1 +#define SDMA4_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA2 +#define SDMA4_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA3 +#define SDMA4_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA4 +#define SDMA4_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA5 +#define SDMA4_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA6 +#define SDMA4_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA7 +#define SDMA4_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_DATA8 +#define SDMA4_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_PAGE_MIDCMD_CNTL +#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC0_RB_CNTL +#define SDMA4_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC0_RB_BASE +#define SDMA4_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_BASE_HI +#define SDMA4_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC0_RB_RPTR +#define SDMA4_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_RPTR_HI +#define SDMA4_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR +#define SDMA4_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_HI +#define SDMA4_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_CNTL +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC0_RB_RPTR_ADDR_HI +#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_RPTR_ADDR_LO +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_IB_CNTL +#define SDMA4_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC0_IB_RPTR +#define SDMA4_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC0_IB_OFFSET +#define SDMA4_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC0_IB_BASE_LO +#define SDMA4_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC0_IB_BASE_HI +#define SDMA4_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_IB_SIZE +#define SDMA4_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC0_SKIP_CNTL +#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC0_CONTEXT_STATUS +#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC0_DOORBELL +#define SDMA4_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC0_STATUS +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC0_DOORBELL_LOG +#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC0_WATERMARK +#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC0_DOORBELL_OFFSET +#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC0_CSA_ADDR_LO +#define SDMA4_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_CSA_ADDR_HI +#define SDMA4_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_IB_SUB_REMAIN +#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC0_PREEMPT +#define SDMA4_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC0_DUMMY_REG +#define SDMA4_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC0_RB_AQL_CNTL +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC0_MINOR_PTR_UPDATE +#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC0_MIDCMD_DATA0 +#define SDMA4_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA1 +#define SDMA4_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA2 +#define SDMA4_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA3 +#define SDMA4_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA4 +#define SDMA4_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA5 +#define SDMA4_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA6 +#define SDMA4_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA7 +#define SDMA4_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_DATA8 +#define SDMA4_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC0_MIDCMD_CNTL +#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC1_RB_CNTL +#define SDMA4_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC1_RB_BASE +#define SDMA4_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_BASE_HI +#define SDMA4_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC1_RB_RPTR +#define SDMA4_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_RPTR_HI +#define SDMA4_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR +#define SDMA4_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_HI +#define SDMA4_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_CNTL +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC1_RB_RPTR_ADDR_HI +#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_RPTR_ADDR_LO +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_IB_CNTL +#define SDMA4_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC1_IB_RPTR +#define SDMA4_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC1_IB_OFFSET +#define SDMA4_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC1_IB_BASE_LO +#define SDMA4_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC1_IB_BASE_HI +#define SDMA4_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_IB_SIZE +#define SDMA4_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC1_SKIP_CNTL +#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC1_CONTEXT_STATUS +#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC1_DOORBELL +#define SDMA4_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC1_STATUS +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC1_DOORBELL_LOG +#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC1_WATERMARK +#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC1_DOORBELL_OFFSET +#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC1_CSA_ADDR_LO +#define SDMA4_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_CSA_ADDR_HI +#define SDMA4_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_IB_SUB_REMAIN +#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC1_PREEMPT +#define SDMA4_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC1_DUMMY_REG +#define SDMA4_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC1_RB_AQL_CNTL +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC1_MINOR_PTR_UPDATE +#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC1_MIDCMD_DATA0 +#define SDMA4_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA1 +#define SDMA4_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA2 +#define SDMA4_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA3 +#define SDMA4_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA4 +#define SDMA4_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA5 +#define SDMA4_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA6 +#define SDMA4_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA7 +#define SDMA4_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_DATA8 +#define SDMA4_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC1_MIDCMD_CNTL +#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC2_RB_CNTL +#define SDMA4_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC2_RB_BASE +#define SDMA4_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_BASE_HI +#define SDMA4_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC2_RB_RPTR +#define SDMA4_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_RPTR_HI +#define SDMA4_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR +#define SDMA4_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_HI +#define SDMA4_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_CNTL +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC2_RB_RPTR_ADDR_HI +#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_RPTR_ADDR_LO +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_IB_CNTL +#define SDMA4_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC2_IB_RPTR +#define SDMA4_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC2_IB_OFFSET +#define SDMA4_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC2_IB_BASE_LO +#define SDMA4_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC2_IB_BASE_HI +#define SDMA4_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_IB_SIZE +#define SDMA4_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC2_SKIP_CNTL +#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC2_CONTEXT_STATUS +#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC2_DOORBELL +#define SDMA4_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC2_STATUS +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC2_DOORBELL_LOG +#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC2_WATERMARK +#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC2_DOORBELL_OFFSET +#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC2_CSA_ADDR_LO +#define SDMA4_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_CSA_ADDR_HI +#define SDMA4_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_IB_SUB_REMAIN +#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC2_PREEMPT +#define SDMA4_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC2_DUMMY_REG +#define SDMA4_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC2_RB_AQL_CNTL +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC2_MINOR_PTR_UPDATE +#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC2_MIDCMD_DATA0 +#define SDMA4_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA1 +#define SDMA4_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA2 +#define SDMA4_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA3 +#define SDMA4_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA4 +#define SDMA4_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA5 +#define SDMA4_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA6 +#define SDMA4_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA7 +#define SDMA4_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_DATA8 +#define SDMA4_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC2_MIDCMD_CNTL +#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC3_RB_CNTL +#define SDMA4_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC3_RB_BASE +#define SDMA4_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_BASE_HI +#define SDMA4_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC3_RB_RPTR +#define SDMA4_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_RPTR_HI +#define SDMA4_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR +#define SDMA4_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_HI +#define SDMA4_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_CNTL +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC3_RB_RPTR_ADDR_HI +#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_RPTR_ADDR_LO +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_IB_CNTL +#define SDMA4_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC3_IB_RPTR +#define SDMA4_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC3_IB_OFFSET +#define SDMA4_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC3_IB_BASE_LO +#define SDMA4_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC3_IB_BASE_HI +#define SDMA4_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_IB_SIZE +#define SDMA4_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC3_SKIP_CNTL +#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC3_CONTEXT_STATUS +#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC3_DOORBELL +#define SDMA4_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC3_STATUS +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC3_DOORBELL_LOG +#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC3_WATERMARK +#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC3_DOORBELL_OFFSET +#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC3_CSA_ADDR_LO +#define SDMA4_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_CSA_ADDR_HI +#define SDMA4_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_IB_SUB_REMAIN +#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC3_PREEMPT +#define SDMA4_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC3_DUMMY_REG +#define SDMA4_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC3_RB_AQL_CNTL +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC3_MINOR_PTR_UPDATE +#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC3_MIDCMD_DATA0 +#define SDMA4_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA1 +#define SDMA4_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA2 +#define SDMA4_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA3 +#define SDMA4_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA4 +#define SDMA4_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA5 +#define SDMA4_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA6 +#define SDMA4_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA7 +#define SDMA4_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_DATA8 +#define SDMA4_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC3_MIDCMD_CNTL +#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC4_RB_CNTL +#define SDMA4_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC4_RB_BASE +#define SDMA4_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_BASE_HI +#define SDMA4_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC4_RB_RPTR +#define SDMA4_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_RPTR_HI +#define SDMA4_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR +#define SDMA4_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_HI +#define SDMA4_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_CNTL +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC4_RB_RPTR_ADDR_HI +#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_RPTR_ADDR_LO +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_IB_CNTL +#define SDMA4_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC4_IB_RPTR +#define SDMA4_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC4_IB_OFFSET +#define SDMA4_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC4_IB_BASE_LO +#define SDMA4_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC4_IB_BASE_HI +#define SDMA4_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_IB_SIZE +#define SDMA4_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC4_SKIP_CNTL +#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC4_CONTEXT_STATUS +#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC4_DOORBELL +#define SDMA4_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC4_STATUS +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC4_DOORBELL_LOG +#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC4_WATERMARK +#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC4_DOORBELL_OFFSET +#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC4_CSA_ADDR_LO +#define SDMA4_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_CSA_ADDR_HI +#define SDMA4_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_IB_SUB_REMAIN +#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC4_PREEMPT +#define SDMA4_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC4_DUMMY_REG +#define SDMA4_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC4_RB_AQL_CNTL +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC4_MINOR_PTR_UPDATE +#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC4_MIDCMD_DATA0 +#define SDMA4_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA1 +#define SDMA4_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA2 +#define SDMA4_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA3 +#define SDMA4_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA4 +#define SDMA4_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA5 +#define SDMA4_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA6 +#define SDMA4_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA7 +#define SDMA4_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_DATA8 +#define SDMA4_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC4_MIDCMD_CNTL +#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC5_RB_CNTL +#define SDMA4_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC5_RB_BASE +#define SDMA4_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_BASE_HI +#define SDMA4_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC5_RB_RPTR +#define SDMA4_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_RPTR_HI +#define SDMA4_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR +#define SDMA4_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_HI +#define SDMA4_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_CNTL +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC5_RB_RPTR_ADDR_HI +#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_RPTR_ADDR_LO +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_IB_CNTL +#define SDMA4_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC5_IB_RPTR +#define SDMA4_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC5_IB_OFFSET +#define SDMA4_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC5_IB_BASE_LO +#define SDMA4_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC5_IB_BASE_HI +#define SDMA4_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_IB_SIZE +#define SDMA4_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC5_SKIP_CNTL +#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC5_CONTEXT_STATUS +#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC5_DOORBELL +#define SDMA4_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC5_STATUS +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC5_DOORBELL_LOG +#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC5_WATERMARK +#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC5_DOORBELL_OFFSET +#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC5_CSA_ADDR_LO +#define SDMA4_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_CSA_ADDR_HI +#define SDMA4_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_IB_SUB_REMAIN +#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC5_PREEMPT +#define SDMA4_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC5_DUMMY_REG +#define SDMA4_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC5_RB_AQL_CNTL +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC5_MINOR_PTR_UPDATE +#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC5_MIDCMD_DATA0 +#define SDMA4_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA1 +#define SDMA4_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA2 +#define SDMA4_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA3 +#define SDMA4_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA4 +#define SDMA4_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA5 +#define SDMA4_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA6 +#define SDMA4_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA7 +#define SDMA4_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_DATA8 +#define SDMA4_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC5_MIDCMD_CNTL +#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC6_RB_CNTL +#define SDMA4_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC6_RB_BASE +#define SDMA4_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_BASE_HI +#define SDMA4_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC6_RB_RPTR +#define SDMA4_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_RPTR_HI +#define SDMA4_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR +#define SDMA4_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_HI +#define SDMA4_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_CNTL +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC6_RB_RPTR_ADDR_HI +#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_RPTR_ADDR_LO +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_IB_CNTL +#define SDMA4_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC6_IB_RPTR +#define SDMA4_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC6_IB_OFFSET +#define SDMA4_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC6_IB_BASE_LO +#define SDMA4_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC6_IB_BASE_HI +#define SDMA4_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_IB_SIZE +#define SDMA4_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC6_SKIP_CNTL +#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC6_CONTEXT_STATUS +#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC6_DOORBELL +#define SDMA4_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC6_STATUS +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC6_DOORBELL_LOG +#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC6_WATERMARK +#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC6_DOORBELL_OFFSET +#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC6_CSA_ADDR_LO +#define SDMA4_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_CSA_ADDR_HI +#define SDMA4_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_IB_SUB_REMAIN +#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC6_PREEMPT +#define SDMA4_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC6_DUMMY_REG +#define SDMA4_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC6_RB_AQL_CNTL +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC6_MINOR_PTR_UPDATE +#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC6_MIDCMD_DATA0 +#define SDMA4_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA1 +#define SDMA4_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA2 +#define SDMA4_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA3 +#define SDMA4_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA4 +#define SDMA4_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA5 +#define SDMA4_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA6 +#define SDMA4_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA7 +#define SDMA4_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_DATA8 +#define SDMA4_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC6_MIDCMD_CNTL +#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA4_RLC7_RB_CNTL +#define SDMA4_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA4_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA4_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA4_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA4_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA4_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA4_RLC7_RB_BASE +#define SDMA4_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_BASE_HI +#define SDMA4_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA4_RLC7_RB_RPTR +#define SDMA4_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_RPTR_HI +#define SDMA4_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR +#define SDMA4_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_HI +#define SDMA4_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_CNTL +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA4_RLC7_RB_RPTR_ADDR_HI +#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_RPTR_ADDR_LO +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_IB_CNTL +#define SDMA4_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA4_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA4_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA4_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA4_RLC7_IB_RPTR +#define SDMA4_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC7_IB_OFFSET +#define SDMA4_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA4_RLC7_IB_BASE_LO +#define SDMA4_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA4_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA4_RLC7_IB_BASE_HI +#define SDMA4_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_IB_SIZE +#define SDMA4_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA4_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC7_SKIP_CNTL +#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA4_RLC7_CONTEXT_STATUS +#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA4_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA4_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA4_RLC7_DOORBELL +#define SDMA4_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA4_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA4_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA4_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA4_RLC7_STATUS +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA4_RLC7_DOORBELL_LOG +#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA4_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA4_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA4_RLC7_WATERMARK +#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA4_RLC7_DOORBELL_OFFSET +#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA4_RLC7_CSA_ADDR_LO +#define SDMA4_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_CSA_ADDR_HI +#define SDMA4_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_IB_SUB_REMAIN +#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA4_RLC7_PREEMPT +#define SDMA4_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA4_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA4_RLC7_DUMMY_REG +#define SDMA4_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA4_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA4_RLC7_RB_AQL_CNTL +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA4_RLC7_MINOR_PTR_UPDATE +#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA4_RLC7_MIDCMD_DATA0 +#define SDMA4_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA1 +#define SDMA4_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA2 +#define SDMA4_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA3 +#define SDMA4_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA4 +#define SDMA4_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA5 +#define SDMA4_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA6 +#define SDMA4_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA7 +#define SDMA4_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_DATA8 +#define SDMA4_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA4_RLC7_MIDCMD_CNTL +#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h new file mode 100644 index 000000000000..ecb51b9f90b0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma5_4_2_2_OFFSET_HEADER +#define _sdma5_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma5_sdma5dec +// base address: 0x7b000 +#define mmSDMA5_UCODE_ADDR 0x0000 +#define mmSDMA5_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA5_UCODE_DATA 0x0001 +#define mmSDMA5_UCODE_DATA_BASE_IDX 1 +#define mmSDMA5_VM_CNTL 0x0004 +#define mmSDMA5_VM_CNTL_BASE_IDX 1 +#define mmSDMA5_VM_CTX_LO 0x0005 +#define mmSDMA5_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA5_VM_CTX_HI 0x0006 +#define mmSDMA5_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA5_ACTIVE_FCN_ID 0x0007 +#define mmSDMA5_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA5_VM_CTX_CNTL 0x0008 +#define mmSDMA5_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA5_VIRT_RESET_REQ 0x0009 +#define mmSDMA5_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA5_VF_ENABLE 0x000a +#define mmSDMA5_VF_ENABLE_BASE_IDX 1 +#define mmSDMA5_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA5_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA5_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA5_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA5_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA5_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA5_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA5_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA5_PUB_REG_TYPE0 0x000f +#define mmSDMA5_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA5_PUB_REG_TYPE1 0x0010 +#define mmSDMA5_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA5_PUB_REG_TYPE2 0x0011 +#define mmSDMA5_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA5_PUB_REG_TYPE3 0x0012 +#define mmSDMA5_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA5_MMHUB_CNTL 0x0013 +#define mmSDMA5_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA5_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA5_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA5_POWER_CNTL 0x001a +#define mmSDMA5_POWER_CNTL_BASE_IDX 1 +#define mmSDMA5_CLK_CTRL 0x001b +#define mmSDMA5_CLK_CTRL_BASE_IDX 1 +#define mmSDMA5_CNTL 0x001c +#define mmSDMA5_CNTL_BASE_IDX 1 +#define mmSDMA5_CHICKEN_BITS 0x001d +#define mmSDMA5_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA5_GB_ADDR_CONFIG 0x001e +#define mmSDMA5_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA5_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA5_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA5_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA5_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA5_RB_RPTR_FETCH 0x0022 +#define mmSDMA5_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA5_IB_OFFSET_FETCH 0x0023 +#define mmSDMA5_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA5_PROGRAM 0x0024 +#define mmSDMA5_PROGRAM_BASE_IDX 1 +#define mmSDMA5_STATUS_REG 0x0025 +#define mmSDMA5_STATUS_REG_BASE_IDX 1 +#define mmSDMA5_STATUS1_REG 0x0026 +#define mmSDMA5_STATUS1_REG_BASE_IDX 1 +#define mmSDMA5_RD_BURST_CNTL 0x0027 +#define mmSDMA5_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA5_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA5_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA5_UCODE_CHECKSUM 0x0029 +#define mmSDMA5_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA5_F32_CNTL 0x002a +#define mmSDMA5_F32_CNTL_BASE_IDX 1 +#define mmSDMA5_FREEZE 0x002b +#define mmSDMA5_FREEZE_BASE_IDX 1 +#define mmSDMA5_PHASE0_QUANTUM 0x002c +#define mmSDMA5_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA5_PHASE1_QUANTUM 0x002d +#define mmSDMA5_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA5_EDC_CONFIG 0x0032 +#define mmSDMA5_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA5_BA_THRESHOLD 0x0033 +#define mmSDMA5_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA5_ID 0x0034 +#define mmSDMA5_ID_BASE_IDX 1 +#define mmSDMA5_VERSION 0x0035 +#define mmSDMA5_VERSION_BASE_IDX 1 +#define mmSDMA5_EDC_COUNTER 0x0036 +#define mmSDMA5_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA5_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA5_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA5_STATUS2_REG 0x0038 +#define mmSDMA5_STATUS2_REG_BASE_IDX 1 +#define mmSDMA5_ATOMIC_CNTL 0x0039 +#define mmSDMA5_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA5_ATOMIC_PREOP_LO 0x003a +#define mmSDMA5_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA5_ATOMIC_PREOP_HI 0x003b +#define mmSDMA5_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA5_UTCL1_CNTL 0x003c +#define mmSDMA5_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA5_UTCL1_WATERMK 0x003d +#define mmSDMA5_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA5_UTCL1_RD_STATUS 0x003e +#define mmSDMA5_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA5_UTCL1_WR_STATUS 0x003f +#define mmSDMA5_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA5_UTCL1_INV0 0x0040 +#define mmSDMA5_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA5_UTCL1_INV1 0x0041 +#define mmSDMA5_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA5_UTCL1_INV2 0x0042 +#define mmSDMA5_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA5_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA5_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA5_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA5_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA5_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA5_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA5_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA5_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA5_UTCL1_TIMEOUT 0x0047 +#define mmSDMA5_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA5_UTCL1_PAGE 0x0048 +#define mmSDMA5_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA5_POWER_CNTL_IDLE 0x0049 +#define mmSDMA5_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA5_RELAX_ORDERING_LUT 0x004a +#define mmSDMA5_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA5_CHICKEN_BITS_2 0x004b +#define mmSDMA5_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA5_STATUS3_REG 0x004c +#define mmSDMA5_STATUS3_REG_BASE_IDX 1 +#define mmSDMA5_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA5_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA5_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_PHASE2_QUANTUM 0x004f +#define mmSDMA5_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA5_ERROR_LOG 0x0050 +#define mmSDMA5_ERROR_LOG_BASE_IDX 1 +#define mmSDMA5_PUB_DUMMY_REG0 0x0051 +#define mmSDMA5_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA5_PUB_DUMMY_REG1 0x0052 +#define mmSDMA5_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA5_PUB_DUMMY_REG2 0x0053 +#define mmSDMA5_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA5_PUB_DUMMY_REG3 0x0054 +#define mmSDMA5_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA5_F32_COUNTER 0x0055 +#define mmSDMA5_F32_COUNTER_BASE_IDX 1 +#define mmSDMA5_UNBREAKABLE 0x0056 +#define mmSDMA5_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA5_PERFMON_CNTL 0x0057 +#define mmSDMA5_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA5_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA5_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA5_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA5_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA5_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA5_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA5_CRD_CNTL 0x005b +#define mmSDMA5_CRD_CNTL_BASE_IDX 1 +#define mmSDMA5_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA5_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA5_ULV_CNTL 0x005e +#define mmSDMA5_ULV_CNTL_BASE_IDX 1 +#define mmSDMA5_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA5_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA5_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA5_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA5_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA5_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA5_GFX_RB_CNTL 0x0080 +#define mmSDMA5_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_RB_BASE 0x0081 +#define mmSDMA5_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA5_GFX_RB_BASE_HI 0x0082 +#define mmSDMA5_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_RPTR 0x0083 +#define mmSDMA5_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA5_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR 0x0085 +#define mmSDMA5_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA5_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA5_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA5_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA5_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_GFX_IB_CNTL 0x008a +#define mmSDMA5_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_IB_RPTR 0x008b +#define mmSDMA5_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_GFX_IB_OFFSET 0x008c +#define mmSDMA5_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_GFX_IB_BASE_LO 0x008d +#define mmSDMA5_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_GFX_IB_BASE_HI 0x008e +#define mmSDMA5_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_GFX_IB_SIZE 0x008f +#define mmSDMA5_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_GFX_SKIP_CNTL 0x0090 +#define mmSDMA5_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA5_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_GFX_DOORBELL 0x0092 +#define mmSDMA5_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA5_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA5_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_STATUS 0x00a8 +#define mmSDMA5_GFX_STATUS_BASE_IDX 1 +#define mmSDMA5_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA5_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_GFX_WATERMARK 0x00aa +#define mmSDMA5_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA5_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA5_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA5_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA5_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA5_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_GFX_PREEMPT 0x00b0 +#define mmSDMA5_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA5_GFX_DUMMY_REG 0x00b1 +#define mmSDMA5_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA5_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA5_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA5_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA5_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA5_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA5_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA5_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA5_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA5_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA5_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA5_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA5_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_CNTL 0x00d8 +#define mmSDMA5_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_BASE 0x00d9 +#define mmSDMA5_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_BASE_HI 0x00da +#define mmSDMA5_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_RPTR 0x00db +#define mmSDMA5_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA5_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR 0x00dd +#define mmSDMA5_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA5_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA5_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA5_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA5_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_CNTL 0x00e2 +#define mmSDMA5_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_RPTR 0x00e3 +#define mmSDMA5_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA5_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA5_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA5_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_SIZE 0x00e7 +#define mmSDMA5_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA5_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA5_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_PAGE_DOORBELL 0x00ea +#define mmSDMA5_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA5_PAGE_STATUS 0x0100 +#define mmSDMA5_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA5_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA5_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_PAGE_WATERMARK 0x0102 +#define mmSDMA5_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA5_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA5_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA5_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA5_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA5_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_PAGE_PREEMPT 0x0108 +#define mmSDMA5_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA5_PAGE_DUMMY_REG 0x0109 +#define mmSDMA5_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA5_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA5_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA5_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA5_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA5_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA5_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA5_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA5_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA5_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA5_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA5_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA5_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_CNTL 0x0130 +#define mmSDMA5_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_BASE 0x0131 +#define mmSDMA5_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA5_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_RPTR 0x0133 +#define mmSDMA5_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA5_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR 0x0135 +#define mmSDMA5_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA5_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA5_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA5_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA5_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_CNTL 0x013a +#define mmSDMA5_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_RPTR 0x013b +#define mmSDMA5_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_OFFSET 0x013c +#define mmSDMA5_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_BASE_LO 0x013d +#define mmSDMA5_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_BASE_HI 0x013e +#define mmSDMA5_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_SIZE 0x013f +#define mmSDMA5_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA5_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA5_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC0_DOORBELL 0x0142 +#define mmSDMA5_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC0_STATUS 0x0158 +#define mmSDMA5_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA5_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC0_WATERMARK 0x015a +#define mmSDMA5_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA5_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA5_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA5_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA5_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC0_PREEMPT 0x0160 +#define mmSDMA5_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC0_DUMMY_REG 0x0161 +#define mmSDMA5_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA5_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA5_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA5_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA5_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA5_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA5_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA5_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA5_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA5_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA5_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA5_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA5_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_CNTL 0x0188 +#define mmSDMA5_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_BASE 0x0189 +#define mmSDMA5_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_BASE_HI 0x018a +#define mmSDMA5_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_RPTR 0x018b +#define mmSDMA5_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA5_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR 0x018d +#define mmSDMA5_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA5_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA5_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA5_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA5_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_CNTL 0x0192 +#define mmSDMA5_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_RPTR 0x0193 +#define mmSDMA5_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_OFFSET 0x0194 +#define mmSDMA5_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA5_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA5_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_SIZE 0x0197 +#define mmSDMA5_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA5_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA5_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC1_DOORBELL 0x019a +#define mmSDMA5_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC1_STATUS 0x01b0 +#define mmSDMA5_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA5_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC1_WATERMARK 0x01b2 +#define mmSDMA5_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA5_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA5_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA5_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA5_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC1_PREEMPT 0x01b8 +#define mmSDMA5_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA5_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA5_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA5_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA5_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA5_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA5_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA5_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA5_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA5_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA5_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA5_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA5_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA5_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_CNTL 0x01e0 +#define mmSDMA5_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_BASE 0x01e1 +#define mmSDMA5_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA5_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_RPTR 0x01e3 +#define mmSDMA5_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA5_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR 0x01e5 +#define mmSDMA5_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA5_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA5_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA5_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA5_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_CNTL 0x01ea +#define mmSDMA5_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_RPTR 0x01eb +#define mmSDMA5_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_OFFSET 0x01ec +#define mmSDMA5_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA5_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA5_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_SIZE 0x01ef +#define mmSDMA5_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA5_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA5_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC2_DOORBELL 0x01f2 +#define mmSDMA5_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC2_STATUS 0x0208 +#define mmSDMA5_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA5_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC2_WATERMARK 0x020a +#define mmSDMA5_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA5_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA5_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA5_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA5_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC2_PREEMPT 0x0210 +#define mmSDMA5_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC2_DUMMY_REG 0x0211 +#define mmSDMA5_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA5_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA5_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA5_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA5_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA5_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA5_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA5_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA5_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA5_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA5_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA5_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA5_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_CNTL 0x0238 +#define mmSDMA5_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_BASE 0x0239 +#define mmSDMA5_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_BASE_HI 0x023a +#define mmSDMA5_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_RPTR 0x023b +#define mmSDMA5_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA5_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR 0x023d +#define mmSDMA5_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA5_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA5_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA5_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA5_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_CNTL 0x0242 +#define mmSDMA5_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_RPTR 0x0243 +#define mmSDMA5_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_OFFSET 0x0244 +#define mmSDMA5_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA5_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA5_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_SIZE 0x0247 +#define mmSDMA5_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA5_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA5_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC3_DOORBELL 0x024a +#define mmSDMA5_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC3_STATUS 0x0260 +#define mmSDMA5_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA5_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC3_WATERMARK 0x0262 +#define mmSDMA5_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA5_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA5_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA5_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA5_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC3_PREEMPT 0x0268 +#define mmSDMA5_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC3_DUMMY_REG 0x0269 +#define mmSDMA5_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA5_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA5_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA5_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA5_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA5_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA5_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA5_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA5_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA5_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA5_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA5_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA5_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_CNTL 0x0290 +#define mmSDMA5_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_BASE 0x0291 +#define mmSDMA5_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA5_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_RPTR 0x0293 +#define mmSDMA5_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA5_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR 0x0295 +#define mmSDMA5_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA5_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA5_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA5_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA5_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_CNTL 0x029a +#define mmSDMA5_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_RPTR 0x029b +#define mmSDMA5_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_OFFSET 0x029c +#define mmSDMA5_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_BASE_LO 0x029d +#define mmSDMA5_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_BASE_HI 0x029e +#define mmSDMA5_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_SIZE 0x029f +#define mmSDMA5_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA5_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA5_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC4_DOORBELL 0x02a2 +#define mmSDMA5_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC4_STATUS 0x02b8 +#define mmSDMA5_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA5_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC4_WATERMARK 0x02ba +#define mmSDMA5_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA5_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA5_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA5_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA5_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC4_PREEMPT 0x02c0 +#define mmSDMA5_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA5_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA5_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA5_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA5_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA5_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA5_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA5_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA5_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA5_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA5_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA5_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA5_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA5_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_CNTL 0x02e8 +#define mmSDMA5_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_BASE 0x02e9 +#define mmSDMA5_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA5_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_RPTR 0x02eb +#define mmSDMA5_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA5_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR 0x02ed +#define mmSDMA5_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA5_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA5_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA5_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA5_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_CNTL 0x02f2 +#define mmSDMA5_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_RPTR 0x02f3 +#define mmSDMA5_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA5_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA5_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA5_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_SIZE 0x02f7 +#define mmSDMA5_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA5_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA5_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC5_DOORBELL 0x02fa +#define mmSDMA5_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC5_STATUS 0x0310 +#define mmSDMA5_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA5_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC5_WATERMARK 0x0312 +#define mmSDMA5_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA5_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA5_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA5_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA5_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC5_PREEMPT 0x0318 +#define mmSDMA5_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC5_DUMMY_REG 0x0319 +#define mmSDMA5_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA5_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA5_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA5_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA5_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA5_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA5_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA5_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA5_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA5_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA5_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA5_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA5_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_CNTL 0x0340 +#define mmSDMA5_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_BASE 0x0341 +#define mmSDMA5_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA5_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_RPTR 0x0343 +#define mmSDMA5_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA5_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR 0x0345 +#define mmSDMA5_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA5_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA5_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA5_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA5_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_CNTL 0x034a +#define mmSDMA5_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_RPTR 0x034b +#define mmSDMA5_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_OFFSET 0x034c +#define mmSDMA5_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_BASE_LO 0x034d +#define mmSDMA5_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_BASE_HI 0x034e +#define mmSDMA5_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_SIZE 0x034f +#define mmSDMA5_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA5_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA5_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC6_DOORBELL 0x0352 +#define mmSDMA5_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC6_STATUS 0x0368 +#define mmSDMA5_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA5_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC6_WATERMARK 0x036a +#define mmSDMA5_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA5_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA5_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA5_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA5_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC6_PREEMPT 0x0370 +#define mmSDMA5_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC6_DUMMY_REG 0x0371 +#define mmSDMA5_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA5_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA5_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA5_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA5_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA5_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA5_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA5_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA5_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA5_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA5_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA5_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA5_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_CNTL 0x0398 +#define mmSDMA5_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_BASE 0x0399 +#define mmSDMA5_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_BASE_HI 0x039a +#define mmSDMA5_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_RPTR 0x039b +#define mmSDMA5_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA5_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR 0x039d +#define mmSDMA5_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA5_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA5_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA5_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA5_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_CNTL 0x03a2 +#define mmSDMA5_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_RPTR 0x03a3 +#define mmSDMA5_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA5_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA5_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA5_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_SIZE 0x03a7 +#define mmSDMA5_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA5_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA5_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA5_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC7_DOORBELL 0x03aa +#define mmSDMA5_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA5_RLC7_STATUS 0x03c0 +#define mmSDMA5_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA5_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA5_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA5_RLC7_WATERMARK 0x03c2 +#define mmSDMA5_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA5_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA5_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA5_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA5_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA5_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA5_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA5_RLC7_PREEMPT 0x03c8 +#define mmSDMA5_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA5_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA5_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA5_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA5_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA5_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA5_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA5_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA5_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA5_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA5_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA5_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA5_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA5_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA5_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA5_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA5_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA5_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h new file mode 100644 index 000000000000..e99856b92386 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma5_4_2_2_SH_MASK_HEADER +#define _sdma5_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma5_sdma5dec +//SDMA5_UCODE_ADDR +#define SDMA5_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA5_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA5_UCODE_DATA +#define SDMA5_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA5_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA5_VM_CNTL +#define SDMA5_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA5_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA5_VM_CTX_LO +#define SDMA5_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA5_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_VM_CTX_HI +#define SDMA5_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA5_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_ACTIVE_FCN_ID +#define SDMA5_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA5_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA5_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA5_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA5_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA5_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA5_VM_CTX_CNTL +#define SDMA5_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA5_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA5_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA5_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA5_VIRT_RESET_REQ +#define SDMA5_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA5_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA5_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA5_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA5_VF_ENABLE +#define SDMA5_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA5_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA5_CONTEXT_REG_TYPE0 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE__SHIFT 0x1 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL__SHIFT 0xa +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_RPTR__SHIFT 0xb +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_SIZE__SHIFT 0xf +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_DOORBELL__SHIFT 0x12 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_MASK 0x00000002L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_DOORBELL_MASK 0x00040000L +#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA5_CONTEXT_REG_TYPE1 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_STATUS__SHIFT 0x8 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK__SHIFT 0xa +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA5_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_PREEMPT__SHIFT 0x10 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA5_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_STATUS_MASK 0x00000100L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK_MASK 0x00000400L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA5_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_PREEMPT_MASK 0x00010000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA5_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA5_CONTEXT_REG_TYPE2 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA5_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA5_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA5_CONTEXT_REG_TYPE3 +#define SDMA5_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA5_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA5_PUB_REG_TYPE0 +#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_ADDR__SHIFT 0x0 +#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_DATA__SHIFT 0x1 +#define SDMA5_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CNTL__SHIFT 0x4 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_LO__SHIFT 0x5 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_HI__SHIFT 0x6 +#define SDMA5_PUB_REG_TYPE0__SDMA5_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA5_PUB_REG_TYPE0__SDMA5_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA5_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA5_PUB_REG_TYPE0__SDMA5_MMHUB_CNTL__SHIFT 0x13 +#define SDMA5_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA5_PUB_REG_TYPE0__SDMA5_POWER_CNTL__SHIFT 0x1a +#define SDMA5_PUB_REG_TYPE0__SDMA5_CLK_CTRL__SHIFT 0x1b +#define SDMA5_PUB_REG_TYPE0__SDMA5_CNTL__SHIFT 0x1c +#define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS__SHIFT 0x1d +#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_ADDR_MASK 0x00000001L +#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_DATA_MASK 0x00000002L +#define SDMA5_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CNTL_MASK 0x00000010L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_LO_MASK 0x00000020L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_HI_MASK 0x00000040L +#define SDMA5_PUB_REG_TYPE0__SDMA5_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA5_PUB_REG_TYPE0__SDMA5_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA5_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_MMHUB_CNTL_MASK 0x00080000L +#define SDMA5_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_POWER_CNTL_MASK 0x04000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CLK_CTRL_MASK 0x08000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CNTL_MASK 0x10000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS_MASK 0x20000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA5_PUB_REG_TYPE1 +#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA5_PUB_REG_TYPE1__SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA5_PUB_REG_TYPE1__SDMA5_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA5_PUB_REG_TYPE1__SDMA5_PROGRAM__SHIFT 0x4 +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS_REG__SHIFT 0x5 +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS1_REG__SHIFT 0x6 +#define SDMA5_PUB_REG_TYPE1__SDMA5_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA5_PUB_REG_TYPE1__SDMA5_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA5_PUB_REG_TYPE1__SDMA5_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL__SHIFT 0xa +#define SDMA5_PUB_REG_TYPE1__SDMA5_FREEZE__SHIFT 0xb +#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA5_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_CONFIG__SHIFT 0x12 +#define SDMA5_PUB_REG_TYPE1__SDMA5_BA_THRESHOLD__SHIFT 0x13 +#define SDMA5_PUB_REG_TYPE1__SDMA5_ID__SHIFT 0x14 +#define SDMA5_PUB_REG_TYPE1__SDMA5_VERSION__SHIFT 0x15 +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER__SHIFT 0x16 +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS2_REG__SHIFT 0x18 +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_CNTL__SHIFT 0x1c +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA5_PUB_REG_TYPE1__SDMA5_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA5_PUB_REG_TYPE1__SDMA5_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA5_PUB_REG_TYPE1__SDMA5_PROGRAM_MASK 0x00000010L +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS_REG_MASK 0x00000020L +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS1_REG_MASK 0x00000040L +#define SDMA5_PUB_REG_TYPE1__SDMA5_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA5_PUB_REG_TYPE1__SDMA5_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL_MASK 0x00000400L +#define SDMA5_PUB_REG_TYPE1__SDMA5_FREEZE_MASK 0x00000800L +#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA5_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_CONFIG_MASK 0x00040000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_BA_THRESHOLD_MASK 0x00080000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_ID_MASK 0x00100000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_VERSION_MASK 0x00200000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_MASK 0x00400000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS2_REG_MASK 0x01000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_CNTL_MASK 0x10000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA5_PUB_REG_TYPE2 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV0__SHIFT 0x0 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV1__SHIFT 0x1 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV2__SHIFT 0x2 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_PAGE__SHIFT 0x8 +#define SDMA5_PUB_REG_TYPE2__SDMA5_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA5_PUB_REG_TYPE2__SDMA5_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA5_PUB_REG_TYPE2__SDMA5_STATUS3_REG__SHIFT 0xc +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA5_PUB_REG_TYPE2__SDMA5_ERROR_LOG__SHIFT 0x10 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA5_PUB_REG_TYPE2__SDMA5_F32_COUNTER__SHIFT 0x15 +#define SDMA5_PUB_REG_TYPE2__SDMA5_UNBREAKABLE__SHIFT 0x16 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFMON_CNTL__SHIFT 0x17 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA5_PUB_REG_TYPE2__SDMA5_CRD_CNTL__SHIFT 0x1b +#define SDMA5_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA5_PUB_REG_TYPE2__SDMA5_ULV_CNTL__SHIFT 0x1e +#define SDMA5_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV0_MASK 0x00000001L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV1_MASK 0x00000002L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV2_MASK 0x00000004L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_PAGE_MASK 0x00000100L +#define SDMA5_PUB_REG_TYPE2__SDMA5_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA5_PUB_REG_TYPE2__SDMA5_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA5_PUB_REG_TYPE2__SDMA5_STATUS3_REG_MASK 0x00001000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_ERROR_LOG_MASK 0x00010000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_F32_COUNTER_MASK 0x00200000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_UNBREAKABLE_MASK 0x00400000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFMON_CNTL_MASK 0x00800000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_CRD_CNTL_MASK 0x08000000L +#define SDMA5_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA5_PUB_REG_TYPE2__SDMA5_ULV_CNTL_MASK 0x40000000L +#define SDMA5_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA5_PUB_REG_TYPE3 +#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA5_PUB_REG_TYPE3__SDMA5_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA5_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA5_PUB_REG_TYPE3__SDMA5_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA5_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA5_MMHUB_CNTL +#define SDMA5_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA5_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA5_CONTEXT_GROUP_BOUNDARY +#define SDMA5_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA5_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA5_POWER_CNTL +#define SDMA5_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA5_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA5_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA5_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA5_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA5_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA5_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA5_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA5_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA5_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA5_CLK_CTRL +#define SDMA5_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA5_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA5_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA5_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA5_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA5_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA5_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA5_CNTL +#define SDMA5_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA5_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA5_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA5_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA5_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA5_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA5_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA5_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA5_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA5_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA5_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA5_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA5_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA5_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA5_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA5_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA5_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA5_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA5_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA5_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA5_CHICKEN_BITS +#define SDMA5_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA5_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA5_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA5_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA5_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA5_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA5_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA5_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA5_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA5_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA5_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA5_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA5_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA5_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA5_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA5_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA5_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA5_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA5_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA5_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA5_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA5_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA5_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA5_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA5_GB_ADDR_CONFIG +#define SDMA5_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA5_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA5_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA5_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA5_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA5_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA5_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA5_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA5_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA5_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA5_GB_ADDR_CONFIG_READ +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA5_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA5_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA5_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA5_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA5_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA5_RB_RPTR_FETCH_HI +#define SDMA5_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA5_RB_RPTR_FETCH +#define SDMA5_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA5_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA5_IB_OFFSET_FETCH +#define SDMA5_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA5_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA5_PROGRAM +#define SDMA5_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA5_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA5_STATUS_REG +#define SDMA5_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA5_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA5_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA5_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA5_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA5_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA5_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA5_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA5_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA5_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA5_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA5_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA5_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA5_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA5_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA5_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA5_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA5_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA5_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA5_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA5_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA5_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA5_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA5_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA5_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA5_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA5_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA5_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA5_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA5_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA5_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA5_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA5_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA5_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA5_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA5_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA5_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA5_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA5_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA5_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA5_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA5_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA5_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA5_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA5_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA5_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA5_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA5_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA5_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA5_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA5_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA5_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA5_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA5_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA5_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA5_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA5_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA5_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA5_STATUS1_REG +#define SDMA5_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA5_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA5_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA5_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA5_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA5_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA5_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA5_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA5_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA5_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA5_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA5_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA5_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA5_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA5_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA5_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA5_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA5_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA5_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA5_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA5_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA5_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA5_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA5_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA5_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA5_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA5_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA5_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA5_RD_BURST_CNTL +#define SDMA5_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA5_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA5_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA5_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA5_HBM_PAGE_CONFIG +#define SDMA5_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA5_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA5_UCODE_CHECKSUM +#define SDMA5_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA5_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA5_F32_CNTL +#define SDMA5_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA5_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA5_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA5_F32_CNTL__STEP_MASK 0x00000002L +//SDMA5_FREEZE +#define SDMA5_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA5_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA5_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA5_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA5_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA5_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA5_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA5_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA5_PHASE0_QUANTUM +#define SDMA5_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA5_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA5_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA5_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA5_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA5_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA5_PHASE1_QUANTUM +#define SDMA5_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA5_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA5_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA5_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA5_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA5_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA5_EDC_CONFIG +#define SDMA5_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA5_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA5_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA5_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA5_BA_THRESHOLD +#define SDMA5_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA5_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA5_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA5_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA5_ID +#define SDMA5_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA5_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA5_VERSION +#define SDMA5_VERSION__MINVER__SHIFT 0x0 +#define SDMA5_VERSION__MAJVER__SHIFT 0x8 +#define SDMA5_VERSION__REV__SHIFT 0x10 +#define SDMA5_VERSION__MINVER_MASK 0x0000007FL +#define SDMA5_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA5_VERSION__REV_MASK 0x003F0000L +//SDMA5_EDC_COUNTER +#define SDMA5_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA5_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA5_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA5_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA5_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA5_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA5_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA5_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA5_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA5_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA5_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA5_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA5_EDC_COUNTER_CLEAR +#define SDMA5_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA5_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA5_STATUS2_REG +#define SDMA5_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA5_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA5_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA5_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA5_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA5_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA5_ATOMIC_CNTL +#define SDMA5_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA5_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA5_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA5_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA5_ATOMIC_PREOP_LO +#define SDMA5_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA5_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA5_ATOMIC_PREOP_HI +#define SDMA5_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA5_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_CNTL +#define SDMA5_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA5_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA5_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA5_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA5_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA5_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA5_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA5_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA5_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA5_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA5_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA5_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA5_UTCL1_WATERMK +#define SDMA5_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA5_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA5_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA5_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA5_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA5_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA5_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA5_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA5_UTCL1_RD_STATUS +#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA5_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA5_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA5_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA5_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA5_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA5_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA5_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA5_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA5_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA5_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA5_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA5_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA5_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA5_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA5_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA5_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA5_UTCL1_WR_STATUS +#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA5_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA5_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA5_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA5_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA5_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA5_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA5_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA5_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA5_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA5_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA5_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA5_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA5_UTCL1_INV0 +#define SDMA5_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA5_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA5_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA5_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA5_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA5_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA5_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA5_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA5_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA5_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA5_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA5_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA5_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA5_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA5_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA5_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA5_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA5_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA5_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA5_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA5_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA5_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA5_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA5_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA5_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA5_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA5_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA5_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA5_UTCL1_INV1 +#define SDMA5_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA5_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_INV2 +#define SDMA5_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA5_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_RD_XNACK0 +#define SDMA5_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA5_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_RD_XNACK1 +#define SDMA5_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA5_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA5_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA5_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA5_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA5_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA5_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA5_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA5_UTCL1_WR_XNACK0 +#define SDMA5_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA5_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA5_UTCL1_WR_XNACK1 +#define SDMA5_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA5_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA5_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA5_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA5_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA5_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA5_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA5_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA5_UTCL1_TIMEOUT +#define SDMA5_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA5_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA5_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA5_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA5_UTCL1_PAGE +#define SDMA5_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA5_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA5_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA5_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA5_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA5_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA5_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA5_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA5_POWER_CNTL_IDLE +#define SDMA5_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA5_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA5_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA5_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA5_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA5_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA5_RELAX_ORDERING_LUT +#define SDMA5_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA5_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA5_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA5_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA5_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA5_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA5_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA5_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA5_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA5_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA5_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA5_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA5_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA5_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA5_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA5_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA5_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA5_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA5_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA5_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA5_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA5_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA5_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA5_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA5_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA5_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA5_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA5_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA5_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA5_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA5_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA5_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA5_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA5_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA5_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA5_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA5_CHICKEN_BITS_2 +#define SDMA5_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA5_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA5_STATUS3_REG +#define SDMA5_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA5_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA5_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA5_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA5_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA5_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA5_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA5_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA5_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA5_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA5_PHYSICAL_ADDR_LO +#define SDMA5_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA5_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA5_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA5_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA5_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA5_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA5_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA5_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA5_PHYSICAL_ADDR_HI +#define SDMA5_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA5_PHASE2_QUANTUM +#define SDMA5_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA5_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA5_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA5_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA5_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA5_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA5_ERROR_LOG +#define SDMA5_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA5_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA5_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA5_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA5_PUB_DUMMY_REG0 +#define SDMA5_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA5_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA5_PUB_DUMMY_REG1 +#define SDMA5_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA5_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA5_PUB_DUMMY_REG2 +#define SDMA5_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA5_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA5_PUB_DUMMY_REG3 +#define SDMA5_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA5_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA5_F32_COUNTER +#define SDMA5_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA5_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA5_UNBREAKABLE +#define SDMA5_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA5_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA5_PERFMON_CNTL +#define SDMA5_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA5_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA5_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA5_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA5_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA5_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA5_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA5_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA5_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA5_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA5_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA5_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA5_PERFCOUNTER0_RESULT +#define SDMA5_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA5_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA5_PERFCOUNTER1_RESULT +#define SDMA5_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA5_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA5_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA5_CRD_CNTL +#define SDMA5_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA5_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA5_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA5_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA5_GPU_IOV_VIOLATION_LOG +#define SDMA5_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA5_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA5_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA5_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA5_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA5_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA5_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA5_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA5_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA5_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA5_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA5_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA5_ULV_CNTL +#define SDMA5_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA5_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA5_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA5_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA5_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA5_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA5_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA5_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA5_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA5_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA5_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA5_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA5_EA_DBIT_ADDR_DATA +#define SDMA5_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA5_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA5_EA_DBIT_ADDR_INDEX +#define SDMA5_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA5_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA5_GPU_IOV_VIOLATION_LOG2 +#define SDMA5_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA5_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA5_GFX_RB_CNTL +#define SDMA5_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_GFX_RB_BASE +#define SDMA5_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_BASE_HI +#define SDMA5_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_GFX_RB_RPTR +#define SDMA5_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_RPTR_HI +#define SDMA5_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR +#define SDMA5_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR_HI +#define SDMA5_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR_POLL_CNTL +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_GFX_RB_RPTR_ADDR_HI +#define SDMA5_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_RPTR_ADDR_LO +#define SDMA5_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_GFX_IB_CNTL +#define SDMA5_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_GFX_IB_RPTR +#define SDMA5_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_GFX_IB_OFFSET +#define SDMA5_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_GFX_IB_BASE_LO +#define SDMA5_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_GFX_IB_BASE_HI +#define SDMA5_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_IB_SIZE +#define SDMA5_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_GFX_SKIP_CNTL +#define SDMA5_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_GFX_CONTEXT_STATUS +#define SDMA5_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_GFX_DOORBELL +#define SDMA5_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_GFX_CONTEXT_CNTL +#define SDMA5_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA5_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA5_GFX_STATUS +#define SDMA5_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_GFX_DOORBELL_LOG +#define SDMA5_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_GFX_WATERMARK +#define SDMA5_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_GFX_DOORBELL_OFFSET +#define SDMA5_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_GFX_CSA_ADDR_LO +#define SDMA5_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_GFX_CSA_ADDR_HI +#define SDMA5_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_IB_SUB_REMAIN +#define SDMA5_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_GFX_PREEMPT +#define SDMA5_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_GFX_DUMMY_REG +#define SDMA5_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_GFX_RB_AQL_CNTL +#define SDMA5_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_GFX_MINOR_PTR_UPDATE +#define SDMA5_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_GFX_MIDCMD_DATA0 +#define SDMA5_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA1 +#define SDMA5_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA2 +#define SDMA5_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA3 +#define SDMA5_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA4 +#define SDMA5_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA5 +#define SDMA5_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA6 +#define SDMA5_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA7 +#define SDMA5_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_DATA8 +#define SDMA5_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_GFX_MIDCMD_CNTL +#define SDMA5_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_PAGE_RB_CNTL +#define SDMA5_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_PAGE_RB_BASE +#define SDMA5_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_BASE_HI +#define SDMA5_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_PAGE_RB_RPTR +#define SDMA5_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_RPTR_HI +#define SDMA5_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR +#define SDMA5_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR_HI +#define SDMA5_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR_POLL_CNTL +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_PAGE_RB_RPTR_ADDR_HI +#define SDMA5_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_RPTR_ADDR_LO +#define SDMA5_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_PAGE_IB_CNTL +#define SDMA5_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_PAGE_IB_RPTR +#define SDMA5_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_PAGE_IB_OFFSET +#define SDMA5_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_PAGE_IB_BASE_LO +#define SDMA5_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_PAGE_IB_BASE_HI +#define SDMA5_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_IB_SIZE +#define SDMA5_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_PAGE_SKIP_CNTL +#define SDMA5_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_PAGE_CONTEXT_STATUS +#define SDMA5_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_PAGE_DOORBELL +#define SDMA5_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_PAGE_STATUS +#define SDMA5_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_PAGE_DOORBELL_LOG +#define SDMA5_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_PAGE_WATERMARK +#define SDMA5_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_PAGE_DOORBELL_OFFSET +#define SDMA5_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_PAGE_CSA_ADDR_LO +#define SDMA5_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_PAGE_CSA_ADDR_HI +#define SDMA5_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_IB_SUB_REMAIN +#define SDMA5_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_PAGE_PREEMPT +#define SDMA5_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_PAGE_DUMMY_REG +#define SDMA5_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_PAGE_RB_AQL_CNTL +#define SDMA5_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_PAGE_MINOR_PTR_UPDATE +#define SDMA5_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_PAGE_MIDCMD_DATA0 +#define SDMA5_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA1 +#define SDMA5_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA2 +#define SDMA5_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA3 +#define SDMA5_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA4 +#define SDMA5_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA5 +#define SDMA5_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA6 +#define SDMA5_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA7 +#define SDMA5_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_DATA8 +#define SDMA5_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_PAGE_MIDCMD_CNTL +#define SDMA5_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC0_RB_CNTL +#define SDMA5_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC0_RB_BASE +#define SDMA5_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_BASE_HI +#define SDMA5_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC0_RB_RPTR +#define SDMA5_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_RPTR_HI +#define SDMA5_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR +#define SDMA5_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR_HI +#define SDMA5_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR_POLL_CNTL +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC0_RB_RPTR_ADDR_HI +#define SDMA5_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_RPTR_ADDR_LO +#define SDMA5_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC0_IB_CNTL +#define SDMA5_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC0_IB_RPTR +#define SDMA5_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC0_IB_OFFSET +#define SDMA5_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC0_IB_BASE_LO +#define SDMA5_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC0_IB_BASE_HI +#define SDMA5_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_IB_SIZE +#define SDMA5_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC0_SKIP_CNTL +#define SDMA5_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC0_CONTEXT_STATUS +#define SDMA5_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC0_DOORBELL +#define SDMA5_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC0_STATUS +#define SDMA5_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC0_DOORBELL_LOG +#define SDMA5_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC0_WATERMARK +#define SDMA5_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC0_DOORBELL_OFFSET +#define SDMA5_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC0_CSA_ADDR_LO +#define SDMA5_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC0_CSA_ADDR_HI +#define SDMA5_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_IB_SUB_REMAIN +#define SDMA5_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC0_PREEMPT +#define SDMA5_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC0_DUMMY_REG +#define SDMA5_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC0_RB_AQL_CNTL +#define SDMA5_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC0_MINOR_PTR_UPDATE +#define SDMA5_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC0_MIDCMD_DATA0 +#define SDMA5_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA1 +#define SDMA5_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA2 +#define SDMA5_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA3 +#define SDMA5_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA4 +#define SDMA5_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA5 +#define SDMA5_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA6 +#define SDMA5_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA7 +#define SDMA5_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_DATA8 +#define SDMA5_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC0_MIDCMD_CNTL +#define SDMA5_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC1_RB_CNTL +#define SDMA5_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC1_RB_BASE +#define SDMA5_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_BASE_HI +#define SDMA5_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC1_RB_RPTR +#define SDMA5_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_RPTR_HI +#define SDMA5_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR +#define SDMA5_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR_HI +#define SDMA5_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR_POLL_CNTL +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC1_RB_RPTR_ADDR_HI +#define SDMA5_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_RPTR_ADDR_LO +#define SDMA5_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC1_IB_CNTL +#define SDMA5_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC1_IB_RPTR +#define SDMA5_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC1_IB_OFFSET +#define SDMA5_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC1_IB_BASE_LO +#define SDMA5_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC1_IB_BASE_HI +#define SDMA5_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_IB_SIZE +#define SDMA5_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC1_SKIP_CNTL +#define SDMA5_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC1_CONTEXT_STATUS +#define SDMA5_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC1_DOORBELL +#define SDMA5_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC1_STATUS +#define SDMA5_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC1_DOORBELL_LOG +#define SDMA5_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC1_WATERMARK +#define SDMA5_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC1_DOORBELL_OFFSET +#define SDMA5_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC1_CSA_ADDR_LO +#define SDMA5_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC1_CSA_ADDR_HI +#define SDMA5_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_IB_SUB_REMAIN +#define SDMA5_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC1_PREEMPT +#define SDMA5_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC1_DUMMY_REG +#define SDMA5_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC1_RB_AQL_CNTL +#define SDMA5_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC1_MINOR_PTR_UPDATE +#define SDMA5_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC1_MIDCMD_DATA0 +#define SDMA5_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA1 +#define SDMA5_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA2 +#define SDMA5_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA3 +#define SDMA5_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA4 +#define SDMA5_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA5 +#define SDMA5_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA6 +#define SDMA5_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA7 +#define SDMA5_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_DATA8 +#define SDMA5_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC1_MIDCMD_CNTL +#define SDMA5_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC2_RB_CNTL +#define SDMA5_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC2_RB_BASE +#define SDMA5_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_BASE_HI +#define SDMA5_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC2_RB_RPTR +#define SDMA5_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_RPTR_HI +#define SDMA5_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR +#define SDMA5_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR_HI +#define SDMA5_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR_POLL_CNTL +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC2_RB_RPTR_ADDR_HI +#define SDMA5_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_RPTR_ADDR_LO +#define SDMA5_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC2_IB_CNTL +#define SDMA5_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC2_IB_RPTR +#define SDMA5_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC2_IB_OFFSET +#define SDMA5_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC2_IB_BASE_LO +#define SDMA5_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC2_IB_BASE_HI +#define SDMA5_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_IB_SIZE +#define SDMA5_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC2_SKIP_CNTL +#define SDMA5_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC2_CONTEXT_STATUS +#define SDMA5_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC2_DOORBELL +#define SDMA5_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC2_STATUS +#define SDMA5_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC2_DOORBELL_LOG +#define SDMA5_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC2_WATERMARK +#define SDMA5_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC2_DOORBELL_OFFSET +#define SDMA5_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC2_CSA_ADDR_LO +#define SDMA5_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC2_CSA_ADDR_HI +#define SDMA5_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_IB_SUB_REMAIN +#define SDMA5_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC2_PREEMPT +#define SDMA5_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC2_DUMMY_REG +#define SDMA5_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC2_RB_AQL_CNTL +#define SDMA5_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC2_MINOR_PTR_UPDATE +#define SDMA5_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC2_MIDCMD_DATA0 +#define SDMA5_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA1 +#define SDMA5_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA2 +#define SDMA5_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA3 +#define SDMA5_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA4 +#define SDMA5_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA5 +#define SDMA5_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA6 +#define SDMA5_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA7 +#define SDMA5_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_DATA8 +#define SDMA5_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC2_MIDCMD_CNTL +#define SDMA5_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC3_RB_CNTL +#define SDMA5_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC3_RB_BASE +#define SDMA5_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_BASE_HI +#define SDMA5_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC3_RB_RPTR +#define SDMA5_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_RPTR_HI +#define SDMA5_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR +#define SDMA5_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR_HI +#define SDMA5_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR_POLL_CNTL +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC3_RB_RPTR_ADDR_HI +#define SDMA5_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_RPTR_ADDR_LO +#define SDMA5_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC3_IB_CNTL +#define SDMA5_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC3_IB_RPTR +#define SDMA5_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC3_IB_OFFSET +#define SDMA5_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC3_IB_BASE_LO +#define SDMA5_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC3_IB_BASE_HI +#define SDMA5_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_IB_SIZE +#define SDMA5_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC3_SKIP_CNTL +#define SDMA5_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC3_CONTEXT_STATUS +#define SDMA5_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC3_DOORBELL +#define SDMA5_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC3_STATUS +#define SDMA5_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC3_DOORBELL_LOG +#define SDMA5_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC3_WATERMARK +#define SDMA5_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC3_DOORBELL_OFFSET +#define SDMA5_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC3_CSA_ADDR_LO +#define SDMA5_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC3_CSA_ADDR_HI +#define SDMA5_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_IB_SUB_REMAIN +#define SDMA5_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC3_PREEMPT +#define SDMA5_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC3_DUMMY_REG +#define SDMA5_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC3_RB_AQL_CNTL +#define SDMA5_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC3_MINOR_PTR_UPDATE +#define SDMA5_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC3_MIDCMD_DATA0 +#define SDMA5_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA1 +#define SDMA5_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA2 +#define SDMA5_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA3 +#define SDMA5_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA4 +#define SDMA5_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA5 +#define SDMA5_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA6 +#define SDMA5_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA7 +#define SDMA5_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_DATA8 +#define SDMA5_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC3_MIDCMD_CNTL +#define SDMA5_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC4_RB_CNTL +#define SDMA5_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC4_RB_BASE +#define SDMA5_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_BASE_HI +#define SDMA5_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC4_RB_RPTR +#define SDMA5_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_RPTR_HI +#define SDMA5_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR +#define SDMA5_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR_HI +#define SDMA5_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR_POLL_CNTL +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC4_RB_RPTR_ADDR_HI +#define SDMA5_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_RPTR_ADDR_LO +#define SDMA5_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC4_IB_CNTL +#define SDMA5_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC4_IB_RPTR +#define SDMA5_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC4_IB_OFFSET +#define SDMA5_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC4_IB_BASE_LO +#define SDMA5_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC4_IB_BASE_HI +#define SDMA5_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_IB_SIZE +#define SDMA5_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC4_SKIP_CNTL +#define SDMA5_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC4_CONTEXT_STATUS +#define SDMA5_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC4_DOORBELL +#define SDMA5_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC4_STATUS +#define SDMA5_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC4_DOORBELL_LOG +#define SDMA5_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC4_WATERMARK +#define SDMA5_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC4_DOORBELL_OFFSET +#define SDMA5_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC4_CSA_ADDR_LO +#define SDMA5_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC4_CSA_ADDR_HI +#define SDMA5_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_IB_SUB_REMAIN +#define SDMA5_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC4_PREEMPT +#define SDMA5_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC4_DUMMY_REG +#define SDMA5_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC4_RB_AQL_CNTL +#define SDMA5_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC4_MINOR_PTR_UPDATE +#define SDMA5_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC4_MIDCMD_DATA0 +#define SDMA5_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA1 +#define SDMA5_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA2 +#define SDMA5_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA3 +#define SDMA5_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA4 +#define SDMA5_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA5 +#define SDMA5_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA6 +#define SDMA5_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA7 +#define SDMA5_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_DATA8 +#define SDMA5_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC4_MIDCMD_CNTL +#define SDMA5_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC5_RB_CNTL +#define SDMA5_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC5_RB_BASE +#define SDMA5_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_BASE_HI +#define SDMA5_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC5_RB_RPTR +#define SDMA5_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_RPTR_HI +#define SDMA5_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR +#define SDMA5_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR_HI +#define SDMA5_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR_POLL_CNTL +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC5_RB_RPTR_ADDR_HI +#define SDMA5_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_RPTR_ADDR_LO +#define SDMA5_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC5_IB_CNTL +#define SDMA5_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC5_IB_RPTR +#define SDMA5_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC5_IB_OFFSET +#define SDMA5_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC5_IB_BASE_LO +#define SDMA5_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC5_IB_BASE_HI +#define SDMA5_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_IB_SIZE +#define SDMA5_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC5_SKIP_CNTL +#define SDMA5_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC5_CONTEXT_STATUS +#define SDMA5_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC5_DOORBELL +#define SDMA5_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC5_STATUS +#define SDMA5_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC5_DOORBELL_LOG +#define SDMA5_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC5_WATERMARK +#define SDMA5_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC5_DOORBELL_OFFSET +#define SDMA5_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC5_CSA_ADDR_LO +#define SDMA5_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC5_CSA_ADDR_HI +#define SDMA5_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_IB_SUB_REMAIN +#define SDMA5_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC5_PREEMPT +#define SDMA5_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC5_DUMMY_REG +#define SDMA5_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC5_RB_AQL_CNTL +#define SDMA5_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC5_MINOR_PTR_UPDATE +#define SDMA5_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC5_MIDCMD_DATA0 +#define SDMA5_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA1 +#define SDMA5_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA2 +#define SDMA5_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA3 +#define SDMA5_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA4 +#define SDMA5_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA5 +#define SDMA5_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA6 +#define SDMA5_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA7 +#define SDMA5_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_DATA8 +#define SDMA5_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC5_MIDCMD_CNTL +#define SDMA5_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC6_RB_CNTL +#define SDMA5_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC6_RB_BASE +#define SDMA5_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_BASE_HI +#define SDMA5_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC6_RB_RPTR +#define SDMA5_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_RPTR_HI +#define SDMA5_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR +#define SDMA5_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR_HI +#define SDMA5_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR_POLL_CNTL +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC6_RB_RPTR_ADDR_HI +#define SDMA5_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_RPTR_ADDR_LO +#define SDMA5_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC6_IB_CNTL +#define SDMA5_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC6_IB_RPTR +#define SDMA5_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC6_IB_OFFSET +#define SDMA5_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC6_IB_BASE_LO +#define SDMA5_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC6_IB_BASE_HI +#define SDMA5_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_IB_SIZE +#define SDMA5_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC6_SKIP_CNTL +#define SDMA5_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC6_CONTEXT_STATUS +#define SDMA5_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC6_DOORBELL +#define SDMA5_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC6_STATUS +#define SDMA5_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC6_DOORBELL_LOG +#define SDMA5_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC6_WATERMARK +#define SDMA5_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC6_DOORBELL_OFFSET +#define SDMA5_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC6_CSA_ADDR_LO +#define SDMA5_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC6_CSA_ADDR_HI +#define SDMA5_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_IB_SUB_REMAIN +#define SDMA5_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC6_PREEMPT +#define SDMA5_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC6_DUMMY_REG +#define SDMA5_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC6_RB_AQL_CNTL +#define SDMA5_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC6_MINOR_PTR_UPDATE +#define SDMA5_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC6_MIDCMD_DATA0 +#define SDMA5_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA1 +#define SDMA5_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA2 +#define SDMA5_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA3 +#define SDMA5_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA4 +#define SDMA5_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA5 +#define SDMA5_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA6 +#define SDMA5_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA7 +#define SDMA5_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_DATA8 +#define SDMA5_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC6_MIDCMD_CNTL +#define SDMA5_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA5_RLC7_RB_CNTL +#define SDMA5_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA5_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA5_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA5_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA5_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA5_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA5_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA5_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA5_RLC7_RB_BASE +#define SDMA5_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_BASE_HI +#define SDMA5_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA5_RLC7_RB_RPTR +#define SDMA5_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_RPTR_HI +#define SDMA5_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR +#define SDMA5_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA5_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR_HI +#define SDMA5_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA5_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR_POLL_CNTL +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA5_RLC7_RB_RPTR_ADDR_HI +#define SDMA5_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_RPTR_ADDR_LO +#define SDMA5_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA5_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA5_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC7_IB_CNTL +#define SDMA5_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA5_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA5_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA5_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA5_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA5_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA5_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA5_RLC7_IB_RPTR +#define SDMA5_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA5_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC7_IB_OFFSET +#define SDMA5_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA5_RLC7_IB_BASE_LO +#define SDMA5_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA5_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA5_RLC7_IB_BASE_HI +#define SDMA5_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_IB_SIZE +#define SDMA5_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA5_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC7_SKIP_CNTL +#define SDMA5_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA5_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA5_RLC7_CONTEXT_STATUS +#define SDMA5_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA5_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA5_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA5_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA5_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA5_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA5_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA5_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA5_RLC7_DOORBELL +#define SDMA5_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA5_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA5_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA5_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA5_RLC7_STATUS +#define SDMA5_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA5_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA5_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA5_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA5_RLC7_DOORBELL_LOG +#define SDMA5_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA5_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA5_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA5_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA5_RLC7_WATERMARK +#define SDMA5_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA5_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA5_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA5_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA5_RLC7_DOORBELL_OFFSET +#define SDMA5_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA5_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA5_RLC7_CSA_ADDR_LO +#define SDMA5_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC7_CSA_ADDR_HI +#define SDMA5_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_IB_SUB_REMAIN +#define SDMA5_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA5_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA5_RLC7_PREEMPT +#define SDMA5_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA5_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA5_RLC7_DUMMY_REG +#define SDMA5_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA5_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA5_RLC7_RB_AQL_CNTL +#define SDMA5_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA5_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA5_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA5_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA5_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA5_RLC7_MINOR_PTR_UPDATE +#define SDMA5_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA5_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA5_RLC7_MIDCMD_DATA0 +#define SDMA5_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA1 +#define SDMA5_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA2 +#define SDMA5_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA3 +#define SDMA5_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA4 +#define SDMA5_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA5 +#define SDMA5_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA6 +#define SDMA5_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA7 +#define SDMA5_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_DATA8 +#define SDMA5_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA5_RLC7_MIDCMD_CNTL +#define SDMA5_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA5_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA5_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA5_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA5_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA5_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA5_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA5_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h new file mode 100644 index 000000000000..ae12db26362e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma6_4_2_2_OFFSET_HEADER +#define _sdma6_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma6_sdma6dec +// base address: 0x7c000 +#define mmSDMA6_UCODE_ADDR 0x0000 +#define mmSDMA6_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA6_UCODE_DATA 0x0001 +#define mmSDMA6_UCODE_DATA_BASE_IDX 1 +#define mmSDMA6_VM_CNTL 0x0004 +#define mmSDMA6_VM_CNTL_BASE_IDX 1 +#define mmSDMA6_VM_CTX_LO 0x0005 +#define mmSDMA6_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA6_VM_CTX_HI 0x0006 +#define mmSDMA6_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA6_ACTIVE_FCN_ID 0x0007 +#define mmSDMA6_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA6_VM_CTX_CNTL 0x0008 +#define mmSDMA6_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA6_VIRT_RESET_REQ 0x0009 +#define mmSDMA6_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA6_VF_ENABLE 0x000a +#define mmSDMA6_VF_ENABLE_BASE_IDX 1 +#define mmSDMA6_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA6_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA6_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA6_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA6_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA6_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA6_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA6_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA6_PUB_REG_TYPE0 0x000f +#define mmSDMA6_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA6_PUB_REG_TYPE1 0x0010 +#define mmSDMA6_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA6_PUB_REG_TYPE2 0x0011 +#define mmSDMA6_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA6_PUB_REG_TYPE3 0x0012 +#define mmSDMA6_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA6_MMHUB_CNTL 0x0013 +#define mmSDMA6_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA6_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA6_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA6_POWER_CNTL 0x001a +#define mmSDMA6_POWER_CNTL_BASE_IDX 1 +#define mmSDMA6_CLK_CTRL 0x001b +#define mmSDMA6_CLK_CTRL_BASE_IDX 1 +#define mmSDMA6_CNTL 0x001c +#define mmSDMA6_CNTL_BASE_IDX 1 +#define mmSDMA6_CHICKEN_BITS 0x001d +#define mmSDMA6_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA6_GB_ADDR_CONFIG 0x001e +#define mmSDMA6_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA6_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA6_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA6_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA6_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA6_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA6_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA6_RB_RPTR_FETCH 0x0022 +#define mmSDMA6_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA6_IB_OFFSET_FETCH 0x0023 +#define mmSDMA6_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA6_PROGRAM 0x0024 +#define mmSDMA6_PROGRAM_BASE_IDX 1 +#define mmSDMA6_STATUS_REG 0x0025 +#define mmSDMA6_STATUS_REG_BASE_IDX 1 +#define mmSDMA6_STATUS1_REG 0x0026 +#define mmSDMA6_STATUS1_REG_BASE_IDX 1 +#define mmSDMA6_RD_BURST_CNTL 0x0027 +#define mmSDMA6_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA6_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA6_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA6_UCODE_CHECKSUM 0x0029 +#define mmSDMA6_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA6_F32_CNTL 0x002a +#define mmSDMA6_F32_CNTL_BASE_IDX 1 +#define mmSDMA6_FREEZE 0x002b +#define mmSDMA6_FREEZE_BASE_IDX 1 +#define mmSDMA6_PHASE0_QUANTUM 0x002c +#define mmSDMA6_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA6_PHASE1_QUANTUM 0x002d +#define mmSDMA6_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA6_EDC_CONFIG 0x0032 +#define mmSDMA6_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA6_BA_THRESHOLD 0x0033 +#define mmSDMA6_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA6_ID 0x0034 +#define mmSDMA6_ID_BASE_IDX 1 +#define mmSDMA6_VERSION 0x0035 +#define mmSDMA6_VERSION_BASE_IDX 1 +#define mmSDMA6_EDC_COUNTER 0x0036 +#define mmSDMA6_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA6_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA6_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA6_STATUS2_REG 0x0038 +#define mmSDMA6_STATUS2_REG_BASE_IDX 1 +#define mmSDMA6_ATOMIC_CNTL 0x0039 +#define mmSDMA6_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA6_ATOMIC_PREOP_LO 0x003a +#define mmSDMA6_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA6_ATOMIC_PREOP_HI 0x003b +#define mmSDMA6_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA6_UTCL1_CNTL 0x003c +#define mmSDMA6_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA6_UTCL1_WATERMK 0x003d +#define mmSDMA6_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA6_UTCL1_RD_STATUS 0x003e +#define mmSDMA6_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA6_UTCL1_WR_STATUS 0x003f +#define mmSDMA6_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA6_UTCL1_INV0 0x0040 +#define mmSDMA6_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA6_UTCL1_INV1 0x0041 +#define mmSDMA6_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA6_UTCL1_INV2 0x0042 +#define mmSDMA6_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA6_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA6_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA6_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA6_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA6_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA6_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA6_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA6_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA6_UTCL1_TIMEOUT 0x0047 +#define mmSDMA6_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA6_UTCL1_PAGE 0x0048 +#define mmSDMA6_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA6_POWER_CNTL_IDLE 0x0049 +#define mmSDMA6_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA6_RELAX_ORDERING_LUT 0x004a +#define mmSDMA6_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA6_CHICKEN_BITS_2 0x004b +#define mmSDMA6_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA6_STATUS3_REG 0x004c +#define mmSDMA6_STATUS3_REG_BASE_IDX 1 +#define mmSDMA6_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA6_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA6_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_PHASE2_QUANTUM 0x004f +#define mmSDMA6_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA6_ERROR_LOG 0x0050 +#define mmSDMA6_ERROR_LOG_BASE_IDX 1 +#define mmSDMA6_PUB_DUMMY_REG0 0x0051 +#define mmSDMA6_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA6_PUB_DUMMY_REG1 0x0052 +#define mmSDMA6_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA6_PUB_DUMMY_REG2 0x0053 +#define mmSDMA6_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA6_PUB_DUMMY_REG3 0x0054 +#define mmSDMA6_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA6_F32_COUNTER 0x0055 +#define mmSDMA6_F32_COUNTER_BASE_IDX 1 +#define mmSDMA6_UNBREAKABLE 0x0056 +#define mmSDMA6_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA6_PERFMON_CNTL 0x0057 +#define mmSDMA6_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA6_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA6_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA6_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA6_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA6_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA6_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA6_CRD_CNTL 0x005b +#define mmSDMA6_CRD_CNTL_BASE_IDX 1 +#define mmSDMA6_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA6_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA6_ULV_CNTL 0x005e +#define mmSDMA6_ULV_CNTL_BASE_IDX 1 +#define mmSDMA6_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA6_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA6_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA6_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA6_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA6_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA6_GFX_RB_CNTL 0x0080 +#define mmSDMA6_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_RB_BASE 0x0081 +#define mmSDMA6_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA6_GFX_RB_BASE_HI 0x0082 +#define mmSDMA6_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_RPTR 0x0083 +#define mmSDMA6_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA6_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR 0x0085 +#define mmSDMA6_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA6_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA6_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA6_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA6_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_GFX_IB_CNTL 0x008a +#define mmSDMA6_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_IB_RPTR 0x008b +#define mmSDMA6_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_GFX_IB_OFFSET 0x008c +#define mmSDMA6_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_GFX_IB_BASE_LO 0x008d +#define mmSDMA6_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_GFX_IB_BASE_HI 0x008e +#define mmSDMA6_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_GFX_IB_SIZE 0x008f +#define mmSDMA6_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_GFX_SKIP_CNTL 0x0090 +#define mmSDMA6_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA6_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_GFX_DOORBELL 0x0092 +#define mmSDMA6_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA6_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA6_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_STATUS 0x00a8 +#define mmSDMA6_GFX_STATUS_BASE_IDX 1 +#define mmSDMA6_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA6_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_GFX_WATERMARK 0x00aa +#define mmSDMA6_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA6_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA6_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA6_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA6_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA6_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_GFX_PREEMPT 0x00b0 +#define mmSDMA6_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA6_GFX_DUMMY_REG 0x00b1 +#define mmSDMA6_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA6_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA6_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA6_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA6_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA6_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA6_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA6_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA6_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA6_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA6_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA6_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA6_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_CNTL 0x00d8 +#define mmSDMA6_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_BASE 0x00d9 +#define mmSDMA6_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_BASE_HI 0x00da +#define mmSDMA6_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_RPTR 0x00db +#define mmSDMA6_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA6_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR 0x00dd +#define mmSDMA6_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA6_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA6_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA6_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA6_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_CNTL 0x00e2 +#define mmSDMA6_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_RPTR 0x00e3 +#define mmSDMA6_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA6_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA6_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA6_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_SIZE 0x00e7 +#define mmSDMA6_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA6_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA6_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_PAGE_DOORBELL 0x00ea +#define mmSDMA6_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA6_PAGE_STATUS 0x0100 +#define mmSDMA6_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA6_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA6_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_PAGE_WATERMARK 0x0102 +#define mmSDMA6_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA6_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA6_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA6_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA6_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA6_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_PAGE_PREEMPT 0x0108 +#define mmSDMA6_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA6_PAGE_DUMMY_REG 0x0109 +#define mmSDMA6_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA6_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA6_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA6_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA6_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA6_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA6_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA6_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA6_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA6_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA6_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA6_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA6_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_CNTL 0x0130 +#define mmSDMA6_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_BASE 0x0131 +#define mmSDMA6_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA6_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_RPTR 0x0133 +#define mmSDMA6_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA6_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR 0x0135 +#define mmSDMA6_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA6_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA6_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA6_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA6_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_CNTL 0x013a +#define mmSDMA6_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_RPTR 0x013b +#define mmSDMA6_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_OFFSET 0x013c +#define mmSDMA6_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_BASE_LO 0x013d +#define mmSDMA6_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_BASE_HI 0x013e +#define mmSDMA6_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_SIZE 0x013f +#define mmSDMA6_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA6_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA6_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC0_DOORBELL 0x0142 +#define mmSDMA6_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC0_STATUS 0x0158 +#define mmSDMA6_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA6_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC0_WATERMARK 0x015a +#define mmSDMA6_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA6_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA6_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA6_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA6_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC0_PREEMPT 0x0160 +#define mmSDMA6_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC0_DUMMY_REG 0x0161 +#define mmSDMA6_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA6_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA6_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA6_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA6_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA6_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA6_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA6_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA6_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA6_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA6_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA6_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA6_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_CNTL 0x0188 +#define mmSDMA6_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_BASE 0x0189 +#define mmSDMA6_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_BASE_HI 0x018a +#define mmSDMA6_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_RPTR 0x018b +#define mmSDMA6_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA6_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR 0x018d +#define mmSDMA6_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA6_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA6_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA6_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA6_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_CNTL 0x0192 +#define mmSDMA6_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_RPTR 0x0193 +#define mmSDMA6_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_OFFSET 0x0194 +#define mmSDMA6_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA6_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA6_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_SIZE 0x0197 +#define mmSDMA6_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA6_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA6_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC1_DOORBELL 0x019a +#define mmSDMA6_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC1_STATUS 0x01b0 +#define mmSDMA6_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA6_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC1_WATERMARK 0x01b2 +#define mmSDMA6_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA6_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA6_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA6_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA6_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC1_PREEMPT 0x01b8 +#define mmSDMA6_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA6_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA6_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA6_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA6_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA6_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA6_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA6_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA6_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA6_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA6_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA6_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA6_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA6_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_CNTL 0x01e0 +#define mmSDMA6_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_BASE 0x01e1 +#define mmSDMA6_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA6_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_RPTR 0x01e3 +#define mmSDMA6_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA6_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR 0x01e5 +#define mmSDMA6_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA6_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA6_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA6_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA6_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_CNTL 0x01ea +#define mmSDMA6_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_RPTR 0x01eb +#define mmSDMA6_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_OFFSET 0x01ec +#define mmSDMA6_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA6_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA6_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_SIZE 0x01ef +#define mmSDMA6_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA6_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA6_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC2_DOORBELL 0x01f2 +#define mmSDMA6_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC2_STATUS 0x0208 +#define mmSDMA6_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA6_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC2_WATERMARK 0x020a +#define mmSDMA6_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA6_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA6_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA6_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA6_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC2_PREEMPT 0x0210 +#define mmSDMA6_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC2_DUMMY_REG 0x0211 +#define mmSDMA6_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA6_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA6_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA6_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA6_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA6_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA6_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA6_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA6_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA6_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA6_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA6_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA6_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_CNTL 0x0238 +#define mmSDMA6_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_BASE 0x0239 +#define mmSDMA6_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_BASE_HI 0x023a +#define mmSDMA6_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_RPTR 0x023b +#define mmSDMA6_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA6_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR 0x023d +#define mmSDMA6_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA6_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA6_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA6_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA6_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_CNTL 0x0242 +#define mmSDMA6_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_RPTR 0x0243 +#define mmSDMA6_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_OFFSET 0x0244 +#define mmSDMA6_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA6_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA6_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_SIZE 0x0247 +#define mmSDMA6_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA6_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA6_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC3_DOORBELL 0x024a +#define mmSDMA6_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC3_STATUS 0x0260 +#define mmSDMA6_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA6_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC3_WATERMARK 0x0262 +#define mmSDMA6_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA6_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA6_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA6_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA6_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC3_PREEMPT 0x0268 +#define mmSDMA6_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC3_DUMMY_REG 0x0269 +#define mmSDMA6_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA6_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA6_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA6_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA6_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA6_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA6_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA6_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA6_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA6_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA6_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA6_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA6_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_CNTL 0x0290 +#define mmSDMA6_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_BASE 0x0291 +#define mmSDMA6_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA6_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_RPTR 0x0293 +#define mmSDMA6_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA6_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR 0x0295 +#define mmSDMA6_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA6_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA6_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA6_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA6_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_CNTL 0x029a +#define mmSDMA6_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_RPTR 0x029b +#define mmSDMA6_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_OFFSET 0x029c +#define mmSDMA6_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_BASE_LO 0x029d +#define mmSDMA6_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_BASE_HI 0x029e +#define mmSDMA6_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_SIZE 0x029f +#define mmSDMA6_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA6_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA6_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC4_DOORBELL 0x02a2 +#define mmSDMA6_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC4_STATUS 0x02b8 +#define mmSDMA6_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA6_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC4_WATERMARK 0x02ba +#define mmSDMA6_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA6_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA6_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA6_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA6_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC4_PREEMPT 0x02c0 +#define mmSDMA6_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA6_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA6_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA6_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA6_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA6_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA6_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA6_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA6_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA6_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA6_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA6_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA6_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA6_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_CNTL 0x02e8 +#define mmSDMA6_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_BASE 0x02e9 +#define mmSDMA6_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA6_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_RPTR 0x02eb +#define mmSDMA6_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA6_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR 0x02ed +#define mmSDMA6_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA6_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA6_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA6_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA6_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_CNTL 0x02f2 +#define mmSDMA6_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_RPTR 0x02f3 +#define mmSDMA6_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA6_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA6_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA6_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_SIZE 0x02f7 +#define mmSDMA6_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA6_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA6_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC5_DOORBELL 0x02fa +#define mmSDMA6_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC5_STATUS 0x0310 +#define mmSDMA6_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA6_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC5_WATERMARK 0x0312 +#define mmSDMA6_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA6_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA6_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA6_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA6_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC5_PREEMPT 0x0318 +#define mmSDMA6_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC5_DUMMY_REG 0x0319 +#define mmSDMA6_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA6_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA6_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA6_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA6_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA6_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA6_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA6_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA6_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA6_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA6_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA6_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA6_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_CNTL 0x0340 +#define mmSDMA6_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_BASE 0x0341 +#define mmSDMA6_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA6_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_RPTR 0x0343 +#define mmSDMA6_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA6_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR 0x0345 +#define mmSDMA6_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA6_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA6_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA6_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA6_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_CNTL 0x034a +#define mmSDMA6_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_RPTR 0x034b +#define mmSDMA6_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_OFFSET 0x034c +#define mmSDMA6_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_BASE_LO 0x034d +#define mmSDMA6_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_BASE_HI 0x034e +#define mmSDMA6_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_SIZE 0x034f +#define mmSDMA6_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA6_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA6_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC6_DOORBELL 0x0352 +#define mmSDMA6_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC6_STATUS 0x0368 +#define mmSDMA6_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA6_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC6_WATERMARK 0x036a +#define mmSDMA6_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA6_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA6_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA6_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA6_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC6_PREEMPT 0x0370 +#define mmSDMA6_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC6_DUMMY_REG 0x0371 +#define mmSDMA6_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA6_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA6_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA6_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA6_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA6_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA6_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA6_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA6_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA6_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA6_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA6_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA6_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_CNTL 0x0398 +#define mmSDMA6_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_BASE 0x0399 +#define mmSDMA6_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_BASE_HI 0x039a +#define mmSDMA6_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_RPTR 0x039b +#define mmSDMA6_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA6_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR 0x039d +#define mmSDMA6_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA6_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA6_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA6_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA6_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_CNTL 0x03a2 +#define mmSDMA6_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_RPTR 0x03a3 +#define mmSDMA6_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA6_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA6_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA6_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_SIZE 0x03a7 +#define mmSDMA6_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA6_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA6_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA6_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC7_DOORBELL 0x03aa +#define mmSDMA6_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA6_RLC7_STATUS 0x03c0 +#define mmSDMA6_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA6_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA6_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA6_RLC7_WATERMARK 0x03c2 +#define mmSDMA6_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA6_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA6_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA6_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA6_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA6_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA6_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA6_RLC7_PREEMPT 0x03c8 +#define mmSDMA6_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA6_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA6_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA6_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA6_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA6_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA6_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA6_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA6_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA6_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA6_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA6_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA6_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA6_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA6_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA6_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA6_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA6_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h new file mode 100644 index 000000000000..55569f5d8eae --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma6_4_2_2_SH_MASK_HEADER +#define _sdma6_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma6_sdma6dec +//SDMA6_UCODE_ADDR +#define SDMA6_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA6_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA6_UCODE_DATA +#define SDMA6_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA6_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA6_VM_CNTL +#define SDMA6_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA6_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA6_VM_CTX_LO +#define SDMA6_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA6_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_VM_CTX_HI +#define SDMA6_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA6_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_ACTIVE_FCN_ID +#define SDMA6_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA6_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA6_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA6_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA6_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA6_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA6_VM_CTX_CNTL +#define SDMA6_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA6_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA6_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA6_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA6_VIRT_RESET_REQ +#define SDMA6_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA6_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA6_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA6_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA6_VF_ENABLE +#define SDMA6_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA6_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA6_CONTEXT_REG_TYPE0 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE__SHIFT 0x1 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_CNTL__SHIFT 0xa +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_RPTR__SHIFT 0xb +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_SIZE__SHIFT 0xf +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_DOORBELL__SHIFT 0x12 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_MASK 0x00000002L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_DOORBELL_MASK 0x00040000L +#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA6_CONTEXT_REG_TYPE1 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_STATUS__SHIFT 0x8 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_WATERMARK__SHIFT 0xa +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA6_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_PREEMPT__SHIFT 0x10 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA6_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_STATUS_MASK 0x00000100L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_WATERMARK_MASK 0x00000400L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA6_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_PREEMPT_MASK 0x00010000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA6_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA6_CONTEXT_REG_TYPE2 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA6_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA6_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA6_CONTEXT_REG_TYPE3 +#define SDMA6_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA6_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA6_PUB_REG_TYPE0 +#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_ADDR__SHIFT 0x0 +#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_DATA__SHIFT 0x1 +#define SDMA6_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CNTL__SHIFT 0x4 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_LO__SHIFT 0x5 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_HI__SHIFT 0x6 +#define SDMA6_PUB_REG_TYPE0__SDMA6_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA6_PUB_REG_TYPE0__SDMA6_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA6_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA6_PUB_REG_TYPE0__SDMA6_MMHUB_CNTL__SHIFT 0x13 +#define SDMA6_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA6_PUB_REG_TYPE0__SDMA6_POWER_CNTL__SHIFT 0x1a +#define SDMA6_PUB_REG_TYPE0__SDMA6_CLK_CTRL__SHIFT 0x1b +#define SDMA6_PUB_REG_TYPE0__SDMA6_CNTL__SHIFT 0x1c +#define SDMA6_PUB_REG_TYPE0__SDMA6_CHICKEN_BITS__SHIFT 0x1d +#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_ADDR_MASK 0x00000001L +#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_DATA_MASK 0x00000002L +#define SDMA6_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CNTL_MASK 0x00000010L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_LO_MASK 0x00000020L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_HI_MASK 0x00000040L +#define SDMA6_PUB_REG_TYPE0__SDMA6_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA6_PUB_REG_TYPE0__SDMA6_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA6_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_MMHUB_CNTL_MASK 0x00080000L +#define SDMA6_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_POWER_CNTL_MASK 0x04000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CLK_CTRL_MASK 0x08000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CNTL_MASK 0x10000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_CHICKEN_BITS_MASK 0x20000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA6_PUB_REG_TYPE1 +#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA6_PUB_REG_TYPE1__SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA6_PUB_REG_TYPE1__SDMA6_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA6_PUB_REG_TYPE1__SDMA6_PROGRAM__SHIFT 0x4 +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS_REG__SHIFT 0x5 +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS1_REG__SHIFT 0x6 +#define SDMA6_PUB_REG_TYPE1__SDMA6_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA6_PUB_REG_TYPE1__SDMA6_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA6_PUB_REG_TYPE1__SDMA6_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA6_PUB_REG_TYPE1__SDMA6_F32_CNTL__SHIFT 0xa +#define SDMA6_PUB_REG_TYPE1__SDMA6_FREEZE__SHIFT 0xb +#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA6_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_CONFIG__SHIFT 0x12 +#define SDMA6_PUB_REG_TYPE1__SDMA6_BA_THRESHOLD__SHIFT 0x13 +#define SDMA6_PUB_REG_TYPE1__SDMA6_ID__SHIFT 0x14 +#define SDMA6_PUB_REG_TYPE1__SDMA6_VERSION__SHIFT 0x15 +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER__SHIFT 0x16 +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS2_REG__SHIFT 0x18 +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_CNTL__SHIFT 0x1c +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA6_PUB_REG_TYPE1__SDMA6_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA6_PUB_REG_TYPE1__SDMA6_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA6_PUB_REG_TYPE1__SDMA6_PROGRAM_MASK 0x00000010L +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS_REG_MASK 0x00000020L +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS1_REG_MASK 0x00000040L +#define SDMA6_PUB_REG_TYPE1__SDMA6_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA6_PUB_REG_TYPE1__SDMA6_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA6_PUB_REG_TYPE1__SDMA6_F32_CNTL_MASK 0x00000400L +#define SDMA6_PUB_REG_TYPE1__SDMA6_FREEZE_MASK 0x00000800L +#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA6_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_CONFIG_MASK 0x00040000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_BA_THRESHOLD_MASK 0x00080000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_ID_MASK 0x00100000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_VERSION_MASK 0x00200000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_MASK 0x00400000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS2_REG_MASK 0x01000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_CNTL_MASK 0x10000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA6_PUB_REG_TYPE2 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV0__SHIFT 0x0 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV1__SHIFT 0x1 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV2__SHIFT 0x2 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_PAGE__SHIFT 0x8 +#define SDMA6_PUB_REG_TYPE2__SDMA6_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA6_PUB_REG_TYPE2__SDMA6_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA6_PUB_REG_TYPE2__SDMA6_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA6_PUB_REG_TYPE2__SDMA6_STATUS3_REG__SHIFT 0xc +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA6_PUB_REG_TYPE2__SDMA6_ERROR_LOG__SHIFT 0x10 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA6_PUB_REG_TYPE2__SDMA6_F32_COUNTER__SHIFT 0x15 +#define SDMA6_PUB_REG_TYPE2__SDMA6_UNBREAKABLE__SHIFT 0x16 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFMON_CNTL__SHIFT 0x17 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA6_PUB_REG_TYPE2__SDMA6_CRD_CNTL__SHIFT 0x1b +#define SDMA6_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA6_PUB_REG_TYPE2__SDMA6_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA6_PUB_REG_TYPE2__SDMA6_ULV_CNTL__SHIFT 0x1e +#define SDMA6_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV0_MASK 0x00000001L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV1_MASK 0x00000002L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV2_MASK 0x00000004L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_PAGE_MASK 0x00000100L +#define SDMA6_PUB_REG_TYPE2__SDMA6_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA6_PUB_REG_TYPE2__SDMA6_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA6_PUB_REG_TYPE2__SDMA6_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA6_PUB_REG_TYPE2__SDMA6_STATUS3_REG_MASK 0x00001000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_ERROR_LOG_MASK 0x00010000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_F32_COUNTER_MASK 0x00200000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_UNBREAKABLE_MASK 0x00400000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFMON_CNTL_MASK 0x00800000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_CRD_CNTL_MASK 0x08000000L +#define SDMA6_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA6_PUB_REG_TYPE2__SDMA6_ULV_CNTL_MASK 0x40000000L +#define SDMA6_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA6_PUB_REG_TYPE3 +#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA6_PUB_REG_TYPE3__SDMA6_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA6_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA6_PUB_REG_TYPE3__SDMA6_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA6_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA6_MMHUB_CNTL +#define SDMA6_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA6_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA6_CONTEXT_GROUP_BOUNDARY +#define SDMA6_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA6_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA6_POWER_CNTL +#define SDMA6_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA6_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA6_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA6_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA6_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA6_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA6_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA6_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA6_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA6_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA6_CLK_CTRL +#define SDMA6_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA6_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA6_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA6_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA6_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA6_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA6_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA6_CNTL +#define SDMA6_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA6_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA6_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA6_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA6_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA6_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA6_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA6_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA6_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA6_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA6_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA6_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA6_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA6_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA6_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA6_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA6_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA6_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA6_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA6_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA6_CHICKEN_BITS +#define SDMA6_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA6_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA6_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA6_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA6_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA6_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA6_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA6_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA6_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA6_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA6_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA6_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA6_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA6_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA6_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA6_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA6_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA6_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA6_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA6_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA6_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA6_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA6_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA6_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA6_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA6_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA6_GB_ADDR_CONFIG +#define SDMA6_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA6_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA6_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA6_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA6_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA6_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA6_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA6_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA6_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA6_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA6_GB_ADDR_CONFIG_READ +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA6_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA6_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA6_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA6_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA6_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA6_RB_RPTR_FETCH_HI +#define SDMA6_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA6_RB_RPTR_FETCH +#define SDMA6_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA6_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA6_IB_OFFSET_FETCH +#define SDMA6_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA6_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA6_PROGRAM +#define SDMA6_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA6_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA6_STATUS_REG +#define SDMA6_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA6_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA6_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA6_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA6_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA6_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA6_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA6_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA6_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA6_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA6_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA6_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA6_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA6_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA6_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA6_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA6_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA6_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA6_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA6_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA6_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA6_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA6_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA6_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA6_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA6_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA6_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA6_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA6_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA6_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA6_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA6_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA6_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA6_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA6_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA6_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA6_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA6_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA6_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA6_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA6_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA6_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA6_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA6_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA6_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA6_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA6_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA6_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA6_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA6_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA6_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA6_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA6_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA6_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA6_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA6_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA6_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA6_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA6_STATUS1_REG +#define SDMA6_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA6_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA6_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA6_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA6_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA6_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA6_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA6_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA6_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA6_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA6_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA6_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA6_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA6_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA6_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA6_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA6_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA6_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA6_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA6_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA6_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA6_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA6_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA6_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA6_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA6_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA6_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA6_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA6_RD_BURST_CNTL +#define SDMA6_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA6_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA6_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA6_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA6_HBM_PAGE_CONFIG +#define SDMA6_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA6_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA6_UCODE_CHECKSUM +#define SDMA6_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA6_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA6_F32_CNTL +#define SDMA6_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA6_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA6_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA6_F32_CNTL__STEP_MASK 0x00000002L +//SDMA6_FREEZE +#define SDMA6_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA6_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA6_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA6_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA6_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA6_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA6_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA6_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA6_PHASE0_QUANTUM +#define SDMA6_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA6_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA6_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA6_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA6_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA6_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA6_PHASE1_QUANTUM +#define SDMA6_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA6_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA6_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA6_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA6_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA6_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA6_EDC_CONFIG +#define SDMA6_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA6_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA6_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA6_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA6_BA_THRESHOLD +#define SDMA6_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA6_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA6_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA6_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA6_ID +#define SDMA6_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA6_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA6_VERSION +#define SDMA6_VERSION__MINVER__SHIFT 0x0 +#define SDMA6_VERSION__MAJVER__SHIFT 0x8 +#define SDMA6_VERSION__REV__SHIFT 0x10 +#define SDMA6_VERSION__MINVER_MASK 0x0000007FL +#define SDMA6_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA6_VERSION__REV_MASK 0x003F0000L +//SDMA6_EDC_COUNTER +#define SDMA6_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA6_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA6_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA6_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA6_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA6_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA6_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA6_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA6_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA6_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA6_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA6_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA6_EDC_COUNTER_CLEAR +#define SDMA6_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA6_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA6_STATUS2_REG +#define SDMA6_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA6_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA6_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA6_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA6_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA6_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA6_ATOMIC_CNTL +#define SDMA6_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA6_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA6_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA6_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA6_ATOMIC_PREOP_LO +#define SDMA6_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA6_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA6_ATOMIC_PREOP_HI +#define SDMA6_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA6_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_CNTL +#define SDMA6_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA6_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA6_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA6_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA6_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA6_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA6_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA6_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA6_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA6_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA6_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA6_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA6_UTCL1_WATERMK +#define SDMA6_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA6_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA6_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA6_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA6_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA6_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA6_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA6_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA6_UTCL1_RD_STATUS +#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA6_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA6_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA6_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA6_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA6_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA6_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA6_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA6_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA6_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA6_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA6_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA6_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA6_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA6_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA6_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA6_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA6_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA6_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA6_UTCL1_WR_STATUS +#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA6_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA6_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA6_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA6_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA6_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA6_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA6_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA6_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA6_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA6_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA6_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA6_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA6_UTCL1_INV0 +#define SDMA6_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA6_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA6_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA6_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA6_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA6_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA6_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA6_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA6_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA6_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA6_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA6_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA6_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA6_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA6_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA6_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA6_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA6_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA6_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA6_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA6_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA6_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA6_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA6_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA6_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA6_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA6_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA6_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA6_UTCL1_INV1 +#define SDMA6_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA6_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_INV2 +#define SDMA6_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA6_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_RD_XNACK0 +#define SDMA6_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA6_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_RD_XNACK1 +#define SDMA6_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA6_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA6_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA6_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA6_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA6_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA6_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA6_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA6_UTCL1_WR_XNACK0 +#define SDMA6_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA6_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA6_UTCL1_WR_XNACK1 +#define SDMA6_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA6_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA6_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA6_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA6_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA6_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA6_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA6_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA6_UTCL1_TIMEOUT +#define SDMA6_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA6_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA6_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA6_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA6_UTCL1_PAGE +#define SDMA6_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA6_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA6_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA6_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA6_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA6_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA6_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA6_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA6_POWER_CNTL_IDLE +#define SDMA6_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA6_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA6_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA6_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA6_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA6_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA6_RELAX_ORDERING_LUT +#define SDMA6_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA6_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA6_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA6_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA6_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA6_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA6_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA6_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA6_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA6_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA6_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA6_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA6_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA6_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA6_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA6_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA6_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA6_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA6_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA6_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA6_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA6_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA6_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA6_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA6_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA6_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA6_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA6_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA6_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA6_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA6_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA6_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA6_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA6_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA6_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA6_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA6_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA6_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA6_CHICKEN_BITS_2 +#define SDMA6_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA6_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA6_STATUS3_REG +#define SDMA6_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA6_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA6_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA6_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA6_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA6_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA6_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA6_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA6_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA6_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA6_PHYSICAL_ADDR_LO +#define SDMA6_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA6_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA6_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA6_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA6_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA6_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA6_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA6_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA6_PHYSICAL_ADDR_HI +#define SDMA6_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA6_PHASE2_QUANTUM +#define SDMA6_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA6_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA6_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA6_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA6_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA6_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA6_ERROR_LOG +#define SDMA6_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA6_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA6_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA6_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA6_PUB_DUMMY_REG0 +#define SDMA6_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA6_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA6_PUB_DUMMY_REG1 +#define SDMA6_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA6_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA6_PUB_DUMMY_REG2 +#define SDMA6_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA6_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA6_PUB_DUMMY_REG3 +#define SDMA6_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA6_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA6_F32_COUNTER +#define SDMA6_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA6_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA6_UNBREAKABLE +#define SDMA6_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA6_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA6_PERFMON_CNTL +#define SDMA6_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA6_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA6_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA6_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA6_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA6_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA6_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA6_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA6_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA6_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA6_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA6_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA6_PERFCOUNTER0_RESULT +#define SDMA6_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA6_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA6_PERFCOUNTER1_RESULT +#define SDMA6_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA6_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA6_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA6_CRD_CNTL +#define SDMA6_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA6_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA6_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA6_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA6_GPU_IOV_VIOLATION_LOG +#define SDMA6_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA6_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA6_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA6_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA6_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA6_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA6_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA6_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA6_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA6_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA6_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA6_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA6_ULV_CNTL +#define SDMA6_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA6_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA6_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA6_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA6_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA6_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA6_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA6_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA6_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA6_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA6_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA6_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA6_EA_DBIT_ADDR_DATA +#define SDMA6_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA6_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA6_EA_DBIT_ADDR_INDEX +#define SDMA6_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA6_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA6_GPU_IOV_VIOLATION_LOG2 +#define SDMA6_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA6_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA6_GFX_RB_CNTL +#define SDMA6_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_GFX_RB_BASE +#define SDMA6_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_BASE_HI +#define SDMA6_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_GFX_RB_RPTR +#define SDMA6_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_RPTR_HI +#define SDMA6_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR +#define SDMA6_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR_HI +#define SDMA6_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR_POLL_CNTL +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_GFX_RB_RPTR_ADDR_HI +#define SDMA6_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_RPTR_ADDR_LO +#define SDMA6_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_GFX_IB_CNTL +#define SDMA6_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_GFX_IB_RPTR +#define SDMA6_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_GFX_IB_OFFSET +#define SDMA6_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_GFX_IB_BASE_LO +#define SDMA6_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_GFX_IB_BASE_HI +#define SDMA6_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_IB_SIZE +#define SDMA6_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_GFX_SKIP_CNTL +#define SDMA6_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_GFX_CONTEXT_STATUS +#define SDMA6_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_GFX_DOORBELL +#define SDMA6_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_GFX_CONTEXT_CNTL +#define SDMA6_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA6_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA6_GFX_STATUS +#define SDMA6_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_GFX_DOORBELL_LOG +#define SDMA6_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_GFX_WATERMARK +#define SDMA6_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_GFX_DOORBELL_OFFSET +#define SDMA6_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_GFX_CSA_ADDR_LO +#define SDMA6_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_GFX_CSA_ADDR_HI +#define SDMA6_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_IB_SUB_REMAIN +#define SDMA6_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_GFX_PREEMPT +#define SDMA6_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_GFX_DUMMY_REG +#define SDMA6_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_GFX_RB_AQL_CNTL +#define SDMA6_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_GFX_MINOR_PTR_UPDATE +#define SDMA6_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_GFX_MIDCMD_DATA0 +#define SDMA6_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA1 +#define SDMA6_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA2 +#define SDMA6_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA3 +#define SDMA6_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA4 +#define SDMA6_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA5 +#define SDMA6_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA6 +#define SDMA6_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA7 +#define SDMA6_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_DATA8 +#define SDMA6_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_GFX_MIDCMD_CNTL +#define SDMA6_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_PAGE_RB_CNTL +#define SDMA6_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_PAGE_RB_BASE +#define SDMA6_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_BASE_HI +#define SDMA6_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_PAGE_RB_RPTR +#define SDMA6_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_RPTR_HI +#define SDMA6_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR +#define SDMA6_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR_HI +#define SDMA6_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR_POLL_CNTL +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_PAGE_RB_RPTR_ADDR_HI +#define SDMA6_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_RPTR_ADDR_LO +#define SDMA6_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_PAGE_IB_CNTL +#define SDMA6_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_PAGE_IB_RPTR +#define SDMA6_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_PAGE_IB_OFFSET +#define SDMA6_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_PAGE_IB_BASE_LO +#define SDMA6_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_PAGE_IB_BASE_HI +#define SDMA6_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_IB_SIZE +#define SDMA6_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_PAGE_SKIP_CNTL +#define SDMA6_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_PAGE_CONTEXT_STATUS +#define SDMA6_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_PAGE_DOORBELL +#define SDMA6_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_PAGE_STATUS +#define SDMA6_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_PAGE_DOORBELL_LOG +#define SDMA6_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_PAGE_WATERMARK +#define SDMA6_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_PAGE_DOORBELL_OFFSET +#define SDMA6_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_PAGE_CSA_ADDR_LO +#define SDMA6_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_PAGE_CSA_ADDR_HI +#define SDMA6_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_IB_SUB_REMAIN +#define SDMA6_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_PAGE_PREEMPT +#define SDMA6_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_PAGE_DUMMY_REG +#define SDMA6_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_PAGE_RB_AQL_CNTL +#define SDMA6_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_PAGE_MINOR_PTR_UPDATE +#define SDMA6_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_PAGE_MIDCMD_DATA0 +#define SDMA6_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA1 +#define SDMA6_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA2 +#define SDMA6_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA3 +#define SDMA6_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA4 +#define SDMA6_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA5 +#define SDMA6_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA6 +#define SDMA6_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA7 +#define SDMA6_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_DATA8 +#define SDMA6_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_PAGE_MIDCMD_CNTL +#define SDMA6_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC0_RB_CNTL +#define SDMA6_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC0_RB_BASE +#define SDMA6_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_BASE_HI +#define SDMA6_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC0_RB_RPTR +#define SDMA6_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_RPTR_HI +#define SDMA6_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR +#define SDMA6_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR_HI +#define SDMA6_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR_POLL_CNTL +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC0_RB_RPTR_ADDR_HI +#define SDMA6_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_RPTR_ADDR_LO +#define SDMA6_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC0_IB_CNTL +#define SDMA6_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC0_IB_RPTR +#define SDMA6_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC0_IB_OFFSET +#define SDMA6_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC0_IB_BASE_LO +#define SDMA6_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC0_IB_BASE_HI +#define SDMA6_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_IB_SIZE +#define SDMA6_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC0_SKIP_CNTL +#define SDMA6_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC0_CONTEXT_STATUS +#define SDMA6_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC0_DOORBELL +#define SDMA6_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC0_STATUS +#define SDMA6_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC0_DOORBELL_LOG +#define SDMA6_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC0_WATERMARK +#define SDMA6_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC0_DOORBELL_OFFSET +#define SDMA6_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC0_CSA_ADDR_LO +#define SDMA6_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC0_CSA_ADDR_HI +#define SDMA6_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_IB_SUB_REMAIN +#define SDMA6_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC0_PREEMPT +#define SDMA6_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC0_DUMMY_REG +#define SDMA6_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC0_RB_AQL_CNTL +#define SDMA6_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC0_MINOR_PTR_UPDATE +#define SDMA6_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC0_MIDCMD_DATA0 +#define SDMA6_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA1 +#define SDMA6_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA2 +#define SDMA6_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA3 +#define SDMA6_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA4 +#define SDMA6_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA5 +#define SDMA6_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA6 +#define SDMA6_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA7 +#define SDMA6_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_DATA8 +#define SDMA6_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC0_MIDCMD_CNTL +#define SDMA6_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC1_RB_CNTL +#define SDMA6_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC1_RB_BASE +#define SDMA6_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_BASE_HI +#define SDMA6_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC1_RB_RPTR +#define SDMA6_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_RPTR_HI +#define SDMA6_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR +#define SDMA6_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR_HI +#define SDMA6_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR_POLL_CNTL +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC1_RB_RPTR_ADDR_HI +#define SDMA6_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_RPTR_ADDR_LO +#define SDMA6_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC1_IB_CNTL +#define SDMA6_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC1_IB_RPTR +#define SDMA6_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC1_IB_OFFSET +#define SDMA6_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC1_IB_BASE_LO +#define SDMA6_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC1_IB_BASE_HI +#define SDMA6_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_IB_SIZE +#define SDMA6_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC1_SKIP_CNTL +#define SDMA6_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC1_CONTEXT_STATUS +#define SDMA6_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC1_DOORBELL +#define SDMA6_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC1_STATUS +#define SDMA6_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC1_DOORBELL_LOG +#define SDMA6_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC1_WATERMARK +#define SDMA6_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC1_DOORBELL_OFFSET +#define SDMA6_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC1_CSA_ADDR_LO +#define SDMA6_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC1_CSA_ADDR_HI +#define SDMA6_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_IB_SUB_REMAIN +#define SDMA6_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC1_PREEMPT +#define SDMA6_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC1_DUMMY_REG +#define SDMA6_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC1_RB_AQL_CNTL +#define SDMA6_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC1_MINOR_PTR_UPDATE +#define SDMA6_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC1_MIDCMD_DATA0 +#define SDMA6_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA1 +#define SDMA6_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA2 +#define SDMA6_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA3 +#define SDMA6_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA4 +#define SDMA6_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA5 +#define SDMA6_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA6 +#define SDMA6_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA7 +#define SDMA6_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_DATA8 +#define SDMA6_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC1_MIDCMD_CNTL +#define SDMA6_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC2_RB_CNTL +#define SDMA6_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC2_RB_BASE +#define SDMA6_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_BASE_HI +#define SDMA6_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC2_RB_RPTR +#define SDMA6_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_RPTR_HI +#define SDMA6_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR +#define SDMA6_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR_HI +#define SDMA6_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR_POLL_CNTL +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC2_RB_RPTR_ADDR_HI +#define SDMA6_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_RPTR_ADDR_LO +#define SDMA6_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC2_IB_CNTL +#define SDMA6_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC2_IB_RPTR +#define SDMA6_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC2_IB_OFFSET +#define SDMA6_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC2_IB_BASE_LO +#define SDMA6_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC2_IB_BASE_HI +#define SDMA6_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_IB_SIZE +#define SDMA6_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC2_SKIP_CNTL +#define SDMA6_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC2_CONTEXT_STATUS +#define SDMA6_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC2_DOORBELL +#define SDMA6_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC2_STATUS +#define SDMA6_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC2_DOORBELL_LOG +#define SDMA6_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC2_WATERMARK +#define SDMA6_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC2_DOORBELL_OFFSET +#define SDMA6_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC2_CSA_ADDR_LO +#define SDMA6_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC2_CSA_ADDR_HI +#define SDMA6_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_IB_SUB_REMAIN +#define SDMA6_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC2_PREEMPT +#define SDMA6_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC2_DUMMY_REG +#define SDMA6_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC2_RB_AQL_CNTL +#define SDMA6_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC2_MINOR_PTR_UPDATE +#define SDMA6_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC2_MIDCMD_DATA0 +#define SDMA6_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA1 +#define SDMA6_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA2 +#define SDMA6_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA3 +#define SDMA6_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA4 +#define SDMA6_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA5 +#define SDMA6_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA6 +#define SDMA6_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA7 +#define SDMA6_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_DATA8 +#define SDMA6_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC2_MIDCMD_CNTL +#define SDMA6_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC3_RB_CNTL +#define SDMA6_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC3_RB_BASE +#define SDMA6_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_BASE_HI +#define SDMA6_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC3_RB_RPTR +#define SDMA6_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_RPTR_HI +#define SDMA6_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR +#define SDMA6_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR_HI +#define SDMA6_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR_POLL_CNTL +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC3_RB_RPTR_ADDR_HI +#define SDMA6_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_RPTR_ADDR_LO +#define SDMA6_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC3_IB_CNTL +#define SDMA6_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC3_IB_RPTR +#define SDMA6_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC3_IB_OFFSET +#define SDMA6_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC3_IB_BASE_LO +#define SDMA6_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC3_IB_BASE_HI +#define SDMA6_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_IB_SIZE +#define SDMA6_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC3_SKIP_CNTL +#define SDMA6_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC3_CONTEXT_STATUS +#define SDMA6_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC3_DOORBELL +#define SDMA6_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC3_STATUS +#define SDMA6_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC3_DOORBELL_LOG +#define SDMA6_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC3_WATERMARK +#define SDMA6_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC3_DOORBELL_OFFSET +#define SDMA6_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC3_CSA_ADDR_LO +#define SDMA6_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC3_CSA_ADDR_HI +#define SDMA6_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_IB_SUB_REMAIN +#define SDMA6_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC3_PREEMPT +#define SDMA6_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC3_DUMMY_REG +#define SDMA6_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC3_RB_AQL_CNTL +#define SDMA6_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC3_MINOR_PTR_UPDATE +#define SDMA6_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC3_MIDCMD_DATA0 +#define SDMA6_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA1 +#define SDMA6_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA2 +#define SDMA6_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA3 +#define SDMA6_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA4 +#define SDMA6_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA5 +#define SDMA6_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA6 +#define SDMA6_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA7 +#define SDMA6_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_DATA8 +#define SDMA6_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC3_MIDCMD_CNTL +#define SDMA6_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC4_RB_CNTL +#define SDMA6_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC4_RB_BASE +#define SDMA6_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_BASE_HI +#define SDMA6_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC4_RB_RPTR +#define SDMA6_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_RPTR_HI +#define SDMA6_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR +#define SDMA6_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR_HI +#define SDMA6_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR_POLL_CNTL +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC4_RB_RPTR_ADDR_HI +#define SDMA6_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_RPTR_ADDR_LO +#define SDMA6_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC4_IB_CNTL +#define SDMA6_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC4_IB_RPTR +#define SDMA6_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC4_IB_OFFSET +#define SDMA6_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC4_IB_BASE_LO +#define SDMA6_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC4_IB_BASE_HI +#define SDMA6_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_IB_SIZE +#define SDMA6_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC4_SKIP_CNTL +#define SDMA6_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC4_CONTEXT_STATUS +#define SDMA6_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC4_DOORBELL +#define SDMA6_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC4_STATUS +#define SDMA6_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC4_DOORBELL_LOG +#define SDMA6_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC4_WATERMARK +#define SDMA6_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC4_DOORBELL_OFFSET +#define SDMA6_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC4_CSA_ADDR_LO +#define SDMA6_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC4_CSA_ADDR_HI +#define SDMA6_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_IB_SUB_REMAIN +#define SDMA6_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC4_PREEMPT +#define SDMA6_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC4_DUMMY_REG +#define SDMA6_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC4_RB_AQL_CNTL +#define SDMA6_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC4_MINOR_PTR_UPDATE +#define SDMA6_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC4_MIDCMD_DATA0 +#define SDMA6_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA1 +#define SDMA6_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA2 +#define SDMA6_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA3 +#define SDMA6_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA4 +#define SDMA6_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA5 +#define SDMA6_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA6 +#define SDMA6_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA7 +#define SDMA6_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_DATA8 +#define SDMA6_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC4_MIDCMD_CNTL +#define SDMA6_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC5_RB_CNTL +#define SDMA6_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC5_RB_BASE +#define SDMA6_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_BASE_HI +#define SDMA6_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC5_RB_RPTR +#define SDMA6_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_RPTR_HI +#define SDMA6_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR +#define SDMA6_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR_HI +#define SDMA6_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR_POLL_CNTL +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC5_RB_RPTR_ADDR_HI +#define SDMA6_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_RPTR_ADDR_LO +#define SDMA6_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC5_IB_CNTL +#define SDMA6_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC5_IB_RPTR +#define SDMA6_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC5_IB_OFFSET +#define SDMA6_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC5_IB_BASE_LO +#define SDMA6_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC5_IB_BASE_HI +#define SDMA6_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_IB_SIZE +#define SDMA6_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC5_SKIP_CNTL +#define SDMA6_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC5_CONTEXT_STATUS +#define SDMA6_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC5_DOORBELL +#define SDMA6_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC5_STATUS +#define SDMA6_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC5_DOORBELL_LOG +#define SDMA6_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC5_WATERMARK +#define SDMA6_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC5_DOORBELL_OFFSET +#define SDMA6_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC5_CSA_ADDR_LO +#define SDMA6_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC5_CSA_ADDR_HI +#define SDMA6_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_IB_SUB_REMAIN +#define SDMA6_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC5_PREEMPT +#define SDMA6_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC5_DUMMY_REG +#define SDMA6_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC5_RB_AQL_CNTL +#define SDMA6_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC5_MINOR_PTR_UPDATE +#define SDMA6_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC5_MIDCMD_DATA0 +#define SDMA6_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA1 +#define SDMA6_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA2 +#define SDMA6_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA3 +#define SDMA6_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA4 +#define SDMA6_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA5 +#define SDMA6_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA6 +#define SDMA6_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA7 +#define SDMA6_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_DATA8 +#define SDMA6_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC5_MIDCMD_CNTL +#define SDMA6_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC6_RB_CNTL +#define SDMA6_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC6_RB_BASE +#define SDMA6_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_BASE_HI +#define SDMA6_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC6_RB_RPTR +#define SDMA6_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_RPTR_HI +#define SDMA6_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR +#define SDMA6_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR_HI +#define SDMA6_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR_POLL_CNTL +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC6_RB_RPTR_ADDR_HI +#define SDMA6_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_RPTR_ADDR_LO +#define SDMA6_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC6_IB_CNTL +#define SDMA6_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC6_IB_RPTR +#define SDMA6_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC6_IB_OFFSET +#define SDMA6_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC6_IB_BASE_LO +#define SDMA6_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC6_IB_BASE_HI +#define SDMA6_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_IB_SIZE +#define SDMA6_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC6_SKIP_CNTL +#define SDMA6_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC6_CONTEXT_STATUS +#define SDMA6_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC6_DOORBELL +#define SDMA6_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC6_STATUS +#define SDMA6_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC6_DOORBELL_LOG +#define SDMA6_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC6_WATERMARK +#define SDMA6_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC6_DOORBELL_OFFSET +#define SDMA6_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC6_CSA_ADDR_LO +#define SDMA6_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC6_CSA_ADDR_HI +#define SDMA6_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_IB_SUB_REMAIN +#define SDMA6_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC6_PREEMPT +#define SDMA6_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC6_DUMMY_REG +#define SDMA6_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC6_RB_AQL_CNTL +#define SDMA6_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC6_MINOR_PTR_UPDATE +#define SDMA6_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC6_MIDCMD_DATA0 +#define SDMA6_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA1 +#define SDMA6_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA2 +#define SDMA6_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA3 +#define SDMA6_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA4 +#define SDMA6_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA5 +#define SDMA6_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA6 +#define SDMA6_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA7 +#define SDMA6_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_DATA8 +#define SDMA6_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC6_MIDCMD_CNTL +#define SDMA6_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA6_RLC7_RB_CNTL +#define SDMA6_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA6_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA6_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA6_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA6_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA6_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA6_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA6_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA6_RLC7_RB_BASE +#define SDMA6_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_BASE_HI +#define SDMA6_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA6_RLC7_RB_RPTR +#define SDMA6_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_RPTR_HI +#define SDMA6_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR +#define SDMA6_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA6_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR_HI +#define SDMA6_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA6_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR_POLL_CNTL +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA6_RLC7_RB_RPTR_ADDR_HI +#define SDMA6_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_RPTR_ADDR_LO +#define SDMA6_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA6_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA6_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC7_IB_CNTL +#define SDMA6_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA6_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA6_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA6_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA6_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA6_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA6_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA6_RLC7_IB_RPTR +#define SDMA6_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA6_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC7_IB_OFFSET +#define SDMA6_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA6_RLC7_IB_BASE_LO +#define SDMA6_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA6_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA6_RLC7_IB_BASE_HI +#define SDMA6_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_IB_SIZE +#define SDMA6_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA6_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC7_SKIP_CNTL +#define SDMA6_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA6_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA6_RLC7_CONTEXT_STATUS +#define SDMA6_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA6_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA6_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA6_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA6_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA6_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA6_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA6_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA6_RLC7_DOORBELL +#define SDMA6_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA6_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA6_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA6_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA6_RLC7_STATUS +#define SDMA6_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA6_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA6_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA6_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA6_RLC7_DOORBELL_LOG +#define SDMA6_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA6_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA6_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA6_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA6_RLC7_WATERMARK +#define SDMA6_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA6_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA6_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA6_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA6_RLC7_DOORBELL_OFFSET +#define SDMA6_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA6_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA6_RLC7_CSA_ADDR_LO +#define SDMA6_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC7_CSA_ADDR_HI +#define SDMA6_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_IB_SUB_REMAIN +#define SDMA6_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA6_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA6_RLC7_PREEMPT +#define SDMA6_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA6_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA6_RLC7_DUMMY_REG +#define SDMA6_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA6_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA6_RLC7_RB_AQL_CNTL +#define SDMA6_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA6_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA6_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA6_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA6_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA6_RLC7_MINOR_PTR_UPDATE +#define SDMA6_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA6_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA6_RLC7_MIDCMD_DATA0 +#define SDMA6_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA1 +#define SDMA6_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA2 +#define SDMA6_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA3 +#define SDMA6_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA4 +#define SDMA6_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA5 +#define SDMA6_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA6 +#define SDMA6_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA7 +#define SDMA6_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_DATA8 +#define SDMA6_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA6_RLC7_MIDCMD_CNTL +#define SDMA6_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA6_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA6_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA6_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA6_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA6_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA6_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA6_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h new file mode 100644 index 000000000000..10f387202af6 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h @@ -0,0 +1,1043 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma7_4_2_2_OFFSET_HEADER +#define _sdma7_4_2_2_OFFSET_HEADER + + + +// addressBlock: sdma7_sdma7dec +// base address: 0x7d000 +#define mmSDMA7_UCODE_ADDR 0x0000 +#define mmSDMA7_UCODE_ADDR_BASE_IDX 1 +#define mmSDMA7_UCODE_DATA 0x0001 +#define mmSDMA7_UCODE_DATA_BASE_IDX 1 +#define mmSDMA7_VM_CNTL 0x0004 +#define mmSDMA7_VM_CNTL_BASE_IDX 1 +#define mmSDMA7_VM_CTX_LO 0x0005 +#define mmSDMA7_VM_CTX_LO_BASE_IDX 1 +#define mmSDMA7_VM_CTX_HI 0x0006 +#define mmSDMA7_VM_CTX_HI_BASE_IDX 1 +#define mmSDMA7_ACTIVE_FCN_ID 0x0007 +#define mmSDMA7_ACTIVE_FCN_ID_BASE_IDX 1 +#define mmSDMA7_VM_CTX_CNTL 0x0008 +#define mmSDMA7_VM_CTX_CNTL_BASE_IDX 1 +#define mmSDMA7_VIRT_RESET_REQ 0x0009 +#define mmSDMA7_VIRT_RESET_REQ_BASE_IDX 1 +#define mmSDMA7_VF_ENABLE 0x000a +#define mmSDMA7_VF_ENABLE_BASE_IDX 1 +#define mmSDMA7_CONTEXT_REG_TYPE0 0x000b +#define mmSDMA7_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define mmSDMA7_CONTEXT_REG_TYPE1 0x000c +#define mmSDMA7_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define mmSDMA7_CONTEXT_REG_TYPE2 0x000d +#define mmSDMA7_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define mmSDMA7_CONTEXT_REG_TYPE3 0x000e +#define mmSDMA7_CONTEXT_REG_TYPE3_BASE_IDX 1 +#define mmSDMA7_PUB_REG_TYPE0 0x000f +#define mmSDMA7_PUB_REG_TYPE0_BASE_IDX 1 +#define mmSDMA7_PUB_REG_TYPE1 0x0010 +#define mmSDMA7_PUB_REG_TYPE1_BASE_IDX 1 +#define mmSDMA7_PUB_REG_TYPE2 0x0011 +#define mmSDMA7_PUB_REG_TYPE2_BASE_IDX 1 +#define mmSDMA7_PUB_REG_TYPE3 0x0012 +#define mmSDMA7_PUB_REG_TYPE3_BASE_IDX 1 +#define mmSDMA7_MMHUB_CNTL 0x0013 +#define mmSDMA7_MMHUB_CNTL_BASE_IDX 1 +#define mmSDMA7_CONTEXT_GROUP_BOUNDARY 0x0019 +#define mmSDMA7_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 +#define mmSDMA7_POWER_CNTL 0x001a +#define mmSDMA7_POWER_CNTL_BASE_IDX 1 +#define mmSDMA7_CLK_CTRL 0x001b +#define mmSDMA7_CLK_CTRL_BASE_IDX 1 +#define mmSDMA7_CNTL 0x001c +#define mmSDMA7_CNTL_BASE_IDX 1 +#define mmSDMA7_CHICKEN_BITS 0x001d +#define mmSDMA7_CHICKEN_BITS_BASE_IDX 1 +#define mmSDMA7_GB_ADDR_CONFIG 0x001e +#define mmSDMA7_GB_ADDR_CONFIG_BASE_IDX 1 +#define mmSDMA7_GB_ADDR_CONFIG_READ 0x001f +#define mmSDMA7_GB_ADDR_CONFIG_READ_BASE_IDX 1 +#define mmSDMA7_RB_RPTR_FETCH_HI 0x0020 +#define mmSDMA7_RB_RPTR_FETCH_HI_BASE_IDX 1 +#define mmSDMA7_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 +#define mmSDMA7_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 +#define mmSDMA7_RB_RPTR_FETCH 0x0022 +#define mmSDMA7_RB_RPTR_FETCH_BASE_IDX 1 +#define mmSDMA7_IB_OFFSET_FETCH 0x0023 +#define mmSDMA7_IB_OFFSET_FETCH_BASE_IDX 1 +#define mmSDMA7_PROGRAM 0x0024 +#define mmSDMA7_PROGRAM_BASE_IDX 1 +#define mmSDMA7_STATUS_REG 0x0025 +#define mmSDMA7_STATUS_REG_BASE_IDX 1 +#define mmSDMA7_STATUS1_REG 0x0026 +#define mmSDMA7_STATUS1_REG_BASE_IDX 1 +#define mmSDMA7_RD_BURST_CNTL 0x0027 +#define mmSDMA7_RD_BURST_CNTL_BASE_IDX 1 +#define mmSDMA7_HBM_PAGE_CONFIG 0x0028 +#define mmSDMA7_HBM_PAGE_CONFIG_BASE_IDX 1 +#define mmSDMA7_UCODE_CHECKSUM 0x0029 +#define mmSDMA7_UCODE_CHECKSUM_BASE_IDX 1 +#define mmSDMA7_F32_CNTL 0x002a +#define mmSDMA7_F32_CNTL_BASE_IDX 1 +#define mmSDMA7_FREEZE 0x002b +#define mmSDMA7_FREEZE_BASE_IDX 1 +#define mmSDMA7_PHASE0_QUANTUM 0x002c +#define mmSDMA7_PHASE0_QUANTUM_BASE_IDX 1 +#define mmSDMA7_PHASE1_QUANTUM 0x002d +#define mmSDMA7_PHASE1_QUANTUM_BASE_IDX 1 +#define mmSDMA7_EDC_CONFIG 0x0032 +#define mmSDMA7_EDC_CONFIG_BASE_IDX 1 +#define mmSDMA7_BA_THRESHOLD 0x0033 +#define mmSDMA7_BA_THRESHOLD_BASE_IDX 1 +#define mmSDMA7_ID 0x0034 +#define mmSDMA7_ID_BASE_IDX 1 +#define mmSDMA7_VERSION 0x0035 +#define mmSDMA7_VERSION_BASE_IDX 1 +#define mmSDMA7_EDC_COUNTER 0x0036 +#define mmSDMA7_EDC_COUNTER_BASE_IDX 1 +#define mmSDMA7_EDC_COUNTER_CLEAR 0x0037 +#define mmSDMA7_EDC_COUNTER_CLEAR_BASE_IDX 1 +#define mmSDMA7_STATUS2_REG 0x0038 +#define mmSDMA7_STATUS2_REG_BASE_IDX 1 +#define mmSDMA7_ATOMIC_CNTL 0x0039 +#define mmSDMA7_ATOMIC_CNTL_BASE_IDX 1 +#define mmSDMA7_ATOMIC_PREOP_LO 0x003a +#define mmSDMA7_ATOMIC_PREOP_LO_BASE_IDX 1 +#define mmSDMA7_ATOMIC_PREOP_HI 0x003b +#define mmSDMA7_ATOMIC_PREOP_HI_BASE_IDX 1 +#define mmSDMA7_UTCL1_CNTL 0x003c +#define mmSDMA7_UTCL1_CNTL_BASE_IDX 1 +#define mmSDMA7_UTCL1_WATERMK 0x003d +#define mmSDMA7_UTCL1_WATERMK_BASE_IDX 1 +#define mmSDMA7_UTCL1_RD_STATUS 0x003e +#define mmSDMA7_UTCL1_RD_STATUS_BASE_IDX 1 +#define mmSDMA7_UTCL1_WR_STATUS 0x003f +#define mmSDMA7_UTCL1_WR_STATUS_BASE_IDX 1 +#define mmSDMA7_UTCL1_INV0 0x0040 +#define mmSDMA7_UTCL1_INV0_BASE_IDX 1 +#define mmSDMA7_UTCL1_INV1 0x0041 +#define mmSDMA7_UTCL1_INV1_BASE_IDX 1 +#define mmSDMA7_UTCL1_INV2 0x0042 +#define mmSDMA7_UTCL1_INV2_BASE_IDX 1 +#define mmSDMA7_UTCL1_RD_XNACK0 0x0043 +#define mmSDMA7_UTCL1_RD_XNACK0_BASE_IDX 1 +#define mmSDMA7_UTCL1_RD_XNACK1 0x0044 +#define mmSDMA7_UTCL1_RD_XNACK1_BASE_IDX 1 +#define mmSDMA7_UTCL1_WR_XNACK0 0x0045 +#define mmSDMA7_UTCL1_WR_XNACK0_BASE_IDX 1 +#define mmSDMA7_UTCL1_WR_XNACK1 0x0046 +#define mmSDMA7_UTCL1_WR_XNACK1_BASE_IDX 1 +#define mmSDMA7_UTCL1_TIMEOUT 0x0047 +#define mmSDMA7_UTCL1_TIMEOUT_BASE_IDX 1 +#define mmSDMA7_UTCL1_PAGE 0x0048 +#define mmSDMA7_UTCL1_PAGE_BASE_IDX 1 +#define mmSDMA7_POWER_CNTL_IDLE 0x0049 +#define mmSDMA7_POWER_CNTL_IDLE_BASE_IDX 1 +#define mmSDMA7_RELAX_ORDERING_LUT 0x004a +#define mmSDMA7_RELAX_ORDERING_LUT_BASE_IDX 1 +#define mmSDMA7_CHICKEN_BITS_2 0x004b +#define mmSDMA7_CHICKEN_BITS_2_BASE_IDX 1 +#define mmSDMA7_STATUS3_REG 0x004c +#define mmSDMA7_STATUS3_REG_BASE_IDX 1 +#define mmSDMA7_PHYSICAL_ADDR_LO 0x004d +#define mmSDMA7_PHYSICAL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_PHYSICAL_ADDR_HI 0x004e +#define mmSDMA7_PHYSICAL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_PHASE2_QUANTUM 0x004f +#define mmSDMA7_PHASE2_QUANTUM_BASE_IDX 1 +#define mmSDMA7_ERROR_LOG 0x0050 +#define mmSDMA7_ERROR_LOG_BASE_IDX 1 +#define mmSDMA7_PUB_DUMMY_REG0 0x0051 +#define mmSDMA7_PUB_DUMMY_REG0_BASE_IDX 1 +#define mmSDMA7_PUB_DUMMY_REG1 0x0052 +#define mmSDMA7_PUB_DUMMY_REG1_BASE_IDX 1 +#define mmSDMA7_PUB_DUMMY_REG2 0x0053 +#define mmSDMA7_PUB_DUMMY_REG2_BASE_IDX 1 +#define mmSDMA7_PUB_DUMMY_REG3 0x0054 +#define mmSDMA7_PUB_DUMMY_REG3_BASE_IDX 1 +#define mmSDMA7_F32_COUNTER 0x0055 +#define mmSDMA7_F32_COUNTER_BASE_IDX 1 +#define mmSDMA7_UNBREAKABLE 0x0056 +#define mmSDMA7_UNBREAKABLE_BASE_IDX 1 +#define mmSDMA7_PERFMON_CNTL 0x0057 +#define mmSDMA7_PERFMON_CNTL_BASE_IDX 1 +#define mmSDMA7_PERFCOUNTER0_RESULT 0x0058 +#define mmSDMA7_PERFCOUNTER0_RESULT_BASE_IDX 1 +#define mmSDMA7_PERFCOUNTER1_RESULT 0x0059 +#define mmSDMA7_PERFCOUNTER1_RESULT_BASE_IDX 1 +#define mmSDMA7_PERFCOUNTER_TAG_DELAY_RANGE 0x005a +#define mmSDMA7_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 +#define mmSDMA7_CRD_CNTL 0x005b +#define mmSDMA7_CRD_CNTL_BASE_IDX 1 +#define mmSDMA7_GPU_IOV_VIOLATION_LOG 0x005d +#define mmSDMA7_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 +#define mmSDMA7_ULV_CNTL 0x005e +#define mmSDMA7_ULV_CNTL_BASE_IDX 1 +#define mmSDMA7_EA_DBIT_ADDR_DATA 0x0060 +#define mmSDMA7_EA_DBIT_ADDR_DATA_BASE_IDX 1 +#define mmSDMA7_EA_DBIT_ADDR_INDEX 0x0061 +#define mmSDMA7_EA_DBIT_ADDR_INDEX_BASE_IDX 1 +#define mmSDMA7_GPU_IOV_VIOLATION_LOG2 0x0062 +#define mmSDMA7_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 +#define mmSDMA7_GFX_RB_CNTL 0x0080 +#define mmSDMA7_GFX_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_RB_BASE 0x0081 +#define mmSDMA7_GFX_RB_BASE_BASE_IDX 1 +#define mmSDMA7_GFX_RB_BASE_HI 0x0082 +#define mmSDMA7_GFX_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_RPTR 0x0083 +#define mmSDMA7_GFX_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_GFX_RB_RPTR_HI 0x0084 +#define mmSDMA7_GFX_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR 0x0085 +#define mmSDMA7_GFX_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR_HI 0x0086 +#define mmSDMA7_GFX_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR_POLL_CNTL 0x0087 +#define mmSDMA7_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_RB_RPTR_ADDR_HI 0x0088 +#define mmSDMA7_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_RPTR_ADDR_LO 0x0089 +#define mmSDMA7_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_GFX_IB_CNTL 0x008a +#define mmSDMA7_GFX_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_IB_RPTR 0x008b +#define mmSDMA7_GFX_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_GFX_IB_OFFSET 0x008c +#define mmSDMA7_GFX_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_GFX_IB_BASE_LO 0x008d +#define mmSDMA7_GFX_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_GFX_IB_BASE_HI 0x008e +#define mmSDMA7_GFX_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_GFX_IB_SIZE 0x008f +#define mmSDMA7_GFX_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_GFX_SKIP_CNTL 0x0090 +#define mmSDMA7_GFX_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_CONTEXT_STATUS 0x0091 +#define mmSDMA7_GFX_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_GFX_DOORBELL 0x0092 +#define mmSDMA7_GFX_DOORBELL_BASE_IDX 1 +#define mmSDMA7_GFX_CONTEXT_CNTL 0x0093 +#define mmSDMA7_GFX_CONTEXT_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_STATUS 0x00a8 +#define mmSDMA7_GFX_STATUS_BASE_IDX 1 +#define mmSDMA7_GFX_DOORBELL_LOG 0x00a9 +#define mmSDMA7_GFX_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_GFX_WATERMARK 0x00aa +#define mmSDMA7_GFX_WATERMARK_BASE_IDX 1 +#define mmSDMA7_GFX_DOORBELL_OFFSET 0x00ab +#define mmSDMA7_GFX_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_GFX_CSA_ADDR_LO 0x00ac +#define mmSDMA7_GFX_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_GFX_CSA_ADDR_HI 0x00ad +#define mmSDMA7_GFX_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_IB_SUB_REMAIN 0x00af +#define mmSDMA7_GFX_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_GFX_PREEMPT 0x00b0 +#define mmSDMA7_GFX_PREEMPT_BASE_IDX 1 +#define mmSDMA7_GFX_DUMMY_REG 0x00b1 +#define mmSDMA7_GFX_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 +#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 +#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_GFX_RB_AQL_CNTL 0x00b4 +#define mmSDMA7_GFX_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_GFX_MINOR_PTR_UPDATE 0x00b5 +#define mmSDMA7_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA0 0x00c0 +#define mmSDMA7_GFX_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA1 0x00c1 +#define mmSDMA7_GFX_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA2 0x00c2 +#define mmSDMA7_GFX_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA3 0x00c3 +#define mmSDMA7_GFX_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA4 0x00c4 +#define mmSDMA7_GFX_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA5 0x00c5 +#define mmSDMA7_GFX_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA6 0x00c6 +#define mmSDMA7_GFX_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA7 0x00c7 +#define mmSDMA7_GFX_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_DATA8 0x00c8 +#define mmSDMA7_GFX_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_GFX_MIDCMD_CNTL 0x00c9 +#define mmSDMA7_GFX_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_CNTL 0x00d8 +#define mmSDMA7_PAGE_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_BASE 0x00d9 +#define mmSDMA7_PAGE_RB_BASE_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_BASE_HI 0x00da +#define mmSDMA7_PAGE_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_RPTR 0x00db +#define mmSDMA7_PAGE_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_RPTR_HI 0x00dc +#define mmSDMA7_PAGE_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR 0x00dd +#define mmSDMA7_PAGE_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR_HI 0x00de +#define mmSDMA7_PAGE_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR_POLL_CNTL 0x00df +#define mmSDMA7_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_RPTR_ADDR_HI 0x00e0 +#define mmSDMA7_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_RPTR_ADDR_LO 0x00e1 +#define mmSDMA7_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_CNTL 0x00e2 +#define mmSDMA7_PAGE_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_RPTR 0x00e3 +#define mmSDMA7_PAGE_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_OFFSET 0x00e4 +#define mmSDMA7_PAGE_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_BASE_LO 0x00e5 +#define mmSDMA7_PAGE_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_BASE_HI 0x00e6 +#define mmSDMA7_PAGE_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_SIZE 0x00e7 +#define mmSDMA7_PAGE_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_PAGE_SKIP_CNTL 0x00e8 +#define mmSDMA7_PAGE_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_CONTEXT_STATUS 0x00e9 +#define mmSDMA7_PAGE_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_PAGE_DOORBELL 0x00ea +#define mmSDMA7_PAGE_DOORBELL_BASE_IDX 1 +#define mmSDMA7_PAGE_STATUS 0x0100 +#define mmSDMA7_PAGE_STATUS_BASE_IDX 1 +#define mmSDMA7_PAGE_DOORBELL_LOG 0x0101 +#define mmSDMA7_PAGE_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_PAGE_WATERMARK 0x0102 +#define mmSDMA7_PAGE_WATERMARK_BASE_IDX 1 +#define mmSDMA7_PAGE_DOORBELL_OFFSET 0x0103 +#define mmSDMA7_PAGE_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_PAGE_CSA_ADDR_LO 0x0104 +#define mmSDMA7_PAGE_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_PAGE_CSA_ADDR_HI 0x0105 +#define mmSDMA7_PAGE_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_IB_SUB_REMAIN 0x0107 +#define mmSDMA7_PAGE_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_PAGE_PREEMPT 0x0108 +#define mmSDMA7_PAGE_PREEMPT_BASE_IDX 1 +#define mmSDMA7_PAGE_DUMMY_REG 0x0109 +#define mmSDMA7_PAGE_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a +#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b +#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_PAGE_RB_AQL_CNTL 0x010c +#define mmSDMA7_PAGE_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_PAGE_MINOR_PTR_UPDATE 0x010d +#define mmSDMA7_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA0 0x0118 +#define mmSDMA7_PAGE_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA1 0x0119 +#define mmSDMA7_PAGE_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA2 0x011a +#define mmSDMA7_PAGE_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA3 0x011b +#define mmSDMA7_PAGE_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA4 0x011c +#define mmSDMA7_PAGE_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA5 0x011d +#define mmSDMA7_PAGE_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA6 0x011e +#define mmSDMA7_PAGE_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA7 0x011f +#define mmSDMA7_PAGE_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_DATA8 0x0120 +#define mmSDMA7_PAGE_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_PAGE_MIDCMD_CNTL 0x0121 +#define mmSDMA7_PAGE_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_CNTL 0x0130 +#define mmSDMA7_RLC0_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_BASE 0x0131 +#define mmSDMA7_RLC0_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_BASE_HI 0x0132 +#define mmSDMA7_RLC0_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_RPTR 0x0133 +#define mmSDMA7_RLC0_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_RPTR_HI 0x0134 +#define mmSDMA7_RLC0_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR 0x0135 +#define mmSDMA7_RLC0_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR_HI 0x0136 +#define mmSDMA7_RLC0_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR_POLL_CNTL 0x0137 +#define mmSDMA7_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_RPTR_ADDR_HI 0x0138 +#define mmSDMA7_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_RPTR_ADDR_LO 0x0139 +#define mmSDMA7_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_CNTL 0x013a +#define mmSDMA7_RLC0_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_RPTR 0x013b +#define mmSDMA7_RLC0_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_OFFSET 0x013c +#define mmSDMA7_RLC0_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_BASE_LO 0x013d +#define mmSDMA7_RLC0_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_BASE_HI 0x013e +#define mmSDMA7_RLC0_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_SIZE 0x013f +#define mmSDMA7_RLC0_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC0_SKIP_CNTL 0x0140 +#define mmSDMA7_RLC0_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_CONTEXT_STATUS 0x0141 +#define mmSDMA7_RLC0_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC0_DOORBELL 0x0142 +#define mmSDMA7_RLC0_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC0_STATUS 0x0158 +#define mmSDMA7_RLC0_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC0_DOORBELL_LOG 0x0159 +#define mmSDMA7_RLC0_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC0_WATERMARK 0x015a +#define mmSDMA7_RLC0_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC0_DOORBELL_OFFSET 0x015b +#define mmSDMA7_RLC0_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC0_CSA_ADDR_LO 0x015c +#define mmSDMA7_RLC0_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC0_CSA_ADDR_HI 0x015d +#define mmSDMA7_RLC0_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_IB_SUB_REMAIN 0x015f +#define mmSDMA7_RLC0_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC0_PREEMPT 0x0160 +#define mmSDMA7_RLC0_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC0_DUMMY_REG 0x0161 +#define mmSDMA7_RLC0_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 +#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 +#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC0_RB_AQL_CNTL 0x0164 +#define mmSDMA7_RLC0_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC0_MINOR_PTR_UPDATE 0x0165 +#define mmSDMA7_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA0 0x0170 +#define mmSDMA7_RLC0_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA1 0x0171 +#define mmSDMA7_RLC0_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA2 0x0172 +#define mmSDMA7_RLC0_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA3 0x0173 +#define mmSDMA7_RLC0_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA4 0x0174 +#define mmSDMA7_RLC0_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA5 0x0175 +#define mmSDMA7_RLC0_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA6 0x0176 +#define mmSDMA7_RLC0_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA7 0x0177 +#define mmSDMA7_RLC0_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_DATA8 0x0178 +#define mmSDMA7_RLC0_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC0_MIDCMD_CNTL 0x0179 +#define mmSDMA7_RLC0_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_CNTL 0x0188 +#define mmSDMA7_RLC1_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_BASE 0x0189 +#define mmSDMA7_RLC1_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_BASE_HI 0x018a +#define mmSDMA7_RLC1_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_RPTR 0x018b +#define mmSDMA7_RLC1_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_RPTR_HI 0x018c +#define mmSDMA7_RLC1_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR 0x018d +#define mmSDMA7_RLC1_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR_HI 0x018e +#define mmSDMA7_RLC1_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR_POLL_CNTL 0x018f +#define mmSDMA7_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_RPTR_ADDR_HI 0x0190 +#define mmSDMA7_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_RPTR_ADDR_LO 0x0191 +#define mmSDMA7_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_CNTL 0x0192 +#define mmSDMA7_RLC1_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_RPTR 0x0193 +#define mmSDMA7_RLC1_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_OFFSET 0x0194 +#define mmSDMA7_RLC1_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_BASE_LO 0x0195 +#define mmSDMA7_RLC1_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_BASE_HI 0x0196 +#define mmSDMA7_RLC1_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_SIZE 0x0197 +#define mmSDMA7_RLC1_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC1_SKIP_CNTL 0x0198 +#define mmSDMA7_RLC1_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_CONTEXT_STATUS 0x0199 +#define mmSDMA7_RLC1_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC1_DOORBELL 0x019a +#define mmSDMA7_RLC1_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC1_STATUS 0x01b0 +#define mmSDMA7_RLC1_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC1_DOORBELL_LOG 0x01b1 +#define mmSDMA7_RLC1_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC1_WATERMARK 0x01b2 +#define mmSDMA7_RLC1_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC1_DOORBELL_OFFSET 0x01b3 +#define mmSDMA7_RLC1_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC1_CSA_ADDR_LO 0x01b4 +#define mmSDMA7_RLC1_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC1_CSA_ADDR_HI 0x01b5 +#define mmSDMA7_RLC1_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_IB_SUB_REMAIN 0x01b7 +#define mmSDMA7_RLC1_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC1_PREEMPT 0x01b8 +#define mmSDMA7_RLC1_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC1_DUMMY_REG 0x01b9 +#define mmSDMA7_RLC1_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba +#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb +#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC1_RB_AQL_CNTL 0x01bc +#define mmSDMA7_RLC1_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC1_MINOR_PTR_UPDATE 0x01bd +#define mmSDMA7_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA0 0x01c8 +#define mmSDMA7_RLC1_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA1 0x01c9 +#define mmSDMA7_RLC1_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA2 0x01ca +#define mmSDMA7_RLC1_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA3 0x01cb +#define mmSDMA7_RLC1_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA4 0x01cc +#define mmSDMA7_RLC1_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA5 0x01cd +#define mmSDMA7_RLC1_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA6 0x01ce +#define mmSDMA7_RLC1_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA7 0x01cf +#define mmSDMA7_RLC1_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_DATA8 0x01d0 +#define mmSDMA7_RLC1_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC1_MIDCMD_CNTL 0x01d1 +#define mmSDMA7_RLC1_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_CNTL 0x01e0 +#define mmSDMA7_RLC2_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_BASE 0x01e1 +#define mmSDMA7_RLC2_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_BASE_HI 0x01e2 +#define mmSDMA7_RLC2_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_RPTR 0x01e3 +#define mmSDMA7_RLC2_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_RPTR_HI 0x01e4 +#define mmSDMA7_RLC2_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR 0x01e5 +#define mmSDMA7_RLC2_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR_HI 0x01e6 +#define mmSDMA7_RLC2_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR_POLL_CNTL 0x01e7 +#define mmSDMA7_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_RPTR_ADDR_HI 0x01e8 +#define mmSDMA7_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_RPTR_ADDR_LO 0x01e9 +#define mmSDMA7_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_CNTL 0x01ea +#define mmSDMA7_RLC2_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_RPTR 0x01eb +#define mmSDMA7_RLC2_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_OFFSET 0x01ec +#define mmSDMA7_RLC2_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_BASE_LO 0x01ed +#define mmSDMA7_RLC2_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_BASE_HI 0x01ee +#define mmSDMA7_RLC2_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_SIZE 0x01ef +#define mmSDMA7_RLC2_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC2_SKIP_CNTL 0x01f0 +#define mmSDMA7_RLC2_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_CONTEXT_STATUS 0x01f1 +#define mmSDMA7_RLC2_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC2_DOORBELL 0x01f2 +#define mmSDMA7_RLC2_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC2_STATUS 0x0208 +#define mmSDMA7_RLC2_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC2_DOORBELL_LOG 0x0209 +#define mmSDMA7_RLC2_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC2_WATERMARK 0x020a +#define mmSDMA7_RLC2_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC2_DOORBELL_OFFSET 0x020b +#define mmSDMA7_RLC2_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC2_CSA_ADDR_LO 0x020c +#define mmSDMA7_RLC2_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC2_CSA_ADDR_HI 0x020d +#define mmSDMA7_RLC2_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_IB_SUB_REMAIN 0x020f +#define mmSDMA7_RLC2_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC2_PREEMPT 0x0210 +#define mmSDMA7_RLC2_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC2_DUMMY_REG 0x0211 +#define mmSDMA7_RLC2_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 +#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 +#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC2_RB_AQL_CNTL 0x0214 +#define mmSDMA7_RLC2_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC2_MINOR_PTR_UPDATE 0x0215 +#define mmSDMA7_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA0 0x0220 +#define mmSDMA7_RLC2_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA1 0x0221 +#define mmSDMA7_RLC2_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA2 0x0222 +#define mmSDMA7_RLC2_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA3 0x0223 +#define mmSDMA7_RLC2_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA4 0x0224 +#define mmSDMA7_RLC2_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA5 0x0225 +#define mmSDMA7_RLC2_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA6 0x0226 +#define mmSDMA7_RLC2_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA7 0x0227 +#define mmSDMA7_RLC2_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_DATA8 0x0228 +#define mmSDMA7_RLC2_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC2_MIDCMD_CNTL 0x0229 +#define mmSDMA7_RLC2_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_CNTL 0x0238 +#define mmSDMA7_RLC3_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_BASE 0x0239 +#define mmSDMA7_RLC3_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_BASE_HI 0x023a +#define mmSDMA7_RLC3_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_RPTR 0x023b +#define mmSDMA7_RLC3_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_RPTR_HI 0x023c +#define mmSDMA7_RLC3_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR 0x023d +#define mmSDMA7_RLC3_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR_HI 0x023e +#define mmSDMA7_RLC3_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR_POLL_CNTL 0x023f +#define mmSDMA7_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_RPTR_ADDR_HI 0x0240 +#define mmSDMA7_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_RPTR_ADDR_LO 0x0241 +#define mmSDMA7_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_CNTL 0x0242 +#define mmSDMA7_RLC3_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_RPTR 0x0243 +#define mmSDMA7_RLC3_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_OFFSET 0x0244 +#define mmSDMA7_RLC3_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_BASE_LO 0x0245 +#define mmSDMA7_RLC3_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_BASE_HI 0x0246 +#define mmSDMA7_RLC3_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_SIZE 0x0247 +#define mmSDMA7_RLC3_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC3_SKIP_CNTL 0x0248 +#define mmSDMA7_RLC3_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_CONTEXT_STATUS 0x0249 +#define mmSDMA7_RLC3_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC3_DOORBELL 0x024a +#define mmSDMA7_RLC3_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC3_STATUS 0x0260 +#define mmSDMA7_RLC3_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC3_DOORBELL_LOG 0x0261 +#define mmSDMA7_RLC3_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC3_WATERMARK 0x0262 +#define mmSDMA7_RLC3_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC3_DOORBELL_OFFSET 0x0263 +#define mmSDMA7_RLC3_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC3_CSA_ADDR_LO 0x0264 +#define mmSDMA7_RLC3_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC3_CSA_ADDR_HI 0x0265 +#define mmSDMA7_RLC3_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_IB_SUB_REMAIN 0x0267 +#define mmSDMA7_RLC3_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC3_PREEMPT 0x0268 +#define mmSDMA7_RLC3_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC3_DUMMY_REG 0x0269 +#define mmSDMA7_RLC3_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a +#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b +#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC3_RB_AQL_CNTL 0x026c +#define mmSDMA7_RLC3_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC3_MINOR_PTR_UPDATE 0x026d +#define mmSDMA7_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA0 0x0278 +#define mmSDMA7_RLC3_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA1 0x0279 +#define mmSDMA7_RLC3_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA2 0x027a +#define mmSDMA7_RLC3_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA3 0x027b +#define mmSDMA7_RLC3_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA4 0x027c +#define mmSDMA7_RLC3_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA5 0x027d +#define mmSDMA7_RLC3_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA6 0x027e +#define mmSDMA7_RLC3_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA7 0x027f +#define mmSDMA7_RLC3_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_DATA8 0x0280 +#define mmSDMA7_RLC3_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC3_MIDCMD_CNTL 0x0281 +#define mmSDMA7_RLC3_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_CNTL 0x0290 +#define mmSDMA7_RLC4_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_BASE 0x0291 +#define mmSDMA7_RLC4_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_BASE_HI 0x0292 +#define mmSDMA7_RLC4_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_RPTR 0x0293 +#define mmSDMA7_RLC4_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_RPTR_HI 0x0294 +#define mmSDMA7_RLC4_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR 0x0295 +#define mmSDMA7_RLC4_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR_HI 0x0296 +#define mmSDMA7_RLC4_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR_POLL_CNTL 0x0297 +#define mmSDMA7_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_RPTR_ADDR_HI 0x0298 +#define mmSDMA7_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_RPTR_ADDR_LO 0x0299 +#define mmSDMA7_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_CNTL 0x029a +#define mmSDMA7_RLC4_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_RPTR 0x029b +#define mmSDMA7_RLC4_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_OFFSET 0x029c +#define mmSDMA7_RLC4_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_BASE_LO 0x029d +#define mmSDMA7_RLC4_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_BASE_HI 0x029e +#define mmSDMA7_RLC4_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_SIZE 0x029f +#define mmSDMA7_RLC4_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC4_SKIP_CNTL 0x02a0 +#define mmSDMA7_RLC4_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_CONTEXT_STATUS 0x02a1 +#define mmSDMA7_RLC4_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC4_DOORBELL 0x02a2 +#define mmSDMA7_RLC4_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC4_STATUS 0x02b8 +#define mmSDMA7_RLC4_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC4_DOORBELL_LOG 0x02b9 +#define mmSDMA7_RLC4_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC4_WATERMARK 0x02ba +#define mmSDMA7_RLC4_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC4_DOORBELL_OFFSET 0x02bb +#define mmSDMA7_RLC4_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC4_CSA_ADDR_LO 0x02bc +#define mmSDMA7_RLC4_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC4_CSA_ADDR_HI 0x02bd +#define mmSDMA7_RLC4_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_IB_SUB_REMAIN 0x02bf +#define mmSDMA7_RLC4_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC4_PREEMPT 0x02c0 +#define mmSDMA7_RLC4_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC4_DUMMY_REG 0x02c1 +#define mmSDMA7_RLC4_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 +#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 +#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC4_RB_AQL_CNTL 0x02c4 +#define mmSDMA7_RLC4_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC4_MINOR_PTR_UPDATE 0x02c5 +#define mmSDMA7_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA0 0x02d0 +#define mmSDMA7_RLC4_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA1 0x02d1 +#define mmSDMA7_RLC4_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA2 0x02d2 +#define mmSDMA7_RLC4_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA3 0x02d3 +#define mmSDMA7_RLC4_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA4 0x02d4 +#define mmSDMA7_RLC4_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA5 0x02d5 +#define mmSDMA7_RLC4_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA6 0x02d6 +#define mmSDMA7_RLC4_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA7 0x02d7 +#define mmSDMA7_RLC4_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_DATA8 0x02d8 +#define mmSDMA7_RLC4_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC4_MIDCMD_CNTL 0x02d9 +#define mmSDMA7_RLC4_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_CNTL 0x02e8 +#define mmSDMA7_RLC5_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_BASE 0x02e9 +#define mmSDMA7_RLC5_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_BASE_HI 0x02ea +#define mmSDMA7_RLC5_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_RPTR 0x02eb +#define mmSDMA7_RLC5_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_RPTR_HI 0x02ec +#define mmSDMA7_RLC5_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR 0x02ed +#define mmSDMA7_RLC5_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR_HI 0x02ee +#define mmSDMA7_RLC5_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR_POLL_CNTL 0x02ef +#define mmSDMA7_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_RPTR_ADDR_HI 0x02f0 +#define mmSDMA7_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_RPTR_ADDR_LO 0x02f1 +#define mmSDMA7_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_CNTL 0x02f2 +#define mmSDMA7_RLC5_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_RPTR 0x02f3 +#define mmSDMA7_RLC5_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_OFFSET 0x02f4 +#define mmSDMA7_RLC5_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_BASE_LO 0x02f5 +#define mmSDMA7_RLC5_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_BASE_HI 0x02f6 +#define mmSDMA7_RLC5_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_SIZE 0x02f7 +#define mmSDMA7_RLC5_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC5_SKIP_CNTL 0x02f8 +#define mmSDMA7_RLC5_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_CONTEXT_STATUS 0x02f9 +#define mmSDMA7_RLC5_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC5_DOORBELL 0x02fa +#define mmSDMA7_RLC5_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC5_STATUS 0x0310 +#define mmSDMA7_RLC5_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC5_DOORBELL_LOG 0x0311 +#define mmSDMA7_RLC5_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC5_WATERMARK 0x0312 +#define mmSDMA7_RLC5_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC5_DOORBELL_OFFSET 0x0313 +#define mmSDMA7_RLC5_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC5_CSA_ADDR_LO 0x0314 +#define mmSDMA7_RLC5_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC5_CSA_ADDR_HI 0x0315 +#define mmSDMA7_RLC5_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_IB_SUB_REMAIN 0x0317 +#define mmSDMA7_RLC5_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC5_PREEMPT 0x0318 +#define mmSDMA7_RLC5_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC5_DUMMY_REG 0x0319 +#define mmSDMA7_RLC5_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a +#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b +#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC5_RB_AQL_CNTL 0x031c +#define mmSDMA7_RLC5_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC5_MINOR_PTR_UPDATE 0x031d +#define mmSDMA7_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA0 0x0328 +#define mmSDMA7_RLC5_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA1 0x0329 +#define mmSDMA7_RLC5_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA2 0x032a +#define mmSDMA7_RLC5_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA3 0x032b +#define mmSDMA7_RLC5_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA4 0x032c +#define mmSDMA7_RLC5_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA5 0x032d +#define mmSDMA7_RLC5_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA6 0x032e +#define mmSDMA7_RLC5_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA7 0x032f +#define mmSDMA7_RLC5_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_DATA8 0x0330 +#define mmSDMA7_RLC5_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC5_MIDCMD_CNTL 0x0331 +#define mmSDMA7_RLC5_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_CNTL 0x0340 +#define mmSDMA7_RLC6_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_BASE 0x0341 +#define mmSDMA7_RLC6_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_BASE_HI 0x0342 +#define mmSDMA7_RLC6_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_RPTR 0x0343 +#define mmSDMA7_RLC6_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_RPTR_HI 0x0344 +#define mmSDMA7_RLC6_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR 0x0345 +#define mmSDMA7_RLC6_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR_HI 0x0346 +#define mmSDMA7_RLC6_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR_POLL_CNTL 0x0347 +#define mmSDMA7_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_RPTR_ADDR_HI 0x0348 +#define mmSDMA7_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_RPTR_ADDR_LO 0x0349 +#define mmSDMA7_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_CNTL 0x034a +#define mmSDMA7_RLC6_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_RPTR 0x034b +#define mmSDMA7_RLC6_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_OFFSET 0x034c +#define mmSDMA7_RLC6_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_BASE_LO 0x034d +#define mmSDMA7_RLC6_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_BASE_HI 0x034e +#define mmSDMA7_RLC6_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_SIZE 0x034f +#define mmSDMA7_RLC6_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC6_SKIP_CNTL 0x0350 +#define mmSDMA7_RLC6_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_CONTEXT_STATUS 0x0351 +#define mmSDMA7_RLC6_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC6_DOORBELL 0x0352 +#define mmSDMA7_RLC6_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC6_STATUS 0x0368 +#define mmSDMA7_RLC6_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC6_DOORBELL_LOG 0x0369 +#define mmSDMA7_RLC6_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC6_WATERMARK 0x036a +#define mmSDMA7_RLC6_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC6_DOORBELL_OFFSET 0x036b +#define mmSDMA7_RLC6_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC6_CSA_ADDR_LO 0x036c +#define mmSDMA7_RLC6_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC6_CSA_ADDR_HI 0x036d +#define mmSDMA7_RLC6_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_IB_SUB_REMAIN 0x036f +#define mmSDMA7_RLC6_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC6_PREEMPT 0x0370 +#define mmSDMA7_RLC6_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC6_DUMMY_REG 0x0371 +#define mmSDMA7_RLC6_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 +#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 +#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC6_RB_AQL_CNTL 0x0374 +#define mmSDMA7_RLC6_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC6_MINOR_PTR_UPDATE 0x0375 +#define mmSDMA7_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA0 0x0380 +#define mmSDMA7_RLC6_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA1 0x0381 +#define mmSDMA7_RLC6_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA2 0x0382 +#define mmSDMA7_RLC6_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA3 0x0383 +#define mmSDMA7_RLC6_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA4 0x0384 +#define mmSDMA7_RLC6_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA5 0x0385 +#define mmSDMA7_RLC6_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA6 0x0386 +#define mmSDMA7_RLC6_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA7 0x0387 +#define mmSDMA7_RLC6_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_DATA8 0x0388 +#define mmSDMA7_RLC6_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC6_MIDCMD_CNTL 0x0389 +#define mmSDMA7_RLC6_MIDCMD_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_CNTL 0x0398 +#define mmSDMA7_RLC7_RB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_BASE 0x0399 +#define mmSDMA7_RLC7_RB_BASE_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_BASE_HI 0x039a +#define mmSDMA7_RLC7_RB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_RPTR 0x039b +#define mmSDMA7_RLC7_RB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_RPTR_HI 0x039c +#define mmSDMA7_RLC7_RB_RPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR 0x039d +#define mmSDMA7_RLC7_RB_WPTR_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR_HI 0x039e +#define mmSDMA7_RLC7_RB_WPTR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR_POLL_CNTL 0x039f +#define mmSDMA7_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_RPTR_ADDR_HI 0x03a0 +#define mmSDMA7_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_RPTR_ADDR_LO 0x03a1 +#define mmSDMA7_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_CNTL 0x03a2 +#define mmSDMA7_RLC7_IB_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_RPTR 0x03a3 +#define mmSDMA7_RLC7_IB_RPTR_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_OFFSET 0x03a4 +#define mmSDMA7_RLC7_IB_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_BASE_LO 0x03a5 +#define mmSDMA7_RLC7_IB_BASE_LO_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_BASE_HI 0x03a6 +#define mmSDMA7_RLC7_IB_BASE_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_SIZE 0x03a7 +#define mmSDMA7_RLC7_IB_SIZE_BASE_IDX 1 +#define mmSDMA7_RLC7_SKIP_CNTL 0x03a8 +#define mmSDMA7_RLC7_SKIP_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_CONTEXT_STATUS 0x03a9 +#define mmSDMA7_RLC7_CONTEXT_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC7_DOORBELL 0x03aa +#define mmSDMA7_RLC7_DOORBELL_BASE_IDX 1 +#define mmSDMA7_RLC7_STATUS 0x03c0 +#define mmSDMA7_RLC7_STATUS_BASE_IDX 1 +#define mmSDMA7_RLC7_DOORBELL_LOG 0x03c1 +#define mmSDMA7_RLC7_DOORBELL_LOG_BASE_IDX 1 +#define mmSDMA7_RLC7_WATERMARK 0x03c2 +#define mmSDMA7_RLC7_WATERMARK_BASE_IDX 1 +#define mmSDMA7_RLC7_DOORBELL_OFFSET 0x03c3 +#define mmSDMA7_RLC7_DOORBELL_OFFSET_BASE_IDX 1 +#define mmSDMA7_RLC7_CSA_ADDR_LO 0x03c4 +#define mmSDMA7_RLC7_CSA_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC7_CSA_ADDR_HI 0x03c5 +#define mmSDMA7_RLC7_CSA_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_IB_SUB_REMAIN 0x03c7 +#define mmSDMA7_RLC7_IB_SUB_REMAIN_BASE_IDX 1 +#define mmSDMA7_RLC7_PREEMPT 0x03c8 +#define mmSDMA7_RLC7_PREEMPT_BASE_IDX 1 +#define mmSDMA7_RLC7_DUMMY_REG 0x03c9 +#define mmSDMA7_RLC7_DUMMY_REG_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca +#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb +#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 +#define mmSDMA7_RLC7_RB_AQL_CNTL 0x03cc +#define mmSDMA7_RLC7_RB_AQL_CNTL_BASE_IDX 1 +#define mmSDMA7_RLC7_MINOR_PTR_UPDATE 0x03cd +#define mmSDMA7_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA0 0x03d8 +#define mmSDMA7_RLC7_MIDCMD_DATA0_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA1 0x03d9 +#define mmSDMA7_RLC7_MIDCMD_DATA1_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA2 0x03da +#define mmSDMA7_RLC7_MIDCMD_DATA2_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA3 0x03db +#define mmSDMA7_RLC7_MIDCMD_DATA3_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA4 0x03dc +#define mmSDMA7_RLC7_MIDCMD_DATA4_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA5 0x03dd +#define mmSDMA7_RLC7_MIDCMD_DATA5_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA6 0x03de +#define mmSDMA7_RLC7_MIDCMD_DATA6_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA7 0x03df +#define mmSDMA7_RLC7_MIDCMD_DATA7_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_DATA8 0x03e0 +#define mmSDMA7_RLC7_MIDCMD_DATA8_BASE_IDX 1 +#define mmSDMA7_RLC7_MIDCMD_CNTL 0x03e1 +#define mmSDMA7_RLC7_MIDCMD_CNTL_BASE_IDX 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h new file mode 100644 index 000000000000..4b56d8c67d91 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h @@ -0,0 +1,2956 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _sdma7_4_2_2_SH_MASK_HEADER +#define _sdma7_4_2_2_SH_MASK_HEADER + + +// addressBlock: sdma7_sdma7dec +//SDMA7_UCODE_ADDR +#define SDMA7_UCODE_ADDR__VALUE__SHIFT 0x0 +#define SDMA7_UCODE_ADDR__VALUE_MASK 0x00001FFFL +//SDMA7_UCODE_DATA +#define SDMA7_UCODE_DATA__VALUE__SHIFT 0x0 +#define SDMA7_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA7_VM_CNTL +#define SDMA7_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA7_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA7_VM_CTX_LO +#define SDMA7_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA7_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_VM_CTX_HI +#define SDMA7_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA7_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_ACTIVE_FCN_ID +#define SDMA7_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA7_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define SDMA7_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define SDMA7_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +#define SDMA7_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L +#define SDMA7_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//SDMA7_VM_CTX_CNTL +#define SDMA7_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA7_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA7_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA7_VM_CTX_CNTL__VMID_MASK 0x000000F0L +//SDMA7_VIRT_RESET_REQ +#define SDMA7_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA7_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA7_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL +#define SDMA7_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA7_VF_ENABLE +#define SDMA7_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define SDMA7_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +//SDMA7_CONTEXT_REG_TYPE0 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_CNTL__SHIFT 0x0 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE__SHIFT 0x1 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_HI__SHIFT 0x2 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR__SHIFT 0x3 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_HI__SHIFT 0x4 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR__SHIFT 0x5 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_HI__SHIFT 0x6 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL__SHIFT 0xa +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_RPTR__SHIFT 0xb +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_OFFSET__SHIFT 0xc +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_LO__SHIFT 0xd +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_HI__SHIFT 0xe +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_SIZE__SHIFT 0xf +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_SKIP_CNTL__SHIFT 0x10 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_DOORBELL__SHIFT 0x12 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_CNTL__SHIFT 0x13 +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_CNTL_MASK 0x00000001L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_MASK 0x00000002L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_HI_MASK 0x00000004L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_MASK 0x00000008L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_HI_MASK 0x00000010L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_MASK 0x00000020L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_HI_MASK 0x00000040L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL_MASK 0x00000400L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_RPTR_MASK 0x00000800L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_OFFSET_MASK 0x00001000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_LO_MASK 0x00002000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_HI_MASK 0x00004000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_SIZE_MASK 0x00008000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_SKIP_CNTL_MASK 0x00010000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_DOORBELL_MASK 0x00040000L +#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_CNTL_MASK 0x00080000L +//SDMA7_CONTEXT_REG_TYPE1 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_STATUS__SHIFT 0x8 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_LOG__SHIFT 0x9 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK__SHIFT 0xa +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_OFFSET__SHIFT 0xb +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_LO__SHIFT 0xc +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_HI__SHIFT 0xd +#define SDMA7_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_IB_SUB_REMAIN__SHIFT 0xf +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_PREEMPT__SHIFT 0x10 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DUMMY_REG__SHIFT 0x11 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_AQL_CNTL__SHIFT 0x14 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 +#define SDMA7_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_STATUS_MASK 0x00000100L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_LOG_MASK 0x00000200L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK_MASK 0x00000400L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_OFFSET_MASK 0x00000800L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_LO_MASK 0x00001000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_HI_MASK 0x00002000L +#define SDMA7_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_IB_SUB_REMAIN_MASK 0x00008000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_PREEMPT_MASK 0x00010000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DUMMY_REG_MASK 0x00020000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_AQL_CNTL_MASK 0x00100000L +#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L +#define SDMA7_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L +//SDMA7_CONTEXT_REG_TYPE2 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_CNTL__SHIFT 0x9 +#define SDMA7_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_CNTL_MASK 0x00000200L +#define SDMA7_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L +//SDMA7_CONTEXT_REG_TYPE3 +#define SDMA7_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 +#define SDMA7_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL +//SDMA7_PUB_REG_TYPE0 +#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_ADDR__SHIFT 0x0 +#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_DATA__SHIFT 0x1 +#define SDMA7_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CNTL__SHIFT 0x4 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_LO__SHIFT 0x5 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_HI__SHIFT 0x6 +#define SDMA7_PUB_REG_TYPE0__SDMA7_ACTIVE_FCN_ID__SHIFT 0x7 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_CNTL__SHIFT 0x8 +#define SDMA7_PUB_REG_TYPE0__SDMA7_VIRT_RESET_REQ__SHIFT 0x9 +#define SDMA7_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE0__SHIFT 0xb +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE1__SHIFT 0xc +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE2__SHIFT 0xd +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE3__SHIFT 0xe +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE0__SHIFT 0xf +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE1__SHIFT 0x10 +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE2__SHIFT 0x11 +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE3__SHIFT 0x12 +#define SDMA7_PUB_REG_TYPE0__SDMA7_MMHUB_CNTL__SHIFT 0x13 +#define SDMA7_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x15 +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 +#define SDMA7_PUB_REG_TYPE0__SDMA7_POWER_CNTL__SHIFT 0x1a +#define SDMA7_PUB_REG_TYPE0__SDMA7_CLK_CTRL__SHIFT 0x1b +#define SDMA7_PUB_REG_TYPE0__SDMA7_CNTL__SHIFT 0x1c +#define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS__SHIFT 0x1d +#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG__SHIFT 0x1e +#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_READ__SHIFT 0x1f +#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_ADDR_MASK 0x00000001L +#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_DATA_MASK 0x00000002L +#define SDMA7_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CNTL_MASK 0x00000010L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_LO_MASK 0x00000020L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_HI_MASK 0x00000040L +#define SDMA7_PUB_REG_TYPE0__SDMA7_ACTIVE_FCN_ID_MASK 0x00000080L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_CNTL_MASK 0x00000100L +#define SDMA7_PUB_REG_TYPE0__SDMA7_VIRT_RESET_REQ_MASK 0x00000200L +#define SDMA7_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE0_MASK 0x00000800L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE1_MASK 0x00001000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE2_MASK 0x00002000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE3_MASK 0x00004000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE0_MASK 0x00008000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE1_MASK 0x00010000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE2_MASK 0x00020000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE3_MASK 0x00040000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_MMHUB_CNTL_MASK 0x00080000L +#define SDMA7_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01E00000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_POWER_CNTL_MASK 0x04000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CLK_CTRL_MASK 0x08000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CNTL_MASK 0x10000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS_MASK 0x20000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_MASK 0x40000000L +#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_READ_MASK 0x80000000L +//SDMA7_PUB_REG_TYPE1 +#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_HI__SHIFT 0x0 +#define SDMA7_PUB_REG_TYPE1__SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 +#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH__SHIFT 0x2 +#define SDMA7_PUB_REG_TYPE1__SDMA7_IB_OFFSET_FETCH__SHIFT 0x3 +#define SDMA7_PUB_REG_TYPE1__SDMA7_PROGRAM__SHIFT 0x4 +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS_REG__SHIFT 0x5 +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS1_REG__SHIFT 0x6 +#define SDMA7_PUB_REG_TYPE1__SDMA7_RD_BURST_CNTL__SHIFT 0x7 +#define SDMA7_PUB_REG_TYPE1__SDMA7_HBM_PAGE_CONFIG__SHIFT 0x8 +#define SDMA7_PUB_REG_TYPE1__SDMA7_UCODE_CHECKSUM__SHIFT 0x9 +#define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL__SHIFT 0xa +#define SDMA7_PUB_REG_TYPE1__SDMA7_FREEZE__SHIFT 0xb +#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE0_QUANTUM__SHIFT 0xc +#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE1_QUANTUM__SHIFT 0xd +#define SDMA7_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_CONFIG__SHIFT 0x12 +#define SDMA7_PUB_REG_TYPE1__SDMA7_BA_THRESHOLD__SHIFT 0x13 +#define SDMA7_PUB_REG_TYPE1__SDMA7_ID__SHIFT 0x14 +#define SDMA7_PUB_REG_TYPE1__SDMA7_VERSION__SHIFT 0x15 +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER__SHIFT 0x16 +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_CLEAR__SHIFT 0x17 +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS2_REG__SHIFT 0x18 +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_CNTL__SHIFT 0x19 +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_LO__SHIFT 0x1a +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_HI__SHIFT 0x1b +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_CNTL__SHIFT 0x1c +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK__SHIFT 0x1d +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_RD_STATUS__SHIFT 0x1e +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WR_STATUS__SHIFT 0x1f +#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_HI_MASK 0x00000001L +#define SDMA7_PUB_REG_TYPE1__SDMA7_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L +#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_MASK 0x00000004L +#define SDMA7_PUB_REG_TYPE1__SDMA7_IB_OFFSET_FETCH_MASK 0x00000008L +#define SDMA7_PUB_REG_TYPE1__SDMA7_PROGRAM_MASK 0x00000010L +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS_REG_MASK 0x00000020L +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS1_REG_MASK 0x00000040L +#define SDMA7_PUB_REG_TYPE1__SDMA7_RD_BURST_CNTL_MASK 0x00000080L +#define SDMA7_PUB_REG_TYPE1__SDMA7_HBM_PAGE_CONFIG_MASK 0x00000100L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UCODE_CHECKSUM_MASK 0x00000200L +#define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL_MASK 0x00000400L +#define SDMA7_PUB_REG_TYPE1__SDMA7_FREEZE_MASK 0x00000800L +#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE0_QUANTUM_MASK 0x00001000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE1_QUANTUM_MASK 0x00002000L +#define SDMA7_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L +#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_CONFIG_MASK 0x00040000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_BA_THRESHOLD_MASK 0x00080000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_ID_MASK 0x00100000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_VERSION_MASK 0x00200000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_MASK 0x00400000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_CLEAR_MASK 0x00800000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS2_REG_MASK 0x01000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_CNTL_MASK 0x02000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_LO_MASK 0x04000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_HI_MASK 0x08000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_CNTL_MASK 0x10000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK_MASK 0x20000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_RD_STATUS_MASK 0x40000000L +#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WR_STATUS_MASK 0x80000000L +//SDMA7_PUB_REG_TYPE2 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV0__SHIFT 0x0 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV1__SHIFT 0x1 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV2__SHIFT 0x2 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK0__SHIFT 0x3 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK1__SHIFT 0x4 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK0__SHIFT 0x5 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK1__SHIFT 0x6 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_TIMEOUT__SHIFT 0x7 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_PAGE__SHIFT 0x8 +#define SDMA7_PUB_REG_TYPE2__SDMA7_POWER_CNTL_IDLE__SHIFT 0x9 +#define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT__SHIFT 0xa +#define SDMA7_PUB_REG_TYPE2__SDMA7_CHICKEN_BITS_2__SHIFT 0xb +#define SDMA7_PUB_REG_TYPE2__SDMA7_STATUS3_REG__SHIFT 0xc +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_LO__SHIFT 0xd +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_HI__SHIFT 0xe +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHASE2_QUANTUM__SHIFT 0xf +#define SDMA7_PUB_REG_TYPE2__SDMA7_ERROR_LOG__SHIFT 0x10 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG0__SHIFT 0x11 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG1__SHIFT 0x12 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG2__SHIFT 0x13 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG3__SHIFT 0x14 +#define SDMA7_PUB_REG_TYPE2__SDMA7_F32_COUNTER__SHIFT 0x15 +#define SDMA7_PUB_REG_TYPE2__SDMA7_UNBREAKABLE__SHIFT 0x16 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFMON_CNTL__SHIFT 0x17 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER0_RESULT__SHIFT 0x18 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER1_RESULT__SHIFT 0x19 +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a +#define SDMA7_PUB_REG_TYPE2__SDMA7_CRD_CNTL__SHIFT 0x1b +#define SDMA7_PUB_REG_TYPE2__RESERVED28__SHIFT 0x1c +#define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d +#define SDMA7_PUB_REG_TYPE2__SDMA7_ULV_CNTL__SHIFT 0x1e +#define SDMA7_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV0_MASK 0x00000001L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV1_MASK 0x00000002L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV2_MASK 0x00000004L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK0_MASK 0x00000008L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK1_MASK 0x00000010L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK0_MASK 0x00000020L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK1_MASK 0x00000040L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_TIMEOUT_MASK 0x00000080L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_PAGE_MASK 0x00000100L +#define SDMA7_PUB_REG_TYPE2__SDMA7_POWER_CNTL_IDLE_MASK 0x00000200L +#define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT_MASK 0x00000400L +#define SDMA7_PUB_REG_TYPE2__SDMA7_CHICKEN_BITS_2_MASK 0x00000800L +#define SDMA7_PUB_REG_TYPE2__SDMA7_STATUS3_REG_MASK 0x00001000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_LO_MASK 0x00002000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_HI_MASK 0x00004000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PHASE2_QUANTUM_MASK 0x00008000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_ERROR_LOG_MASK 0x00010000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG0_MASK 0x00020000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG1_MASK 0x00040000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG2_MASK 0x00080000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG3_MASK 0x00100000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_F32_COUNTER_MASK 0x00200000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_UNBREAKABLE_MASK 0x00400000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFMON_CNTL_MASK 0x00800000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER0_RESULT_MASK 0x01000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER1_RESULT_MASK 0x02000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_CRD_CNTL_MASK 0x08000000L +#define SDMA7_PUB_REG_TYPE2__RESERVED28_MASK 0x10000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L +#define SDMA7_PUB_REG_TYPE2__SDMA7_ULV_CNTL_MASK 0x40000000L +#define SDMA7_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA7_PUB_REG_TYPE3 +#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_DATA__SHIFT 0x0 +#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_INDEX__SHIFT 0x1 +#define SDMA7_PUB_REG_TYPE3__SDMA7_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA7_PUB_REG_TYPE3__RESERVED__SHIFT 0x3 +#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_DATA_MASK 0x00000001L +#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_INDEX_MASK 0x00000002L +#define SDMA7_PUB_REG_TYPE3__SDMA7_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA7_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFF8L +//SDMA7_MMHUB_CNTL +#define SDMA7_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define SDMA7_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//SDMA7_CONTEXT_GROUP_BOUNDARY +#define SDMA7_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 +#define SDMA7_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL +//SDMA7_POWER_CNTL +#define SDMA7_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 +#define SDMA7_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 +#define SDMA7_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa +#define SDMA7_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb +#define SDMA7_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc +#define SDMA7_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L +#define SDMA7_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L +#define SDMA7_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L +#define SDMA7_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L +#define SDMA7_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L +//SDMA7_CLK_CTRL +#define SDMA7_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define SDMA7_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define SDMA7_CLK_CTRL__RESERVED__SHIFT 0xc +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define SDMA7_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define SDMA7_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define SDMA7_CLK_CTRL__RESERVED_MASK 0x00FFF000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define SDMA7_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//SDMA7_CNTL +#define SDMA7_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA7_CNTL__UTC_L1_ENABLE__SHIFT 0x1 +#define SDMA7_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 +#define SDMA7_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA7_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA7_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA7_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 +#define SDMA7_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA7_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA7_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA7_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA7_CNTL__UTC_L1_ENABLE_MASK 0x00000002L +#define SDMA7_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L +#define SDMA7_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA7_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA7_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA7_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L +#define SDMA7_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA7_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA7_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +//SDMA7_CHICKEN_BITS +#define SDMA7_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 +#define SDMA7_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 +#define SDMA7_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 +#define SDMA7_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 +#define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa +#define SDMA7_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA7_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 +#define SDMA7_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 +#define SDMA7_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 +#define SDMA7_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 +#define SDMA7_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a +#define SDMA7_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c +#define SDMA7_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e +#define SDMA7_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L +#define SDMA7_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L +#define SDMA7_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L +#define SDMA7_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L +#define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L +#define SDMA7_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA7_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L +#define SDMA7_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L +#define SDMA7_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L +#define SDMA7_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L +#define SDMA7_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L +#define SDMA7_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L +#define SDMA7_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L +//SDMA7_GB_ADDR_CONFIG +#define SDMA7_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define SDMA7_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA7_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA7_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define SDMA7_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA7_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define SDMA7_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA7_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA7_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define SDMA7_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA7_GB_ADDR_CONFIG_READ +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define SDMA7_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define SDMA7_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define SDMA7_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define SDMA7_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L +#define SDMA7_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +//SDMA7_RB_RPTR_FETCH_HI +#define SDMA7_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_SEM_WAIT_FAIL_TIMER_CNTL +#define SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 +#define SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL +//SDMA7_RB_RPTR_FETCH +#define SDMA7_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA7_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA7_IB_OFFSET_FETCH +#define SDMA7_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA7_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA7_PROGRAM +#define SDMA7_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA7_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA7_STATUS_REG +#define SDMA7_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA7_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA7_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA7_STATUS_REG__RB_FULL__SHIFT 0x3 +#define SDMA7_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA7_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA7_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA7_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA7_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 +#define SDMA7_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA7_STATUS_REG__EX_IDLE__SHIFT 0xa +#define SDMA7_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb +#define SDMA7_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA7_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA7_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA7_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA7_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA7_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA7_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA7_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA7_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA7_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 +#define SDMA7_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 +#define SDMA7_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 +#define SDMA7_STATUS_REG__SEM_IDLE__SHIFT 0x1a +#define SDMA7_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b +#define SDMA7_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c +#define SDMA7_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA7_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA7_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA7_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA7_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA7_STATUS_REG__RB_FULL_MASK 0x00000008L +#define SDMA7_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA7_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA7_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA7_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA7_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L +#define SDMA7_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA7_STATUS_REG__EX_IDLE_MASK 0x00000400L +#define SDMA7_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L +#define SDMA7_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA7_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA7_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA7_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA7_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA7_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA7_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA7_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA7_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA7_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L +#define SDMA7_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L +#define SDMA7_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L +#define SDMA7_STATUS_REG__SEM_IDLE_MASK 0x04000000L +#define SDMA7_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L +#define SDMA7_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L +#define SDMA7_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA7_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA7_STATUS1_REG +#define SDMA7_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA7_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA7_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 +#define SDMA7_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA7_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA7_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA7_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA7_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA7_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA7_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd +#define SDMA7_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe +#define SDMA7_STATUS1_REG__EX_START__SHIFT 0xf +#define SDMA7_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 +#define SDMA7_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 +#define SDMA7_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA7_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA7_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L +#define SDMA7_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA7_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA7_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA7_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA7_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA7_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA7_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L +#define SDMA7_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L +#define SDMA7_STATUS1_REG__EX_START_MASK 0x00008000L +#define SDMA7_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L +#define SDMA7_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L +//SDMA7_RD_BURST_CNTL +#define SDMA7_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 +#define SDMA7_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 +#define SDMA7_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L +#define SDMA7_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL +//SDMA7_HBM_PAGE_CONFIG +#define SDMA7_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA7_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L +//SDMA7_UCODE_CHECKSUM +#define SDMA7_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define SDMA7_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//SDMA7_F32_CNTL +#define SDMA7_F32_CNTL__HALT__SHIFT 0x0 +#define SDMA7_F32_CNTL__STEP__SHIFT 0x1 +#define SDMA7_F32_CNTL__HALT_MASK 0x00000001L +#define SDMA7_F32_CNTL__STEP_MASK 0x00000002L +//SDMA7_FREEZE +#define SDMA7_FREEZE__PREEMPT__SHIFT 0x0 +#define SDMA7_FREEZE__FREEZE__SHIFT 0x4 +#define SDMA7_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA7_FREEZE__F32_FREEZE__SHIFT 0x6 +#define SDMA7_FREEZE__PREEMPT_MASK 0x00000001L +#define SDMA7_FREEZE__FREEZE_MASK 0x00000010L +#define SDMA7_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA7_FREEZE__F32_FREEZE_MASK 0x00000040L +//SDMA7_PHASE0_QUANTUM +#define SDMA7_PHASE0_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA7_PHASE0_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA7_PHASE0_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA7_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA7_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA7_PHASE0_QUANTUM__PREFER_MASK 0x40000000L +//SDMA7_PHASE1_QUANTUM +#define SDMA7_PHASE1_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA7_PHASE1_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA7_PHASE1_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA7_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA7_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA7_PHASE1_QUANTUM__PREFER_MASK 0x40000000L +//SDMA7_EDC_CONFIG +#define SDMA7_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define SDMA7_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 +#define SDMA7_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +#define SDMA7_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L +//SDMA7_BA_THRESHOLD +#define SDMA7_BA_THRESHOLD__READ_THRES__SHIFT 0x0 +#define SDMA7_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 +#define SDMA7_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL +#define SDMA7_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L +//SDMA7_ID +#define SDMA7_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA7_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA7_VERSION +#define SDMA7_VERSION__MINVER__SHIFT 0x0 +#define SDMA7_VERSION__MAJVER__SHIFT 0x8 +#define SDMA7_VERSION__REV__SHIFT 0x10 +#define SDMA7_VERSION__MINVER_MASK 0x0000007FL +#define SDMA7_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA7_VERSION__REV_MASK 0x003F0000L +//SDMA7_EDC_COUNTER +#define SDMA7_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 +#define SDMA7_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 +#define SDMA7_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 +#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 +#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 +#define SDMA7_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 +#define SDMA7_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 +#define SDMA7_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 +#define SDMA7_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L +#define SDMA7_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L +#define SDMA7_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L +#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L +#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L +#define SDMA7_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L +#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L +#define SDMA7_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L +#define SDMA7_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L +//SDMA7_EDC_COUNTER_CLEAR +#define SDMA7_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 +#define SDMA7_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L +//SDMA7_STATUS2_REG +#define SDMA7_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA7_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 +#define SDMA7_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA7_STATUS2_REG__ID_MASK 0x00000007L +#define SDMA7_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L +#define SDMA7_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA7_ATOMIC_CNTL +#define SDMA7_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA7_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA7_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA7_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA7_ATOMIC_PREOP_LO +#define SDMA7_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA7_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA7_ATOMIC_PREOP_HI +#define SDMA7_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA7_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_CNTL +#define SDMA7_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 +#define SDMA7_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 +#define SDMA7_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb +#define SDMA7_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe +#define SDMA7_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 +#define SDMA7_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d +#define SDMA7_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L +#define SDMA7_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL +#define SDMA7_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L +#define SDMA7_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L +#define SDMA7_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L +#define SDMA7_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L +//SDMA7_UTCL1_WATERMK +#define SDMA7_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 +#define SDMA7_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 +#define SDMA7_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 +#define SDMA7_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 +#define SDMA7_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL +#define SDMA7_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L +#define SDMA7_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L +#define SDMA7_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L +//SDMA7_UTCL1_RD_STATUS +#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA7_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA7_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA7_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA7_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 +#define SDMA7_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 +#define SDMA7_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a +#define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d +#define SDMA7_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e +#define SDMA7_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f +#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA7_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA7_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA7_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA7_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L +#define SDMA7_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L +#define SDMA7_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L +#define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L +#define SDMA7_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L +#define SDMA7_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L +//SDMA7_UTCL1_WR_STATUS +#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 +#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 +#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 +#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 +#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 +#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 +#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 +#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 +#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 +#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 +#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb +#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc +#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd +#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe +#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf +#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 +#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 +#define SDMA7_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 +#define SDMA7_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 +#define SDMA7_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 +#define SDMA7_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 +#define SDMA7_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 +#define SDMA7_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 +#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c +#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d +#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e +#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f +#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L +#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L +#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L +#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L +#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L +#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L +#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L +#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L +#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L +#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L +#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L +#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L +#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L +#define SDMA7_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L +#define SDMA7_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L +#define SDMA7_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L +#define SDMA7_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L +#define SDMA7_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L +#define SDMA7_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L +#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L +#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L +#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L +#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L +//SDMA7_UTCL1_INV0 +#define SDMA7_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 +#define SDMA7_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 +#define SDMA7_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 +#define SDMA7_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 +#define SDMA7_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 +#define SDMA7_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 +#define SDMA7_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 +#define SDMA7_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 +#define SDMA7_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 +#define SDMA7_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 +#define SDMA7_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa +#define SDMA7_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb +#define SDMA7_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc +#define SDMA7_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c +#define SDMA7_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L +#define SDMA7_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L +#define SDMA7_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L +#define SDMA7_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L +#define SDMA7_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L +#define SDMA7_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L +#define SDMA7_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L +#define SDMA7_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L +#define SDMA7_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L +#define SDMA7_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L +#define SDMA7_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L +#define SDMA7_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L +#define SDMA7_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L +#define SDMA7_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L +//SDMA7_UTCL1_INV1 +#define SDMA7_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA7_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_INV2 +#define SDMA7_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 +#define SDMA7_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_RD_XNACK0 +#define SDMA7_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA7_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_RD_XNACK1 +#define SDMA7_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA7_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA7_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA7_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA7_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA7_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA7_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA7_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA7_UTCL1_WR_XNACK0 +#define SDMA7_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 +#define SDMA7_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA7_UTCL1_WR_XNACK1 +#define SDMA7_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 +#define SDMA7_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 +#define SDMA7_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 +#define SDMA7_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a +#define SDMA7_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL +#define SDMA7_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L +#define SDMA7_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L +#define SDMA7_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L +//SDMA7_UTCL1_TIMEOUT +#define SDMA7_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 +#define SDMA7_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 +#define SDMA7_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL +#define SDMA7_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L +//SDMA7_UTCL1_PAGE +#define SDMA7_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 +#define SDMA7_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA7_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 +#define SDMA7_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 +#define SDMA7_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L +#define SDMA7_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL +#define SDMA7_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L +#define SDMA7_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L +//SDMA7_POWER_CNTL_IDLE +#define SDMA7_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 +#define SDMA7_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 +#define SDMA7_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 +#define SDMA7_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL +#define SDMA7_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L +#define SDMA7_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L +//SDMA7_RELAX_ORDERING_LUT +#define SDMA7_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define SDMA7_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 +#define SDMA7_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 +#define SDMA7_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define SDMA7_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define SDMA7_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define SDMA7_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define SDMA7_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define SDMA7_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define SDMA7_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define SDMA7_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb +#define SDMA7_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc +#define SDMA7_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define SDMA7_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe +#define SDMA7_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define SDMA7_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d +#define SDMA7_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define SDMA7_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define SDMA7_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define SDMA7_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L +#define SDMA7_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L +#define SDMA7_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define SDMA7_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define SDMA7_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define SDMA7_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define SDMA7_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define SDMA7_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define SDMA7_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define SDMA7_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L +#define SDMA7_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L +#define SDMA7_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define SDMA7_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L +#define SDMA7_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define SDMA7_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L +#define SDMA7_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define SDMA7_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//SDMA7_CHICKEN_BITS_2 +#define SDMA7_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA7_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +//SDMA7_STATUS3_REG +#define SDMA7_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 +#define SDMA7_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA7_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA7_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 +#define SDMA7_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 +#define SDMA7_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL +#define SDMA7_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA7_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA7_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L +#define SDMA7_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L +//SDMA7_PHYSICAL_ADDR_LO +#define SDMA7_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 +#define SDMA7_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 +#define SDMA7_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 +#define SDMA7_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc +#define SDMA7_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L +#define SDMA7_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L +#define SDMA7_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L +#define SDMA7_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L +//SDMA7_PHYSICAL_ADDR_HI +#define SDMA7_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL +//SDMA7_PHASE2_QUANTUM +#define SDMA7_PHASE2_QUANTUM__UNIT__SHIFT 0x0 +#define SDMA7_PHASE2_QUANTUM__VALUE__SHIFT 0x8 +#define SDMA7_PHASE2_QUANTUM__PREFER__SHIFT 0x1e +#define SDMA7_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL +#define SDMA7_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L +#define SDMA7_PHASE2_QUANTUM__PREFER_MASK 0x40000000L +//SDMA7_ERROR_LOG +#define SDMA7_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA7_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA7_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA7_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA7_PUB_DUMMY_REG0 +#define SDMA7_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA7_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA7_PUB_DUMMY_REG1 +#define SDMA7_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA7_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA7_PUB_DUMMY_REG2 +#define SDMA7_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA7_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA7_PUB_DUMMY_REG3 +#define SDMA7_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA7_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA7_F32_COUNTER +#define SDMA7_F32_COUNTER__VALUE__SHIFT 0x0 +#define SDMA7_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA7_UNBREAKABLE +#define SDMA7_UNBREAKABLE__VALUE__SHIFT 0x0 +#define SDMA7_UNBREAKABLE__VALUE_MASK 0x00000001L +//SDMA7_PERFMON_CNTL +#define SDMA7_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 +#define SDMA7_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 +#define SDMA7_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define SDMA7_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa +#define SDMA7_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb +#define SDMA7_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc +#define SDMA7_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L +#define SDMA7_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L +#define SDMA7_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL +#define SDMA7_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L +#define SDMA7_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L +#define SDMA7_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L +//SDMA7_PERFCOUNTER0_RESULT +#define SDMA7_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA7_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA7_PERFCOUNTER1_RESULT +#define SDMA7_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define SDMA7_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//SDMA7_PERFCOUNTER_TAG_DELAY_RANGE +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L +#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L +//SDMA7_CRD_CNTL +#define SDMA7_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define SDMA7_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define SDMA7_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define SDMA7_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//SDMA7_GPU_IOV_VIOLATION_LOG +#define SDMA7_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA7_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA7_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA7_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA7_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA7_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA7_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA7_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA7_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA7_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA7_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA7_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L +//SDMA7_ULV_CNTL +#define SDMA7_ULV_CNTL__HYSTERESIS__SHIFT 0x0 +#define SDMA7_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b +#define SDMA7_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c +#define SDMA7_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d +#define SDMA7_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e +#define SDMA7_ULV_CNTL__ULV_STATUS__SHIFT 0x1f +#define SDMA7_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL +#define SDMA7_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L +#define SDMA7_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L +#define SDMA7_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L +#define SDMA7_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L +#define SDMA7_ULV_CNTL__ULV_STATUS_MASK 0x80000000L +//SDMA7_EA_DBIT_ADDR_DATA +#define SDMA7_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 +#define SDMA7_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL +//SDMA7_EA_DBIT_ADDR_INDEX +#define SDMA7_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 +#define SDMA7_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L +//SDMA7_GPU_IOV_VIOLATION_LOG2 +#define SDMA7_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA7_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000000FFL +//SDMA7_GFX_RB_CNTL +#define SDMA7_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_GFX_RB_BASE +#define SDMA7_GFX_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_BASE_HI +#define SDMA7_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_GFX_RB_RPTR +#define SDMA7_GFX_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_RPTR_HI +#define SDMA7_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR +#define SDMA7_GFX_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR_HI +#define SDMA7_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR_POLL_CNTL +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_GFX_RB_RPTR_ADDR_HI +#define SDMA7_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_RPTR_ADDR_LO +#define SDMA7_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_GFX_IB_CNTL +#define SDMA7_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_GFX_IB_RPTR +#define SDMA7_GFX_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_GFX_IB_OFFSET +#define SDMA7_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_GFX_IB_BASE_LO +#define SDMA7_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_GFX_IB_BASE_HI +#define SDMA7_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_IB_SIZE +#define SDMA7_GFX_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_GFX_SKIP_CNTL +#define SDMA7_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_GFX_CONTEXT_STATUS +#define SDMA7_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_GFX_DOORBELL +#define SDMA7_GFX_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_GFX_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_GFX_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_GFX_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_GFX_CONTEXT_CNTL +#define SDMA7_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 +#define SDMA7_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L +//SDMA7_GFX_STATUS +#define SDMA7_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_GFX_DOORBELL_LOG +#define SDMA7_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_GFX_WATERMARK +#define SDMA7_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_GFX_DOORBELL_OFFSET +#define SDMA7_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_GFX_CSA_ADDR_LO +#define SDMA7_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_GFX_CSA_ADDR_HI +#define SDMA7_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_IB_SUB_REMAIN +#define SDMA7_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_GFX_PREEMPT +#define SDMA7_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_GFX_DUMMY_REG +#define SDMA7_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR_POLL_ADDR_HI +#define SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_GFX_RB_WPTR_POLL_ADDR_LO +#define SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_GFX_RB_AQL_CNTL +#define SDMA7_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_GFX_MINOR_PTR_UPDATE +#define SDMA7_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_GFX_MIDCMD_DATA0 +#define SDMA7_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA1 +#define SDMA7_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA2 +#define SDMA7_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA3 +#define SDMA7_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA4 +#define SDMA7_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA5 +#define SDMA7_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA6 +#define SDMA7_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA7 +#define SDMA7_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_DATA8 +#define SDMA7_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_GFX_MIDCMD_CNTL +#define SDMA7_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_PAGE_RB_CNTL +#define SDMA7_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_PAGE_RB_BASE +#define SDMA7_PAGE_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_BASE_HI +#define SDMA7_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_PAGE_RB_RPTR +#define SDMA7_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_RPTR_HI +#define SDMA7_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR +#define SDMA7_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR_HI +#define SDMA7_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR_POLL_CNTL +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_PAGE_RB_RPTR_ADDR_HI +#define SDMA7_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_RPTR_ADDR_LO +#define SDMA7_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_PAGE_IB_CNTL +#define SDMA7_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_PAGE_IB_RPTR +#define SDMA7_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_PAGE_IB_OFFSET +#define SDMA7_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_PAGE_IB_BASE_LO +#define SDMA7_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_PAGE_IB_BASE_HI +#define SDMA7_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_IB_SIZE +#define SDMA7_PAGE_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_PAGE_SKIP_CNTL +#define SDMA7_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_PAGE_CONTEXT_STATUS +#define SDMA7_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_PAGE_DOORBELL +#define SDMA7_PAGE_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_PAGE_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_PAGE_STATUS +#define SDMA7_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_PAGE_DOORBELL_LOG +#define SDMA7_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_PAGE_WATERMARK +#define SDMA7_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_PAGE_DOORBELL_OFFSET +#define SDMA7_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_PAGE_CSA_ADDR_LO +#define SDMA7_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_PAGE_CSA_ADDR_HI +#define SDMA7_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_IB_SUB_REMAIN +#define SDMA7_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_PAGE_PREEMPT +#define SDMA7_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_PAGE_DUMMY_REG +#define SDMA7_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI +#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO +#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_PAGE_RB_AQL_CNTL +#define SDMA7_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_PAGE_MINOR_PTR_UPDATE +#define SDMA7_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_PAGE_MIDCMD_DATA0 +#define SDMA7_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA1 +#define SDMA7_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA2 +#define SDMA7_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA3 +#define SDMA7_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA4 +#define SDMA7_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA5 +#define SDMA7_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA6 +#define SDMA7_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA7 +#define SDMA7_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_DATA8 +#define SDMA7_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_PAGE_MIDCMD_CNTL +#define SDMA7_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC0_RB_CNTL +#define SDMA7_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC0_RB_BASE +#define SDMA7_RLC0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_BASE_HI +#define SDMA7_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC0_RB_RPTR +#define SDMA7_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_RPTR_HI +#define SDMA7_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR +#define SDMA7_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR_HI +#define SDMA7_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR_POLL_CNTL +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC0_RB_RPTR_ADDR_HI +#define SDMA7_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_RPTR_ADDR_LO +#define SDMA7_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC0_IB_CNTL +#define SDMA7_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC0_IB_RPTR +#define SDMA7_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC0_IB_OFFSET +#define SDMA7_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC0_IB_BASE_LO +#define SDMA7_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC0_IB_BASE_HI +#define SDMA7_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_IB_SIZE +#define SDMA7_RLC0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC0_SKIP_CNTL +#define SDMA7_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC0_CONTEXT_STATUS +#define SDMA7_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC0_DOORBELL +#define SDMA7_RLC0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC0_STATUS +#define SDMA7_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC0_DOORBELL_LOG +#define SDMA7_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC0_WATERMARK +#define SDMA7_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC0_DOORBELL_OFFSET +#define SDMA7_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC0_CSA_ADDR_LO +#define SDMA7_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC0_CSA_ADDR_HI +#define SDMA7_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_IB_SUB_REMAIN +#define SDMA7_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC0_PREEMPT +#define SDMA7_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC0_DUMMY_REG +#define SDMA7_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC0_RB_AQL_CNTL +#define SDMA7_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC0_MINOR_PTR_UPDATE +#define SDMA7_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC0_MIDCMD_DATA0 +#define SDMA7_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA1 +#define SDMA7_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA2 +#define SDMA7_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA3 +#define SDMA7_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA4 +#define SDMA7_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA5 +#define SDMA7_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA6 +#define SDMA7_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA7 +#define SDMA7_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_DATA8 +#define SDMA7_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC0_MIDCMD_CNTL +#define SDMA7_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC1_RB_CNTL +#define SDMA7_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC1_RB_BASE +#define SDMA7_RLC1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_BASE_HI +#define SDMA7_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC1_RB_RPTR +#define SDMA7_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_RPTR_HI +#define SDMA7_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR +#define SDMA7_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR_HI +#define SDMA7_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR_POLL_CNTL +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC1_RB_RPTR_ADDR_HI +#define SDMA7_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_RPTR_ADDR_LO +#define SDMA7_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC1_IB_CNTL +#define SDMA7_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC1_IB_RPTR +#define SDMA7_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC1_IB_OFFSET +#define SDMA7_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC1_IB_BASE_LO +#define SDMA7_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC1_IB_BASE_HI +#define SDMA7_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_IB_SIZE +#define SDMA7_RLC1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC1_SKIP_CNTL +#define SDMA7_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC1_CONTEXT_STATUS +#define SDMA7_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC1_DOORBELL +#define SDMA7_RLC1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC1_STATUS +#define SDMA7_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC1_DOORBELL_LOG +#define SDMA7_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC1_WATERMARK +#define SDMA7_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC1_DOORBELL_OFFSET +#define SDMA7_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC1_CSA_ADDR_LO +#define SDMA7_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC1_CSA_ADDR_HI +#define SDMA7_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_IB_SUB_REMAIN +#define SDMA7_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC1_PREEMPT +#define SDMA7_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC1_DUMMY_REG +#define SDMA7_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC1_RB_AQL_CNTL +#define SDMA7_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC1_MINOR_PTR_UPDATE +#define SDMA7_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC1_MIDCMD_DATA0 +#define SDMA7_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA1 +#define SDMA7_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA2 +#define SDMA7_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA3 +#define SDMA7_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA4 +#define SDMA7_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA5 +#define SDMA7_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA6 +#define SDMA7_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA7 +#define SDMA7_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_DATA8 +#define SDMA7_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC1_MIDCMD_CNTL +#define SDMA7_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC2_RB_CNTL +#define SDMA7_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC2_RB_BASE +#define SDMA7_RLC2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_BASE_HI +#define SDMA7_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC2_RB_RPTR +#define SDMA7_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_RPTR_HI +#define SDMA7_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR +#define SDMA7_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR_HI +#define SDMA7_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR_POLL_CNTL +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC2_RB_RPTR_ADDR_HI +#define SDMA7_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_RPTR_ADDR_LO +#define SDMA7_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC2_IB_CNTL +#define SDMA7_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC2_IB_RPTR +#define SDMA7_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC2_IB_OFFSET +#define SDMA7_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC2_IB_BASE_LO +#define SDMA7_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC2_IB_BASE_HI +#define SDMA7_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_IB_SIZE +#define SDMA7_RLC2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC2_SKIP_CNTL +#define SDMA7_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC2_CONTEXT_STATUS +#define SDMA7_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC2_DOORBELL +#define SDMA7_RLC2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC2_STATUS +#define SDMA7_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC2_DOORBELL_LOG +#define SDMA7_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC2_WATERMARK +#define SDMA7_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC2_DOORBELL_OFFSET +#define SDMA7_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC2_CSA_ADDR_LO +#define SDMA7_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC2_CSA_ADDR_HI +#define SDMA7_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_IB_SUB_REMAIN +#define SDMA7_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC2_PREEMPT +#define SDMA7_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC2_DUMMY_REG +#define SDMA7_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC2_RB_AQL_CNTL +#define SDMA7_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC2_MINOR_PTR_UPDATE +#define SDMA7_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC2_MIDCMD_DATA0 +#define SDMA7_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA1 +#define SDMA7_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA2 +#define SDMA7_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA3 +#define SDMA7_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA4 +#define SDMA7_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA5 +#define SDMA7_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA6 +#define SDMA7_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA7 +#define SDMA7_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_DATA8 +#define SDMA7_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC2_MIDCMD_CNTL +#define SDMA7_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC3_RB_CNTL +#define SDMA7_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC3_RB_BASE +#define SDMA7_RLC3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_BASE_HI +#define SDMA7_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC3_RB_RPTR +#define SDMA7_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_RPTR_HI +#define SDMA7_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR +#define SDMA7_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR_HI +#define SDMA7_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR_POLL_CNTL +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC3_RB_RPTR_ADDR_HI +#define SDMA7_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_RPTR_ADDR_LO +#define SDMA7_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC3_IB_CNTL +#define SDMA7_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC3_IB_RPTR +#define SDMA7_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC3_IB_OFFSET +#define SDMA7_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC3_IB_BASE_LO +#define SDMA7_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC3_IB_BASE_HI +#define SDMA7_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_IB_SIZE +#define SDMA7_RLC3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC3_SKIP_CNTL +#define SDMA7_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC3_CONTEXT_STATUS +#define SDMA7_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC3_DOORBELL +#define SDMA7_RLC3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC3_STATUS +#define SDMA7_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC3_DOORBELL_LOG +#define SDMA7_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC3_WATERMARK +#define SDMA7_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC3_DOORBELL_OFFSET +#define SDMA7_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC3_CSA_ADDR_LO +#define SDMA7_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC3_CSA_ADDR_HI +#define SDMA7_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_IB_SUB_REMAIN +#define SDMA7_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC3_PREEMPT +#define SDMA7_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC3_DUMMY_REG +#define SDMA7_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC3_RB_AQL_CNTL +#define SDMA7_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC3_MINOR_PTR_UPDATE +#define SDMA7_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC3_MIDCMD_DATA0 +#define SDMA7_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA1 +#define SDMA7_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA2 +#define SDMA7_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA3 +#define SDMA7_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA4 +#define SDMA7_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA5 +#define SDMA7_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA6 +#define SDMA7_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA7 +#define SDMA7_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_DATA8 +#define SDMA7_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC3_MIDCMD_CNTL +#define SDMA7_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC4_RB_CNTL +#define SDMA7_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC4_RB_BASE +#define SDMA7_RLC4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_BASE_HI +#define SDMA7_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC4_RB_RPTR +#define SDMA7_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_RPTR_HI +#define SDMA7_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR +#define SDMA7_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR_HI +#define SDMA7_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR_POLL_CNTL +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC4_RB_RPTR_ADDR_HI +#define SDMA7_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_RPTR_ADDR_LO +#define SDMA7_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC4_IB_CNTL +#define SDMA7_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC4_IB_RPTR +#define SDMA7_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC4_IB_OFFSET +#define SDMA7_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC4_IB_BASE_LO +#define SDMA7_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC4_IB_BASE_HI +#define SDMA7_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_IB_SIZE +#define SDMA7_RLC4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC4_SKIP_CNTL +#define SDMA7_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC4_CONTEXT_STATUS +#define SDMA7_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC4_DOORBELL +#define SDMA7_RLC4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC4_STATUS +#define SDMA7_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC4_DOORBELL_LOG +#define SDMA7_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC4_WATERMARK +#define SDMA7_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC4_DOORBELL_OFFSET +#define SDMA7_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC4_CSA_ADDR_LO +#define SDMA7_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC4_CSA_ADDR_HI +#define SDMA7_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_IB_SUB_REMAIN +#define SDMA7_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC4_PREEMPT +#define SDMA7_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC4_DUMMY_REG +#define SDMA7_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC4_RB_AQL_CNTL +#define SDMA7_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC4_MINOR_PTR_UPDATE +#define SDMA7_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC4_MIDCMD_DATA0 +#define SDMA7_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA1 +#define SDMA7_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA2 +#define SDMA7_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA3 +#define SDMA7_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA4 +#define SDMA7_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA5 +#define SDMA7_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA6 +#define SDMA7_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA7 +#define SDMA7_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_DATA8 +#define SDMA7_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC4_MIDCMD_CNTL +#define SDMA7_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC5_RB_CNTL +#define SDMA7_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC5_RB_BASE +#define SDMA7_RLC5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_BASE_HI +#define SDMA7_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC5_RB_RPTR +#define SDMA7_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_RPTR_HI +#define SDMA7_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR +#define SDMA7_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR_HI +#define SDMA7_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR_POLL_CNTL +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC5_RB_RPTR_ADDR_HI +#define SDMA7_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_RPTR_ADDR_LO +#define SDMA7_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC5_IB_CNTL +#define SDMA7_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC5_IB_RPTR +#define SDMA7_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC5_IB_OFFSET +#define SDMA7_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC5_IB_BASE_LO +#define SDMA7_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC5_IB_BASE_HI +#define SDMA7_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_IB_SIZE +#define SDMA7_RLC5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC5_SKIP_CNTL +#define SDMA7_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC5_CONTEXT_STATUS +#define SDMA7_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC5_DOORBELL +#define SDMA7_RLC5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC5_STATUS +#define SDMA7_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC5_DOORBELL_LOG +#define SDMA7_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC5_WATERMARK +#define SDMA7_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC5_DOORBELL_OFFSET +#define SDMA7_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC5_CSA_ADDR_LO +#define SDMA7_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC5_CSA_ADDR_HI +#define SDMA7_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_IB_SUB_REMAIN +#define SDMA7_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC5_PREEMPT +#define SDMA7_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC5_DUMMY_REG +#define SDMA7_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC5_RB_AQL_CNTL +#define SDMA7_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC5_MINOR_PTR_UPDATE +#define SDMA7_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC5_MIDCMD_DATA0 +#define SDMA7_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA1 +#define SDMA7_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA2 +#define SDMA7_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA3 +#define SDMA7_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA4 +#define SDMA7_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA5 +#define SDMA7_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA6 +#define SDMA7_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA7 +#define SDMA7_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_DATA8 +#define SDMA7_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC5_MIDCMD_CNTL +#define SDMA7_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC6_RB_CNTL +#define SDMA7_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC6_RB_BASE +#define SDMA7_RLC6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_BASE_HI +#define SDMA7_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC6_RB_RPTR +#define SDMA7_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_RPTR_HI +#define SDMA7_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR +#define SDMA7_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR_HI +#define SDMA7_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR_POLL_CNTL +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC6_RB_RPTR_ADDR_HI +#define SDMA7_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_RPTR_ADDR_LO +#define SDMA7_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC6_IB_CNTL +#define SDMA7_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC6_IB_RPTR +#define SDMA7_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC6_IB_OFFSET +#define SDMA7_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC6_IB_BASE_LO +#define SDMA7_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC6_IB_BASE_HI +#define SDMA7_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_IB_SIZE +#define SDMA7_RLC6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC6_SKIP_CNTL +#define SDMA7_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC6_CONTEXT_STATUS +#define SDMA7_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC6_DOORBELL +#define SDMA7_RLC6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC6_STATUS +#define SDMA7_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC6_DOORBELL_LOG +#define SDMA7_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC6_WATERMARK +#define SDMA7_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC6_DOORBELL_OFFSET +#define SDMA7_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC6_CSA_ADDR_LO +#define SDMA7_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC6_CSA_ADDR_HI +#define SDMA7_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_IB_SUB_REMAIN +#define SDMA7_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC6_PREEMPT +#define SDMA7_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC6_DUMMY_REG +#define SDMA7_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC6_RB_AQL_CNTL +#define SDMA7_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC6_MINOR_PTR_UPDATE +#define SDMA7_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC6_MIDCMD_DATA0 +#define SDMA7_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA1 +#define SDMA7_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA2 +#define SDMA7_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA3 +#define SDMA7_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA4 +#define SDMA7_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA5 +#define SDMA7_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA6 +#define SDMA7_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA7 +#define SDMA7_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_DATA8 +#define SDMA7_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC6_MIDCMD_CNTL +#define SDMA7_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA7_RLC7_RB_CNTL +#define SDMA7_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA7_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA7_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA7_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA7_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA7_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA7_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA7_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA7_RLC7_RB_BASE +#define SDMA7_RLC7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_BASE_HI +#define SDMA7_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA7_RLC7_RB_RPTR +#define SDMA7_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_RPTR_HI +#define SDMA7_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR +#define SDMA7_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA7_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR_HI +#define SDMA7_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA7_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR_POLL_CNTL +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L +#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//SDMA7_RLC7_RB_RPTR_ADDR_HI +#define SDMA7_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_RPTR_ADDR_LO +#define SDMA7_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 +#define SDMA7_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L +#define SDMA7_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC7_IB_CNTL +#define SDMA7_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA7_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA7_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA7_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA7_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA7_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA7_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +//SDMA7_RLC7_IB_RPTR +#define SDMA7_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA7_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC7_IB_OFFSET +#define SDMA7_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA7_RLC7_IB_BASE_LO +#define SDMA7_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define SDMA7_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//SDMA7_RLC7_IB_BASE_HI +#define SDMA7_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_IB_SIZE +#define SDMA7_RLC7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA7_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC7_SKIP_CNTL +#define SDMA7_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define SDMA7_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//SDMA7_RLC7_CONTEXT_STATUS +#define SDMA7_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA7_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA7_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA7_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 +#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 +#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA7_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA7_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA7_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA7_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L +#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L +#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +//SDMA7_RLC7_DOORBELL +#define SDMA7_RLC7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA7_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA7_RLC7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA7_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA7_RLC7_STATUS +#define SDMA7_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 +#define SDMA7_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 +#define SDMA7_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL +#define SDMA7_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L +//SDMA7_RLC7_DOORBELL_LOG +#define SDMA7_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA7_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA7_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA7_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA7_RLC7_WATERMARK +#define SDMA7_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 +#define SDMA7_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 +#define SDMA7_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL +#define SDMA7_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L +//SDMA7_RLC7_DOORBELL_OFFSET +#define SDMA7_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA7_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA7_RLC7_CSA_ADDR_LO +#define SDMA7_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC7_CSA_ADDR_HI +#define SDMA7_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_IB_SUB_REMAIN +#define SDMA7_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA7_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL +//SDMA7_RLC7_PREEMPT +#define SDMA7_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA7_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA7_RLC7_DUMMY_REG +#define SDMA7_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA7_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI +#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO +#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA7_RLC7_RB_AQL_CNTL +#define SDMA7_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA7_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA7_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA7_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA7_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +//SDMA7_RLC7_MINOR_PTR_UPDATE +#define SDMA7_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA7_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA7_RLC7_MIDCMD_DATA0 +#define SDMA7_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA1 +#define SDMA7_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA2 +#define SDMA7_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA3 +#define SDMA7_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA4 +#define SDMA7_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA5 +#define SDMA7_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA6 +#define SDMA7_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA7 +#define SDMA7_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_DATA8 +#define SDMA7_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA7_RLC7_MIDCMD_CNTL +#define SDMA7_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA7_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA7_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA7_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA7_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA7_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA7_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA7_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h index 5df70484bc7d..d3876052562b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h @@ -29,6 +29,98 @@ #define mmSMUSVI0_TEL_PLANE0_BASE_IDX 0 #define mmSMUIO_MCM_CONFIG 0x0024 #define mmSMUIO_MCM_CONFIG_BASE_IDX 0 +#define mmCKSVII2C_IC_CON 0x0040 +#define mmCKSVII2C_IC_CON_BASE_IDX 0 +#define mmCKSVII2C_IC_TAR 0x0041 +#define mmCKSVII2C_IC_TAR_BASE_IDX 0 +#define mmCKSVII2C_IC_SAR 0x0042 +#define mmCKSVII2C_IC_SAR_BASE_IDX 0 +#define mmCKSVII2C_IC_HS_MADDR 0x0043 +#define mmCKSVII2C_IC_HS_MADDR_BASE_IDX 0 +#define mmCKSVII2C_IC_DATA_CMD 0x0044 +#define mmCKSVII2C_IC_DATA_CMD_BASE_IDX 0 +#define mmCKSVII2C_IC_SS_SCL_HCNT 0x0045 +#define mmCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0 +#define mmCKSVII2C_IC_SS_SCL_LCNT 0x0046 +#define mmCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0 +#define mmCKSVII2C_IC_FS_SCL_HCNT 0x0047 +#define mmCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0 +#define mmCKSVII2C_IC_FS_SCL_LCNT 0x0048 +#define mmCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0 +#define mmCKSVII2C_IC_HS_SCL_HCNT 0x0049 +#define mmCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0 +#define mmCKSVII2C_IC_HS_SCL_LCNT 0x004a +#define mmCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0 +#define mmCKSVII2C_IC_INTR_STAT 0x004b +#define mmCKSVII2C_IC_INTR_STAT_BASE_IDX 0 +#define mmCKSVII2C_IC_INTR_MASK 0x004c +#define mmCKSVII2C_IC_INTR_MASK_BASE_IDX 0 +#define mmCKSVII2C_IC_RAW_INTR_STAT 0x004d +#define mmCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0 +#define mmCKSVII2C_IC_RX_TL 0x004e +#define mmCKSVII2C_IC_RX_TL_BASE_IDX 0 +#define mmCKSVII2C_IC_TX_TL 0x004f +#define mmCKSVII2C_IC_TX_TL_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_INTR 0x0050 +#define mmCKSVII2C_IC_CLR_INTR_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_RX_UNDER 0x0051 +#define mmCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_RX_OVER 0x0052 +#define mmCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_TX_OVER 0x0053 +#define mmCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_RD_REQ 0x0054 +#define mmCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_TX_ABRT 0x0055 +#define mmCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_RX_DONE 0x0056 +#define mmCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_ACTIVITY 0x0057 +#define mmCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_STOP_DET 0x0058 +#define mmCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_START_DET 0x0059 +#define mmCKSVII2C_IC_CLR_START_DET_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_GEN_CALL 0x005a +#define mmCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0 +#define mmCKSVII2C_IC_ENABLE 0x005b +#define mmCKSVII2C_IC_ENABLE_BASE_IDX 0 +#define mmCKSVII2C_IC_STATUS 0x005c +#define mmCKSVII2C_IC_STATUS_BASE_IDX 0 +#define mmCKSVII2C_IC_TXFLR 0x005d +#define mmCKSVII2C_IC_TXFLR_BASE_IDX 0 +#define mmCKSVII2C_IC_RXFLR 0x005e +#define mmCKSVII2C_IC_RXFLR_BASE_IDX 0 +#define mmCKSVII2C_IC_SDA_HOLD 0x005f +#define mmCKSVII2C_IC_SDA_HOLD_BASE_IDX 0 +#define mmCKSVII2C_IC_TX_ABRT_SOURCE 0x0060 +#define mmCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0 +#define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061 +#define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 +#define mmCKSVII2C_IC_DMA_CR 0x0062 +#define mmCKSVII2C_IC_DMA_CR_BASE_IDX 0 +#define mmCKSVII2C_IC_DMA_TDLR 0x0063 +#define mmCKSVII2C_IC_DMA_TDLR_BASE_IDX 0 +#define mmCKSVII2C_IC_DMA_RDLR 0x0064 +#define mmCKSVII2C_IC_DMA_RDLR_BASE_IDX 0 +#define mmCKSVII2C_IC_SDA_SETUP 0x0065 +#define mmCKSVII2C_IC_SDA_SETUP_BASE_IDX 0 +#define mmCKSVII2C_IC_ACK_GENERAL_CALL 0x0066 +#define mmCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX 0 +#define mmCKSVII2C_IC_ENABLE_STATUS 0x0067 +#define mmCKSVII2C_IC_ENABLE_STATUS_BASE_IDX 0 +#define mmCKSVII2C_IC_FS_SPKLEN 0x0068 +#define mmCKSVII2C_IC_FS_SPKLEN_BASE_IDX 0 +#define mmCKSVII2C_IC_HS_SPKLEN 0x0069 +#define mmCKSVII2C_IC_HS_SPKLEN_BASE_IDX 0 +#define mmCKSVII2C_IC_CLR_RESTART_DET 0x006a +#define mmCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX 0 +#define mmCKSVII2C_IC_COMP_PARAM_1 0x006b +#define mmCKSVII2C_IC_COMP_PARAM_1_BASE_IDX 0 +#define mmCKSVII2C_IC_COMP_VERSION 0x006c +#define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX 0 +#define mmCKSVII2C_IC_COMP_TYPE 0x006d +#define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX 0 #define mmSMUIO_MP_RESET_INTR 0x00c1 #define mmSMUIO_MP_RESET_INTR_BASE_IDX 0 #define mmSMUIO_SOC_HALT 0x00c2 diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h index 237961558e89..f8afa3518bf2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h @@ -37,6 +37,237 @@ #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000001CL #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000020L #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x000000C0L +//CKSVII2C_IC_CON +#define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 +#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 +#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 +#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 +#define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 +#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 +#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 +#define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 +#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 +#define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L +#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L +#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L +#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L +#define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L +#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L +#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L +#define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L +#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L +//CKSVII2C_IC_TAR +#define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 +#define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa +#define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb +#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc +#define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL +#define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L +#define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L +#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L +//CKSVII2C_IC_SAR +#define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 +#define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL +//CKSVII2C_IC_HS_MADDR +#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 +#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L +//CKSVII2C_IC_DATA_CMD +#define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 +#define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 +#define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 +#define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa +#define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL +#define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L +#define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L +#define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L +//CKSVII2C_IC_SS_SCL_HCNT +#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_SS_SCL_LCNT +#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_FS_SCL_HCNT +#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_FS_SCL_LCNT +#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_HS_SCL_HCNT +#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_HS_SCL_LCNT +#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_INTR_STAT +#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 +#define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 +#define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 +#define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 +#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 +#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 +#define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 +#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 +#define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 +#define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa +#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb +#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc +#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L +#define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L +#define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L +#define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L +#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L +#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L +#define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L +#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L +#define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L +#define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L +#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L +#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L +#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C_IC_INTR_MASK +#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 +#define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 +#define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 +#define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 +#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 +#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 +#define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 +#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 +#define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 +#define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa +#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb +#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc +#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L +#define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L +#define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L +#define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L +#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L +#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L +#define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L +#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L +#define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L +#define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L +#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L +#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L +#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C_IC_RAW_INTR_STAT +#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER__SHIFT 0x0 +#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER__SHIFT 0x1 +#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL__SHIFT 0x2 +#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER__SHIFT 0x3 +#define CKSVII2C_IC__RAW_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ__SHIFT 0x5 +#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT__SHIFT 0x6 +#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE__SHIFT 0x7 +#define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY__SHIFT 0x8 +#define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET__SHIFT 0x9 +#define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET__SHIFT 0xa +#define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL__SHIFT 0xb +#define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET__SHIFT 0xc +#define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER_MASK 0x00000001L +#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER_MASK 0x00000002L +#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL_MASK 0x00000004L +#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER_MASK 0x00000008L +#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ_MASK 0x00000020L +#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT_MASK 0x00000040L +#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE_MASK 0x00000080L +#define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY_MASK 0x00000100L +#define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET_MASK 0x00000200L +#define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET_MASK 0x00000400L +#define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL_MASK 0x00000800L +#define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET_MASK 0x00001000L +#define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C_IC_RX_TL +//CKSVII2C_IC_TX_TL +//CKSVII2C_IC_CLR_INTR +//CKSVII2C_IC_CLR_RX_UNDER +//CKSVII2C_IC_CLR_RX_OVER +//CKSVII2C_IC_CLR_TX_OVER +//CKSVII2C_IC_CLR_RD_REQ +//CKSVII2C_IC_CLR_TX_ABRT +//CKSVII2C_IC_CLR_RX_DONE +//CKSVII2C_IC_CLR_ACTIVITY +#define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY__SHIFT 0x0 +#define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY_MASK 0x00000001L +//CKSVII2C_IC_CLR_STOP_DET +//CKSVII2C_IC_CLR_START_DET +//CKSVII2C_IC_CLR_GEN_CALL +//CKSVII2C_IC_ENABLE +#define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 +#define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 +#define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L +#define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L +//CKSVII2C_IC_STATUS +#define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 +#define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 +#define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 +#define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 +#define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 +#define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 +#define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 +#define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L +#define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L +#define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L +#define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L +#define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L +#define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L +#define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L +//CKSVII2C_IC_TXFLR +//CKSVII2C_IC_RXFLR +//CKSVII2C_IC_SDA_HOLD +#define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD__SHIFT 0x0 +#define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD_MASK 0x00FFFFFFL +//CKSVII2C_IC_TX_ABRT_SOURCE + +#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK__SHIFT 0x0 +#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK__SHIFT 0x1 +#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK__SHIFT 0x2 +#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK__SHIFT 0x3 +#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK_MASK 0x00000001L +#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK_MASK 0x00000002L +#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK_MASK 0x00000004L +#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK_MASK 0x00000008L +//CKSVII2C_IC_SLV_DATA_NACK_ONLY +//CKSVII2C_IC_DMA_CR +//CKSVII2C_IC_DMA_TDLR +//CKSVII2C_IC_DMA_RDLR +//CKSVII2C_IC_SDA_SETUP +#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 +#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL +//CKSVII2C_IC_ACK_GENERAL_CALL +#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT 0x0 +#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK 0x00000001L +//CKSVII2C_IC_ENABLE_STATUS +#define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 +#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED__SHIFT 0x1 +#define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED__SHIFT 0x2 +#define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L +#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED_MASK 0x00000002L +#define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED_MASK 0x00000004L +//CKSVII2C_IC_FS_SPKLEN +#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT 0x0 +#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK 0x000000FFL +//CKSVII2C_IC_HS_SPKLEN +#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT 0x0 +#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK 0x000000FFL +//CKSVII2C_IC_CLR_RESTART_DET +//CKSVII2C_IC_COMP_PARAM_1 +#define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1__SHIFT 0x0 +#define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1_MASK 0xFFFFFFFFL +//CKSVII2C_IC_COMP_VERSION +#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT 0x0 +#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK 0xFFFFFFFFL +//CKSVII2C_IC_COMP_TYPE +#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0 +#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL //SMUIO_MP_RESET_INTR #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT 0x0 #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK 0x00000001L diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h new file mode 100644 index 000000000000..043aa695d63f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _umc_6_1_1_OFFSET_HEADER +#define _umc_6_1_1_OFFSET_HEADER + +#define mmUMCCH0_0_EccErrCntSel 0x0360 +#define mmUMCCH0_0_EccErrCntSel_BASE_IDX 0 +#define mmUMCCH0_0_EccErrCnt 0x0361 +#define mmUMCCH0_0_EccErrCnt_BASE_IDX 0 +#define mmMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2 +#define mmMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h new file mode 100644 index 000000000000..45c888280af9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _umc_6_1_1_SH_MASK_HEADER +#define _umc_6_1_1_SH_MASK_HEADER + +//UMCCH0_0_EccErrCntSel +#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT 0x0 +#define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT 0xc +#define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT 0xf +#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK 0x0000000FL +#define UMCCH0_0_EccErrCntSel__EccErrInt_MASK 0x00003000L +#define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK 0x00008000L +//UMCCH0_0_EccErrCnt +#define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT 0x0 +#define UMCCH0_0_EccErrCnt__EccErrCnt_MASK 0x0000FFFFL +//MCA_UMC_UMC0_MCUMC_STATUST0 +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0 +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0__SHIFT 0x16 +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1__SHIFT 0x26 +#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2__SHIFT 0x29 +#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b +#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c +#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d +#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3__SHIFT 0x2f +#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34 +#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35 +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4__SHIFT 0x36 +#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37 +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38 +#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39 +#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a +#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b +#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c +#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d +#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e +#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0_MASK 0x00000000FFC00000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1_MASK 0x000000C000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2_MASK 0x0000060000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3_MASK 0x000F800000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4_MASK 0x0040000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L +#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L +//MCA_UMC_UMC0_MCUMC_ADDRT0 +#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0 +#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT 0x38 +#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x3e +#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL +#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK 0x3F00000000000000L +#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xC000000000000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h new file mode 100644 index 000000000000..cf2149cc12ee --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h @@ -0,0 +1,979 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _vcn_2_5_OFFSET_HEADER +#define _vcn_2_5_OFFSET_HEADER + +// addressBlock: uvd0_mmsch_dec +// base address: 0x1e000 + + +// addressBlock: uvd0_jpegnpdec +// base address: 0x1e200 +#define mmUVD_JPEG_CNTL 0x0080 +#define mmUVD_JPEG_CNTL_BASE_IDX 0 +#define mmUVD_JPEG_RB_BASE 0x0081 +#define mmUVD_JPEG_RB_BASE_BASE_IDX 0 +#define mmUVD_JPEG_RB_WPTR 0x0082 +#define mmUVD_JPEG_RB_WPTR_BASE_IDX 0 +#define mmUVD_JPEG_RB_RPTR 0x0083 +#define mmUVD_JPEG_RB_RPTR_BASE_IDX 0 +#define mmUVD_JPEG_RB_SIZE 0x0084 +#define mmUVD_JPEG_RB_SIZE_BASE_IDX 0 +#define mmUVD_JPEG_DEC_SCRATCH0 0x0089 +#define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX 0 +#define mmUVD_JPEG_INT_EN 0x008a +#define mmUVD_JPEG_INT_EN_BASE_IDX 0 +#define mmUVD_JPEG_INT_STAT 0x008b +#define mmUVD_JPEG_INT_STAT_BASE_IDX 0 +#define mmUVD_JPEG_PITCH 0x009f +#define mmUVD_JPEG_PITCH_BASE_IDX 0 +#define mmUVD_JPEG_UV_PITCH 0x00a0 +#define mmUVD_JPEG_UV_PITCH_BASE_IDX 0 +#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE 0x00a1 +#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 0 +#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE 0x00a2 +#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 0 +#define mmJPEG_DEC_GFX8_ADDR_CONFIG 0x00a3 +#define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 0 +#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0x00a4 +#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 +#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0x00a5 +#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 +#define mmJPEG_DEC_GFX10_ADDR_CONFIG 0x00a6 +#define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 0 +#define mmJPEG_DEC_ADDR_MODE 0x00a7 +#define mmJPEG_DEC_ADDR_MODE_BASE_IDX 0 +#define mmUVD_JPEG_GPCOM_CMD 0x00a9 +#define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 0 +#define mmUVD_JPEG_GPCOM_DATA0 0x00aa +#define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX 0 +#define mmUVD_JPEG_GPCOM_DATA1 0x00ab +#define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX 0 +#define mmUVD_JPEG_SCRATCH1 0x00ae +#define mmUVD_JPEG_SCRATCH1_BASE_IDX 0 +#define mmUVD_JPEG_DEC_SOFT_RST 0x00af +#define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jpeg_enc_dec +// base address: 0x1e300 +#define mmUVD_JPEG_ENC_INT_EN 0x00c1 +#define mmUVD_JPEG_ENC_INT_EN_BASE_IDX 0 +#define mmUVD_JPEG_ENC_INT_STATUS 0x00c2 +#define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX 0 +#define mmUVD_JPEG_ENC_ENGINE_CNTL 0x00c5 +#define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX 0 +#define mmUVD_JPEG_ENC_SCRATCH1 0x00ce +#define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec +// base address: 0x1e380 +#define mmUVD_JPEG_ENC_STATUS 0x00e5 +#define mmUVD_JPEG_ENC_STATUS_BASE_IDX 0 +#define mmUVD_JPEG_ENC_PITCH 0x00e6 +#define mmUVD_JPEG_ENC_PITCH_BASE_IDX 0 +#define mmUVD_JPEG_ENC_LUMA_BASE 0x00e7 +#define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX 0 +#define mmUVD_JPEG_ENC_CHROMAU_BASE 0x00e8 +#define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX 0 +#define mmUVD_JPEG_ENC_CHROMAV_BASE 0x00e9 +#define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX 0 +#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE 0x00ea +#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX 0 +#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE 0x00eb +#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX 0 +#define mmJPEG_ENC_GFX10_ADDR_CONFIG 0x00ec +#define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX 0 +#define mmJPEG_ENC_ADDR_MODE 0x00ed +#define mmJPEG_ENC_ADDR_MODE_BASE_IDX 0 +#define mmUVD_JPEG_ENC_GPCOM_CMD 0x00ee +#define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX 0 +#define mmUVD_JPEG_ENC_GPCOM_DATA0 0x00ef +#define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX 0 +#define mmUVD_JPEG_ENC_GPCOM_DATA1 0x00f0 +#define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX 0 +#define mmUVD_JPEG_ENC_CGC_CNTL 0x00f5 +#define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX 0 +#define mmUVD_JPEG_ENC_SCRATCH0 0x00f6 +#define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX 0 +#define mmUVD_JPEG_ENC_SOFT_RST 0x00f7 +#define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jrbc_dec +// base address: 0x1e400 +#define mmUVD_JRBC_RB_WPTR 0x0100 +#define mmUVD_JRBC_RB_WPTR_BASE_IDX 0 +#define mmUVD_JRBC_RB_CNTL 0x0101 +#define mmUVD_JRBC_RB_CNTL_BASE_IDX 0 +#define mmUVD_JRBC_IB_SIZE 0x0102 +#define mmUVD_JRBC_IB_SIZE_BASE_IDX 0 +#define mmUVD_JRBC_URGENT_CNTL 0x0103 +#define mmUVD_JRBC_URGENT_CNTL_BASE_IDX 0 +#define mmUVD_JRBC_RB_REF_DATA 0x0104 +#define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 0 +#define mmUVD_JRBC_RB_COND_RD_TIMER 0x0105 +#define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 0 +#define mmUVD_JRBC_SOFT_RESET 0x0108 +#define mmUVD_JRBC_SOFT_RESET_BASE_IDX 0 +#define mmUVD_JRBC_STATUS 0x0109 +#define mmUVD_JRBC_STATUS_BASE_IDX 0 +#define mmUVD_JRBC_RB_RPTR 0x010a +#define mmUVD_JRBC_RB_RPTR_BASE_IDX 0 +#define mmUVD_JRBC_RB_BUF_STATUS 0x010b +#define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX 0 +#define mmUVD_JRBC_IB_BUF_STATUS 0x010c +#define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX 0 +#define mmUVD_JRBC_IB_SIZE_UPDATE 0x010d +#define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 0 +#define mmUVD_JRBC_IB_COND_RD_TIMER 0x010e +#define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 0 +#define mmUVD_JRBC_IB_REF_DATA 0x010f +#define mmUVD_JRBC_IB_REF_DATA_BASE_IDX 0 +#define mmUVD_JPEG_PREEMPT_CMD 0x0110 +#define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX 0 +#define mmUVD_JPEG_PREEMPT_FENCE_DATA0 0x0111 +#define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 0 +#define mmUVD_JPEG_PREEMPT_FENCE_DATA1 0x0112 +#define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 0 +#define mmUVD_JRBC_RB_SIZE 0x0113 +#define mmUVD_JRBC_RB_SIZE_BASE_IDX 0 +#define mmUVD_JRBC_SCRATCH0 0x0114 +#define mmUVD_JRBC_SCRATCH0_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jrbc_enc_dec +// base address: 0x1e480 +#define mmUVD_JRBC_ENC_RB_WPTR 0x0120 +#define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX 0 +#define mmUVD_JRBC_ENC_RB_CNTL 0x0121 +#define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX 0 +#define mmUVD_JRBC_ENC_IB_SIZE 0x0122 +#define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX 0 +#define mmUVD_JRBC_ENC_URGENT_CNTL 0x0123 +#define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX 0 +#define mmUVD_JRBC_ENC_RB_REF_DATA 0x0124 +#define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX 0 +#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER 0x0125 +#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX 0 +#define mmUVD_JRBC_ENC_SOFT_RESET 0x0128 +#define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX 0 +#define mmUVD_JRBC_ENC_STATUS 0x0129 +#define mmUVD_JRBC_ENC_STATUS_BASE_IDX 0 +#define mmUVD_JRBC_ENC_RB_RPTR 0x012a +#define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX 0 +#define mmUVD_JRBC_ENC_RB_BUF_STATUS 0x012b +#define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX 0 +#define mmUVD_JRBC_ENC_IB_BUF_STATUS 0x012c +#define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX 0 +#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE 0x012d +#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX 0 +#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER 0x012e +#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX 0 +#define mmUVD_JRBC_ENC_IB_REF_DATA 0x012f +#define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX 0 +#define mmUVD_JPEG_ENC_PREEMPT_CMD 0x0130 +#define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX 0 +#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0x0131 +#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX 0 +#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0x0132 +#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX 0 +#define mmUVD_JRBC_ENC_RB_SIZE 0x0133 +#define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX 0 +#define mmUVD_JRBC_ENC_SCRATCH0 0x0134 +#define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jmi_dec +// base address: 0x1e500 +#define mmUVD_JMI_CTRL 0x0145 +#define mmUVD_JMI_CTRL_BASE_IDX 0 +#define mmUVD_LMI_JRBC_CTRL 0x0146 +#define mmUVD_LMI_JRBC_CTRL_BASE_IDX 0 +#define mmUVD_LMI_JPEG_CTRL 0x0147 +#define mmUVD_LMI_JPEG_CTRL_BASE_IDX 0 +#define mmUVD_JMI_EJRBC_CTRL 0x0148 +#define mmUVD_JMI_EJRBC_CTRL_BASE_IDX 0 +#define mmUVD_LMI_EJPEG_CTRL 0x0149 +#define mmUVD_LMI_EJPEG_CTRL_BASE_IDX 0 +#define mmUVD_LMI_JRBC_IB_VMID 0x014f +#define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 0 +#define mmUVD_LMI_JRBC_RB_VMID 0x0150 +#define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 0 +#define mmUVD_LMI_JPEG_VMID 0x0151 +#define mmUVD_LMI_JPEG_VMID_BASE_IDX 0 +#define mmUVD_JMI_ENC_JRBC_IB_VMID 0x0152 +#define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX 0 +#define mmUVD_JMI_ENC_JRBC_RB_VMID 0x0153 +#define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX 0 +#define mmUVD_JMI_ENC_JPEG_VMID 0x0154 +#define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX 0 +#define mmUVD_JMI_PERFMON_CTRL 0x015c +#define mmUVD_JMI_PERFMON_CTRL_BASE_IDX 0 +#define mmUVD_JMI_PERFMON_COUNT_LO 0x015d +#define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 0 +#define mmUVD_JMI_PERFMON_COUNT_HI 0x015e +#define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 0 +#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0160 +#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0161 +#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0162 +#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0163 +#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0164 +#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0165 +#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0166 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x0167 +#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0168 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0169 +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x016a +#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x016b +#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x016c +#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x016d +#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x016e +#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x016f +#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0170 +#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0171 +#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x017a +#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x017b +#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0x017c +#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0x017d +#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0x017e +#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0x017f +#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0x0180 +#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x0181 +#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0182 +#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0183 +#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0184 +#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0185 +#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0x0186 +#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0x0187 +#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JPEG_PREEMPT_VMID 0x0188 +#define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 0 +#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID 0x0189 +#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX 0 +#define mmUVD_LMI_JPEG2_VMID 0x018a +#define mmUVD_LMI_JPEG2_VMID_BASE_IDX 0 +#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0x018b +#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0x018c +#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0x018d +#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0x018e +#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_LMI_JPEG_CTRL2 0x018f +#define mmUVD_LMI_JPEG_CTRL2_BASE_IDX 0 +#define mmUVD_JMI_DEC_SWAP_CNTL 0x0190 +#define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 0 +#define mmUVD_JMI_ENC_SWAP_CNTL 0x0191 +#define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX 0 +#define mmUVD_JMI_CNTL 0x0192 +#define mmUVD_JMI_CNTL_BASE_IDX 0 +#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0x019a +#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX 0 +#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0x019b +#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX 0 +#define mmUVD_JMI_DEC_SWAP_CNTL2 0x019c +#define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jpeg_common_dec +// base address: 0x1e700 +#define mmJPEG_SOFT_RESET_STATUS 0x01c0 +#define mmJPEG_SOFT_RESET_STATUS_BASE_IDX 0 +#define mmJPEG_SYS_INT_EN 0x01c1 +#define mmJPEG_SYS_INT_EN_BASE_IDX 0 +#define mmJPEG_SYS_INT_STATUS 0x01c2 +#define mmJPEG_SYS_INT_STATUS_BASE_IDX 0 +#define mmJPEG_SYS_INT_ACK 0x01c3 +#define mmJPEG_SYS_INT_ACK_BASE_IDX 0 +#define mmJPEG_MASTINT_EN 0x01c8 +#define mmJPEG_MASTINT_EN_BASE_IDX 0 +#define mmJPEG_IH_CTRL 0x01c9 +#define mmJPEG_IH_CTRL_BASE_IDX 0 +#define mmJRBBM_ARB_CTRL 0x01cb +#define mmJRBBM_ARB_CTRL_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_jpeg_common_sclk_dec +// base address: 0x1e780 +#define mmJPEG_CGC_GATE 0x01e0 +#define mmJPEG_CGC_GATE_BASE_IDX 0 +#define mmJPEG_CGC_CTRL 0x01e1 +#define mmJPEG_CGC_CTRL_BASE_IDX 0 +#define mmJPEG_CGC_STATUS 0x01e2 +#define mmJPEG_CGC_STATUS_BASE_IDX 0 +#define mmJPEG_COMN_CGC_MEM_CTRL 0x01e3 +#define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 0 +#define mmJPEG_DEC_CGC_MEM_CTRL 0x01e4 +#define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 0 +#define mmJPEG2_DEC_CGC_MEM_CTRL 0x01e5 +#define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX 0 +#define mmJPEG_ENC_CGC_MEM_CTRL 0x01e6 +#define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 0 +#define mmJPEG_SOFT_RESET2 0x01e7 +#define mmJPEG_SOFT_RESET2_BASE_IDX 0 +#define mmJPEG_PERF_BANK_CONF 0x01e8 +#define mmJPEG_PERF_BANK_CONF_BASE_IDX 0 +#define mmJPEG_PERF_BANK_EVENT_SEL 0x01e9 +#define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 0 +#define mmJPEG_PERF_BANK_COUNT0 0x01ea +#define mmJPEG_PERF_BANK_COUNT0_BASE_IDX 0 +#define mmJPEG_PERF_BANK_COUNT1 0x01eb +#define mmJPEG_PERF_BANK_COUNT1_BASE_IDX 0 +#define mmJPEG_PERF_BANK_COUNT2 0x01ec +#define mmJPEG_PERF_BANK_COUNT2_BASE_IDX 0 +#define mmJPEG_PERF_BANK_COUNT3 0x01ed +#define mmJPEG_PERF_BANK_COUNT3_BASE_IDX 0 + + +// addressBlock: uvd0_uvd_pg_dec +// base address: 0x1f800 +#define mmUVD_PGFSM_CONFIG 0x0000 +#define mmUVD_PGFSM_CONFIG_BASE_IDX 1 +#define mmUVD_PGFSM_STATUS 0x0001 +#define mmUVD_PGFSM_STATUS_BASE_IDX 1 +#define mmUVD_POWER_STATUS 0x0004 +#define mmUVD_POWER_STATUS_BASE_IDX 1 +#define mmUVD_PG_IND_INDEX 0x0005 +#define mmUVD_PG_IND_INDEX_BASE_IDX 1 +#define mmUVD_PG_IND_DATA 0x0006 +#define mmUVD_PG_IND_DATA_BASE_IDX 1 +#define mmCC_UVD_HARVESTING 0x0007 +#define mmCC_UVD_HARVESTING_BASE_IDX 1 +#define mmUVD_JPEG_POWER_STATUS 0x000a +#define mmUVD_JPEG_POWER_STATUS_BASE_IDX 1 +#define mmUVD_DPG_LMA_CTL 0x0011 +#define mmUVD_DPG_LMA_CTL_BASE_IDX 1 +#define mmUVD_DPG_LMA_DATA 0x0012 +#define mmUVD_DPG_LMA_DATA_BASE_IDX 1 +#define mmUVD_DPG_LMA_MASK 0x0013 +#define mmUVD_DPG_LMA_MASK_BASE_IDX 1 +#define mmUVD_DPG_PAUSE 0x0014 +#define mmUVD_DPG_PAUSE_BASE_IDX 1 +#define mmUVD_SCRATCH1 0x0015 +#define mmUVD_SCRATCH1_BASE_IDX 1 +#define mmUVD_SCRATCH2 0x0016 +#define mmUVD_SCRATCH2_BASE_IDX 1 +#define mmUVD_SCRATCH3 0x0017 +#define mmUVD_SCRATCH3_BASE_IDX 1 +#define mmUVD_SCRATCH4 0x0018 +#define mmUVD_SCRATCH4_BASE_IDX 1 +#define mmUVD_SCRATCH5 0x0019 +#define mmUVD_SCRATCH5_BASE_IDX 1 +#define mmUVD_SCRATCH6 0x001a +#define mmUVD_SCRATCH6_BASE_IDX 1 +#define mmUVD_SCRATCH7 0x001b +#define mmUVD_SCRATCH7_BASE_IDX 1 +#define mmUVD_SCRATCH8 0x001c +#define mmUVD_SCRATCH8_BASE_IDX 1 +#define mmUVD_SCRATCH9 0x001d +#define mmUVD_SCRATCH9_BASE_IDX 1 +#define mmUVD_SCRATCH10 0x001e +#define mmUVD_SCRATCH10_BASE_IDX 1 +#define mmUVD_SCRATCH11 0x001f +#define mmUVD_SCRATCH11_BASE_IDX 1 +#define mmUVD_SCRATCH12 0x0020 +#define mmUVD_SCRATCH12_BASE_IDX 1 +#define mmUVD_SCRATCH13 0x0021 +#define mmUVD_SCRATCH13_BASE_IDX 1 +#define mmUVD_SCRATCH14 0x0022 +#define mmUVD_SCRATCH14_BASE_IDX 1 +#define mmUVD_FREE_COUNTER_REG 0x0024 +#define mmUVD_FREE_COUNTER_REG_BASE_IDX 1 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0025 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0026 +#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_DPG_VCPU_CACHE_OFFSET0 0x0027 +#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 +#define mmUVD_DPG_LMI_VCPU_CACHE_VMID 0x0028 +#define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 +#define mmUVD_PF_STATUS 0x0039 +#define mmUVD_PF_STATUS_BASE_IDX 1 +#define mmUVD_DPG_CLK_EN_VCPU_REPORT 0x003c +#define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 +#define mmUVD_GFX8_ADDR_CONFIG 0x0049 +#define mmUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_GFX10_ADDR_CONFIG 0x004a +#define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_GPCNT2_CNTL 0x004b +#define mmUVD_GPCNT2_CNTL_BASE_IDX 1 +#define mmUVD_GPCNT2_TARGET_LOWER 0x004c +#define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 +#define mmUVD_GPCNT2_STATUS_LOWER 0x004d +#define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 +#define mmUVD_GPCNT2_TARGET_UPPER 0x004e +#define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 +#define mmUVD_GPCNT2_STATUS_UPPER 0x004f +#define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 +#define mmUVD_GPCNT3_CNTL 0x0050 +#define mmUVD_GPCNT3_CNTL_BASE_IDX 1 +#define mmUVD_GPCNT3_TARGET_LOWER 0x0051 +#define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 +#define mmUVD_GPCNT3_STATUS_LOWER 0x0052 +#define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 +#define mmUVD_GPCNT3_TARGET_UPPER 0x0053 +#define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 +#define mmUVD_GPCNT3_STATUS_UPPER 0x0054 +#define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 + + +// addressBlock: uvd0_uvddec +// base address: 0x1fa00 +#define mmUVD_STATUS 0x0080 +#define mmUVD_STATUS_BASE_IDX 1 +#define mmUVD_ENC_PIPE_BUSY 0x0081 +#define mmUVD_ENC_PIPE_BUSY_BASE_IDX 1 +#define mmUVD_SOFT_RESET 0x0084 +#define mmUVD_SOFT_RESET_BASE_IDX 1 +#define mmUVD_SOFT_RESET2 0x0085 +#define mmUVD_SOFT_RESET2_BASE_IDX 1 +#define mmUVD_MMSCH_SOFT_RESET 0x0086 +#define mmUVD_MMSCH_SOFT_RESET_BASE_IDX 1 +#define mmUVD_CGC_GATE 0x0088 +#define mmUVD_CGC_GATE_BASE_IDX 1 +#define mmUVD_CGC_STATUS 0x0089 +#define mmUVD_CGC_STATUS_BASE_IDX 1 +#define mmUVD_CGC_CTRL 0x008a +#define mmUVD_CGC_CTRL_BASE_IDX 1 +#define mmUVD_CGC_UDEC_STATUS 0x008b +#define mmUVD_CGC_UDEC_STATUS_BASE_IDX 1 +#define mmUVD_SUVD_CGC_GATE 0x008c +#define mmUVD_SUVD_CGC_GATE_BASE_IDX 1 +#define mmUVD_SUVD_CGC_STATUS 0x008d +#define mmUVD_SUVD_CGC_STATUS_BASE_IDX 1 +#define mmUVD_SUVD_CGC_CTRL 0x008e +#define mmUVD_SUVD_CGC_CTRL_BASE_IDX 1 +#define mmUVD_GPCOM_VCPU_CMD 0x008f +#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX 1 +#define mmUVD_GPCOM_VCPU_DATA0 0x0090 +#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 +#define mmUVD_GPCOM_VCPU_DATA1 0x0091 +#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 +#define mmUVD_GPCOM_SYS_CMD 0x0092 +#define mmUVD_GPCOM_SYS_CMD_BASE_IDX 1 +#define mmUVD_GPCOM_SYS_DATA0 0x0093 +#define mmUVD_GPCOM_SYS_DATA0_BASE_IDX 1 +#define mmUVD_GPCOM_SYS_DATA1 0x0094 +#define mmUVD_GPCOM_SYS_DATA1_BASE_IDX 1 +#define mmUVD_VCPU_INT_EN 0x0095 +#define mmUVD_VCPU_INT_EN_BASE_IDX 1 +#define mmUVD_VCPU_INT_ACK 0x0097 +#define mmUVD_VCPU_INT_ACK_BASE_IDX 1 +#define mmUVD_VCPU_INT_ROUTE 0x0098 +#define mmUVD_VCPU_INT_ROUTE_BASE_IDX 1 +#define mmUVD_ENC_VCPU_INT_EN 0x009e +#define mmUVD_ENC_VCPU_INT_EN_BASE_IDX 1 +#define mmUVD_ENC_VCPU_INT_ACK 0x00a0 +#define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 +#define mmUVD_MASTINT_EN 0x00a1 +#define mmUVD_MASTINT_EN_BASE_IDX 1 +#define mmUVD_SYS_INT_EN 0x00a2 +#define mmUVD_SYS_INT_EN_BASE_IDX 1 +#define mmUVD_SYS_INT_STATUS 0x00a3 +#define mmUVD_SYS_INT_STATUS_BASE_IDX 1 +#define mmUVD_SYS_INT_ACK 0x00a4 +#define mmUVD_SYS_INT_ACK_BASE_IDX 1 +#define mmUVD_JOB_DONE 0x00a5 +#define mmUVD_JOB_DONE_BASE_IDX 1 +#define mmUVD_CBUF_ID 0x00a6 +#define mmUVD_CBUF_ID_BASE_IDX 1 +#define mmUVD_CONTEXT_ID 0x00a7 +#define mmUVD_CONTEXT_ID_BASE_IDX 1 +#define mmUVD_CONTEXT_ID2 0x00a8 +#define mmUVD_CONTEXT_ID2_BASE_IDX 1 +#define mmUVD_NO_OP 0x00a9 +#define mmUVD_NO_OP_BASE_IDX 1 +#define mmUVD_RB_BASE_LO 0x00aa +#define mmUVD_RB_BASE_LO_BASE_IDX 1 +#define mmUVD_RB_BASE_HI 0x00ab +#define mmUVD_RB_BASE_HI_BASE_IDX 1 +#define mmUVD_RB_SIZE 0x00ac +#define mmUVD_RB_SIZE_BASE_IDX 1 +#define mmUVD_RB_RPTR 0x00ad +#define mmUVD_RB_RPTR_BASE_IDX 1 +#define mmUVD_RB_WPTR 0x00ae +#define mmUVD_RB_WPTR_BASE_IDX 1 +#define mmUVD_RB_BASE_LO2 0x00af +#define mmUVD_RB_BASE_LO2_BASE_IDX 1 +#define mmUVD_RB_BASE_HI2 0x00b0 +#define mmUVD_RB_BASE_HI2_BASE_IDX 1 +#define mmUVD_RB_SIZE2 0x00b1 +#define mmUVD_RB_SIZE2_BASE_IDX 1 +#define mmUVD_RB_RPTR2 0x00b2 +#define mmUVD_RB_RPTR2_BASE_IDX 1 +#define mmUVD_RB_WPTR2 0x00b3 +#define mmUVD_RB_WPTR2_BASE_IDX 1 +#define mmUVD_RB_BASE_LO3 0x00b4 +#define mmUVD_RB_BASE_LO3_BASE_IDX 1 +#define mmUVD_RB_BASE_HI3 0x00b5 +#define mmUVD_RB_BASE_HI3_BASE_IDX 1 +#define mmUVD_RB_SIZE3 0x00b6 +#define mmUVD_RB_SIZE3_BASE_IDX 1 +#define mmUVD_RB_RPTR3 0x00b7 +#define mmUVD_RB_RPTR3_BASE_IDX 1 +#define mmUVD_RB_WPTR3 0x00b8 +#define mmUVD_RB_WPTR3_BASE_IDX 1 +#define mmUVD_RB_BASE_LO4 0x00b9 +#define mmUVD_RB_BASE_LO4_BASE_IDX 1 +#define mmUVD_RB_BASE_HI4 0x00ba +#define mmUVD_RB_BASE_HI4_BASE_IDX 1 +#define mmUVD_RB_SIZE4 0x00bb +#define mmUVD_RB_SIZE4_BASE_IDX 1 +#define mmUVD_RB_RPTR4 0x00bc +#define mmUVD_RB_RPTR4_BASE_IDX 1 +#define mmUVD_RB_WPTR4 0x00bd +#define mmUVD_RB_WPTR4_BASE_IDX 1 +#define mmUVD_OUT_RB_BASE_LO 0x00be +#define mmUVD_OUT_RB_BASE_LO_BASE_IDX 1 +#define mmUVD_OUT_RB_BASE_HI 0x00bf +#define mmUVD_OUT_RB_BASE_HI_BASE_IDX 1 +#define mmUVD_OUT_RB_SIZE 0x00c0 +#define mmUVD_OUT_RB_SIZE_BASE_IDX 1 +#define mmUVD_OUT_RB_RPTR 0x00c1 +#define mmUVD_OUT_RB_RPTR_BASE_IDX 1 +#define mmUVD_OUT_RB_WPTR 0x00c2 +#define mmUVD_OUT_RB_WPTR_BASE_IDX 1 +#define mmUVD_RB_ARB_CTRL 0x00c6 +#define mmUVD_RB_ARB_CTRL_BASE_IDX 1 +#define mmUVD_CTX_INDEX 0x00c7 +#define mmUVD_CTX_INDEX_BASE_IDX 1 +#define mmUVD_CTX_DATA 0x00c8 +#define mmUVD_CTX_DATA_BASE_IDX 1 +#define mmUVD_CXW_WR 0x00c9 +#define mmUVD_CXW_WR_BASE_IDX 1 +#define mmUVD_CXW_WR_INT_ID 0x00ca +#define mmUVD_CXW_WR_INT_ID_BASE_IDX 1 +#define mmUVD_CXW_WR_INT_CTX_ID 0x00cb +#define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 +#define mmUVD_CXW_INT_ID 0x00cc +#define mmUVD_CXW_INT_ID_BASE_IDX 1 +#define mmUVD_TOP_CTRL 0x00cf +#define mmUVD_TOP_CTRL_BASE_IDX 1 +#define mmUVD_YBASE 0x00d0 +#define mmUVD_YBASE_BASE_IDX 1 +#define mmUVD_UVBASE 0x00d1 +#define mmUVD_UVBASE_BASE_IDX 1 +#define mmUVD_PITCH 0x00d2 +#define mmUVD_PITCH_BASE_IDX 1 +#define mmUVD_WIDTH 0x00d3 +#define mmUVD_WIDTH_BASE_IDX 1 +#define mmUVD_HEIGHT 0x00d4 +#define mmUVD_HEIGHT_BASE_IDX 1 +#define mmUVD_PICCOUNT 0x00d5 +#define mmUVD_PICCOUNT_BASE_IDX 1 +#define mmUVD_SCRATCH_NP 0x00db +#define mmUVD_SCRATCH_NP_BASE_IDX 1 +#define mmUVD_VERSION 0x00dd +#define mmUVD_VERSION_BASE_IDX 1 +#define mmUVD_GP_SCRATCH0 0x00de +#define mmUVD_GP_SCRATCH0_BASE_IDX 1 +#define mmUVD_GP_SCRATCH1 0x00df +#define mmUVD_GP_SCRATCH1_BASE_IDX 1 +#define mmUVD_GP_SCRATCH2 0x00e0 +#define mmUVD_GP_SCRATCH2_BASE_IDX 1 +#define mmUVD_GP_SCRATCH3 0x00e1 +#define mmUVD_GP_SCRATCH3_BASE_IDX 1 +#define mmUVD_GP_SCRATCH4 0x00e2 +#define mmUVD_GP_SCRATCH4_BASE_IDX 1 +#define mmUVD_GP_SCRATCH5 0x00e3 +#define mmUVD_GP_SCRATCH5_BASE_IDX 1 +#define mmUVD_GP_SCRATCH6 0x00e4 +#define mmUVD_GP_SCRATCH6_BASE_IDX 1 +#define mmUVD_GP_SCRATCH7 0x00e5 +#define mmUVD_GP_SCRATCH7_BASE_IDX 1 +#define mmUVD_GP_SCRATCH8 0x00e6 +#define mmUVD_GP_SCRATCH8_BASE_IDX 1 +#define mmUVD_GP_SCRATCH9 0x00e7 +#define mmUVD_GP_SCRATCH9_BASE_IDX 1 +#define mmUVD_GP_SCRATCH10 0x00e8 +#define mmUVD_GP_SCRATCH10_BASE_IDX 1 +#define mmUVD_GP_SCRATCH11 0x00e9 +#define mmUVD_GP_SCRATCH11_BASE_IDX 1 +#define mmUVD_GP_SCRATCH12 0x00ea +#define mmUVD_GP_SCRATCH12_BASE_IDX 1 +#define mmUVD_GP_SCRATCH13 0x00eb +#define mmUVD_GP_SCRATCH13_BASE_IDX 1 +#define mmUVD_GP_SCRATCH14 0x00ec +#define mmUVD_GP_SCRATCH14_BASE_IDX 1 +#define mmUVD_GP_SCRATCH15 0x00ed +#define mmUVD_GP_SCRATCH15_BASE_IDX 1 +#define mmUVD_GP_SCRATCH16 0x00ee +#define mmUVD_GP_SCRATCH16_BASE_IDX 1 +#define mmUVD_GP_SCRATCH17 0x00ef +#define mmUVD_GP_SCRATCH17_BASE_IDX 1 +#define mmUVD_GP_SCRATCH18 0x00f0 +#define mmUVD_GP_SCRATCH18_BASE_IDX 1 +#define mmUVD_GP_SCRATCH19 0x00f1 +#define mmUVD_GP_SCRATCH19_BASE_IDX 1 +#define mmUVD_GP_SCRATCH20 0x00f2 +#define mmUVD_GP_SCRATCH20_BASE_IDX 1 +#define mmUVD_GP_SCRATCH21 0x00f3 +#define mmUVD_GP_SCRATCH21_BASE_IDX 1 +#define mmUVD_GP_SCRATCH22 0x00f4 +#define mmUVD_GP_SCRATCH22_BASE_IDX 1 +#define mmUVD_GP_SCRATCH23 0x00f5 +#define mmUVD_GP_SCRATCH23_BASE_IDX 1 + + +// addressBlock: uvd0_ecpudec +// base address: 0x1fd00 +#define mmUVD_VCPU_CACHE_OFFSET0 0x0140 +#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE0 0x0141 +#define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET1 0x0142 +#define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE1 0x0143 +#define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET2 0x0144 +#define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE2 0x0145 +#define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET3 0x0146 +#define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE3 0x0147 +#define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET4 0x0148 +#define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE4 0x0149 +#define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET5 0x014a +#define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE5 0x014b +#define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET6 0x014c +#define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE6 0x014d +#define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET7 0x014e +#define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE7 0x014f +#define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_OFFSET8 0x0150 +#define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 +#define mmUVD_VCPU_CACHE_SIZE8 0x0151 +#define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 +#define mmUVD_VCPU_NONCACHE_OFFSET0 0x0152 +#define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 +#define mmUVD_VCPU_NONCACHE_SIZE0 0x0153 +#define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 +#define mmUVD_VCPU_NONCACHE_OFFSET1 0x0154 +#define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 +#define mmUVD_VCPU_NONCACHE_SIZE1 0x0155 +#define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 +#define mmUVD_VCPU_CNTL 0x0156 +#define mmUVD_VCPU_CNTL_BASE_IDX 1 +#define mmUVD_VCPU_PRID 0x0157 +#define mmUVD_VCPU_PRID_BASE_IDX 1 +#define mmUVD_VCPU_TRCE 0x0158 +#define mmUVD_VCPU_TRCE_BASE_IDX 1 +#define mmUVD_VCPU_TRCE_RD 0x0159 +#define mmUVD_VCPU_TRCE_RD_BASE_IDX 1 + + +// addressBlock: uvd0_uvd_mpcdec +// base address: 0x20310 +#define mmUVD_MP_SWAP_CNTL 0x02c4 +#define mmUVD_MP_SWAP_CNTL_BASE_IDX 1 +#define mmUVD_MP_SWAP_CNTL2 0x02c5 +#define mmUVD_MP_SWAP_CNTL2_BASE_IDX 1 +#define mmUVD_MPC_LUMA_SRCH 0x02c6 +#define mmUVD_MPC_LUMA_SRCH_BASE_IDX 1 +#define mmUVD_MPC_LUMA_HIT 0x02c7 +#define mmUVD_MPC_LUMA_HIT_BASE_IDX 1 +#define mmUVD_MPC_LUMA_HITPEND 0x02c8 +#define mmUVD_MPC_LUMA_HITPEND_BASE_IDX 1 +#define mmUVD_MPC_CHROMA_SRCH 0x02c9 +#define mmUVD_MPC_CHROMA_SRCH_BASE_IDX 1 +#define mmUVD_MPC_CHROMA_HIT 0x02ca +#define mmUVD_MPC_CHROMA_HIT_BASE_IDX 1 +#define mmUVD_MPC_CHROMA_HITPEND 0x02cb +#define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX 1 +#define mmUVD_MPC_CNTL 0x02cc +#define mmUVD_MPC_CNTL_BASE_IDX 1 +#define mmUVD_MPC_PITCH 0x02cd +#define mmUVD_MPC_PITCH_BASE_IDX 1 +#define mmUVD_MPC_SET_MUXA0 0x02ce +#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 +#define mmUVD_MPC_SET_MUXA1 0x02cf +#define mmUVD_MPC_SET_MUXA1_BASE_IDX 1 +#define mmUVD_MPC_SET_MUXB0 0x02d0 +#define mmUVD_MPC_SET_MUXB0_BASE_IDX 1 +#define mmUVD_MPC_SET_MUXB1 0x02d1 +#define mmUVD_MPC_SET_MUXB1_BASE_IDX 1 +#define mmUVD_MPC_SET_MUX 0x02d2 +#define mmUVD_MPC_SET_MUX_BASE_IDX 1 +#define mmUVD_MPC_SET_ALU 0x02d3 +#define mmUVD_MPC_SET_ALU_BASE_IDX 1 +#define mmUVD_MPC_PERF0 0x02d4 +#define mmUVD_MPC_PERF0_BASE_IDX 1 +#define mmUVD_MPC_PERF1 0x02d5 +#define mmUVD_MPC_PERF1_BASE_IDX 1 + + +// addressBlock: uvd0_uvd_rbcdec +// base address: 0x20370 +#define mmUVD_RBC_IB_SIZE 0x02dc +#define mmUVD_RBC_IB_SIZE_BASE_IDX 1 +#define mmUVD_RBC_IB_SIZE_UPDATE 0x02dd +#define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX 1 +#define mmUVD_RBC_RB_CNTL 0x02de +#define mmUVD_RBC_RB_CNTL_BASE_IDX 1 +#define mmUVD_RBC_RB_RPTR_ADDR 0x02df +#define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX 1 +#define mmUVD_RBC_RB_RPTR 0x02e0 +#define mmUVD_RBC_RB_RPTR_BASE_IDX 1 +#define mmUVD_RBC_RB_WPTR 0x02e1 +#define mmUVD_RBC_RB_WPTR_BASE_IDX 1 +#define mmUVD_RBC_VCPU_ACCESS 0x02e2 +#define mmUVD_RBC_VCPU_ACCESS_BASE_IDX 1 +#define mmUVD_RBC_READ_REQ_URGENT_CNTL 0x02e5 +#define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX 1 +#define mmUVD_RBC_RB_WPTR_CNTL 0x02e6 +#define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX 1 +#define mmUVD_RBC_WPTR_STATUS 0x02e7 +#define mmUVD_RBC_WPTR_STATUS_BASE_IDX 1 +#define mmUVD_RBC_WPTR_POLL_CNTL 0x02e8 +#define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX 1 +#define mmUVD_RBC_WPTR_POLL_ADDR 0x02e9 +#define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX 1 +#define mmUVD_SEMA_CMD 0x02ea +#define mmUVD_SEMA_CMD_BASE_IDX 1 +#define mmUVD_SEMA_ADDR_LOW 0x02eb +#define mmUVD_SEMA_ADDR_LOW_BASE_IDX 1 +#define mmUVD_SEMA_ADDR_HIGH 0x02ec +#define mmUVD_SEMA_ADDR_HIGH_BASE_IDX 1 +#define mmUVD_ENGINE_CNTL 0x02ed +#define mmUVD_ENGINE_CNTL_BASE_IDX 1 +#define mmUVD_SEMA_TIMEOUT_STATUS 0x02ee +#define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX 1 +#define mmUVD_SEMA_CNTL 0x02ef +#define mmUVD_SEMA_CNTL_BASE_IDX 1 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x02f0 +#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x02f1 +#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX 1 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x02f2 +#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX 1 +#define mmUVD_JOB_START 0x02f3 +#define mmUVD_JOB_START_BASE_IDX 1 +#define mmUVD_RBC_BUF_STATUS 0x02f4 +#define mmUVD_RBC_BUF_STATUS_BASE_IDX 1 + + +// addressBlock: uvd0_uvdgendec +// base address: 0x20470 +#define mmUVD_LCM_CGC_CNTRL 0x033f +#define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 +#define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x03a0 +#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x03a1 +#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x03a2 +#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_CURR_ADDR_CONFIG 0x03ae +#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_REF_ADDR_CONFIG 0x03af +#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1 +#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x03e1 +#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1 + + +// addressBlock: uvd0_lmi_adpdec +// base address: 0x20870 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x0432 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x0433 +#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x0434 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x0435 +#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x0438 +#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x0439 +#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x043a +#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x043b +#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x043c +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x043d +#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x0468 +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469 +#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x046a +#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x046b +#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x046c +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x046d +#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x046e +#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x046f +#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0470 +#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0471 +#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0472 +#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0473 +#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0474 +#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0475 +#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0476 +#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x0477 +#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_SPH_64BIT_BAR_HIGH 0x047c +#define mmUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x047d +#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x047e +#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x047f +#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0480 +#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0481 +#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0482 +#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0483 +#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0484 +#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0485 +#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0486 +#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x0487 +#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x0488 +#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x0489 +#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x048a +#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x048b +#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x048c +#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_NC_VMID 0x048d +#define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 +#define mmUVD_LMI_MMSCH_CTRL 0x048e +#define mmUVD_LMI_MMSCH_CTRL_BASE_IDX 1 +#define mmUVD_LMI_ARB_CTRL2 0x049a +#define mmUVD_LMI_ARB_CTRL2_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x049f +#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 +#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI 0x04a0 +#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 +#define mmUVD_LMI_LAT_CTRL 0x04a1 +#define mmUVD_LMI_LAT_CTRL_BASE_IDX 1 +#define mmUVD_LMI_LAT_CNTR 0x04a2 +#define mmUVD_LMI_LAT_CNTR_BASE_IDX 1 +#define mmUVD_LMI_AVG_LAT_CNTR 0x04a3 +#define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 +#define mmUVD_LMI_SPH 0x04a4 +#define mmUVD_LMI_SPH_BASE_IDX 1 +#define mmUVD_LMI_VCPU_CACHE_VMID 0x04a5 +#define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 +#define mmUVD_LMI_CTRL2 0x04a6 +#define mmUVD_LMI_CTRL2_BASE_IDX 1 +#define mmUVD_LMI_URGENT_CTRL 0x04a7 +#define mmUVD_LMI_URGENT_CTRL_BASE_IDX 1 +#define mmUVD_LMI_CTRL 0x04a8 +#define mmUVD_LMI_CTRL_BASE_IDX 1 +#define mmUVD_LMI_STATUS 0x04a9 +#define mmUVD_LMI_STATUS_BASE_IDX 1 +#define mmUVD_LMI_PERFMON_CTRL 0x04ac +#define mmUVD_LMI_PERFMON_CTRL_BASE_IDX 1 +#define mmUVD_LMI_PERFMON_COUNT_LO 0x04ad +#define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 +#define mmUVD_LMI_PERFMON_COUNT_HI 0x04ae +#define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 +#define mmUVD_LMI_RBC_RB_VMID 0x04b0 +#define mmUVD_LMI_RBC_RB_VMID_BASE_IDX 1 +#define mmUVD_LMI_RBC_IB_VMID 0x04b1 +#define mmUVD_LMI_RBC_IB_VMID_BASE_IDX 1 +#define mmUVD_LMI_MC_CREDITS 0x04b2 +#define mmUVD_LMI_MC_CREDITS_BASE_IDX 1 + + +// addressBlock: uvd0_uvdnpdec +// base address: 0x20bd0 +#define mmMDM_DMA_CMD 0x06f4 +#define mmMDM_DMA_CMD_BASE_IDX 1 +#define mmMDM_DMA_STATUS 0x06f5 +#define mmMDM_DMA_STATUS_BASE_IDX 1 +#define mmMDM_DMA_CTL 0x06f6 +#define mmMDM_DMA_CTL_BASE_IDX 1 +#define mmMDM_ENC_PIPE_BUSY 0x06f7 +#define mmMDM_ENC_PIPE_BUSY_BASE_IDX 1 +#define mmMDM_WIG_PIPE_BUSY 0x06f9 +#define mmMDM_WIG_PIPE_BUSY_BASE_IDX 1 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h new file mode 100644 index 000000000000..c41c59c30006 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h @@ -0,0 +1,3609 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _vcn_2_5_SH_MASK_HEADER +#define _vcn_2_5_SH_MASK_HEADER + +// addressBlock: uvd0_mmsch_dec +//MMSCH_UCODE_ADDR +#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 +#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f +#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL +#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L +//MMSCH_UCODE_DATA +#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//MMSCH_SRAM_ADDR +#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 +#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f +#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL +#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L +//MMSCH_SRAM_DATA +#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 +#define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_SRAM_OFFSET +#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 +#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 +#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL +#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L +//MMSCH_DB_SRAM_OFFSET +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L +#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L +//MMSCH_CTX_SRAM_OFFSET +#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 +#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 +#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL +#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L +//MMSCH_CTL +#define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0 +#define MMSCH_CTL__P_RESET__SHIFT 0x1 +#define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4 +#define MMSCH_CTL__P_LOCK__SHIFT 0x1f +#define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L +#define MMSCH_CTL__P_RESET_MASK 0x00000002L +#define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L +#define MMSCH_CTL__P_LOCK_MASK 0x80000000L +//MMSCH_INTR +#define MMSCH_INTR__INTR__SHIFT 0x0 +#define MMSCH_INTR__INTR_MASK 0x00001FFFL +//MMSCH_INTR_ACK +#define MMSCH_INTR_ACK__INTR__SHIFT 0x0 +#define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL +//MMSCH_INTR_STATUS +#define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 +#define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL +//MMSCH_VF_VMID +#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 +#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 +#define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL +#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L +//MMSCH_VF_CTX_ADDR_LO +#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 +#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L +//MMSCH_VF_CTX_ADDR_HI +#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 +#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL +//MMSCH_VF_CTX_SIZE +#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 +#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL +//MMSCH_VF_GPCOM_ADDR_LO +#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 +#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L +//MMSCH_VF_GPCOM_ADDR_HI +#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 +#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL +//MMSCH_VF_GPCOM_SIZE +#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 +#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_HOST +#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_RESP +#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_0 +#define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_0_RESP +#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_1 +#define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX_1_RESP +#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 +#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL +//MMSCH_CNTL +#define MMSCH_CNTL__CLK_EN__SHIFT 0x0 +#define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 +#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 +#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 +#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa +#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 +#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c +#define MMSCH_CNTL__CLK_EN_MASK 0x00000001L +#define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L +#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L +#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L +#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L +#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L +#define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L +//MMSCH_NONCACHE_OFFSET0 +#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 +#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL +//MMSCH_NONCACHE_SIZE0 +#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 +#define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL +//MMSCH_NONCACHE_OFFSET1 +#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 +#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL +//MMSCH_NONCACHE_SIZE1 +#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 +#define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL +//MMSCH_PROC_STATE1 +#define MMSCH_PROC_STATE1__PC__SHIFT 0x0 +#define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL +//MMSCH_LAST_MC_ADDR +#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 +#define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f +#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL +#define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L +//MMSCH_LAST_MEM_ACCESS_HI +#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 +#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 +#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc +#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L +#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L +#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L +//MMSCH_LAST_MEM_ACCESS_LO +#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 +#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL +//MMSCH_IOV_ACTIVE_FCN_ID +#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 +#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f +#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL +#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L +//MMSCH_SCRATCH_0 +#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 +#define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_1 +#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 +#define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_SCH_BLOCK_0 +#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_CONTROL_0 +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 +#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 +#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L +#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L +#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L +#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L +//MMSCH_GPUIOV_CMD_STATUS_0 +#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_VM_BUSY_STATUS_0 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCNS_0 +#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_DW6_0 +#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW7_0 +#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW8_0 +#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_SCH_BLOCK_1 +#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_CONTROL_1 +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 +#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 +#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L +#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L +#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L +#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L +//MMSCH_GPUIOV_CMD_STATUS_1 +#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_VM_BUSY_STATUS_1 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCNS_1 +#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_1 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_DW6_1 +#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW7_1 +#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW8_1 +#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_CNTXT +#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 +#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 +#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa +#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL +#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L +#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L +//MMSCH_SCRATCH_2 +#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 +#define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_3 +#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 +#define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_4 +#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 +#define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_5 +#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 +#define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_6 +#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 +#define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL +//MMSCH_SCRATCH_7 +#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 +#define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL +//MMSCH_VFID_FIFO_HEAD_0 +#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 +#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL +//MMSCH_VFID_FIFO_TAIL_0 +#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 +#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL +//MMSCH_VFID_FIFO_HEAD_1 +#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 +#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL +//MMSCH_VFID_FIFO_TAIL_1 +#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 +#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL +//MMSCH_NACK_STATUS +#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 +#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 +#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L +#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL +//MMSCH_VF_MAILBOX0_DATA +#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL +//MMSCH_VF_MAILBOX1_DATA +#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 +#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_SCH_BLOCK_IP_0 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_STATUS_IP_0 +#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_SCH_BLOCK_IP_1 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_STATUS_IP_1 +#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_CNTXT_IP +#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 +#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 +#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL +#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L +//MMSCH_GPUIOV_SCH_BLOCK_2 +#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_CONTROL_2 +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 +#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 +#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L +#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L +#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L +#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L +//MMSCH_GPUIOV_CMD_STATUS_2 +#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_VM_BUSY_STATUS_2 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 +#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCNS_2 +#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_2 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L +//MMSCH_GPUIOV_DW6_2 +#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW7_2 +#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_DW8_2 +#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 +#define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL +//MMSCH_GPUIOV_SCH_BLOCK_IP_2 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L +#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L +//MMSCH_GPUIOV_CMD_STATUS_IP_2 +#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 +#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL +//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL +#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L +//MMSCH_VFID_FIFO_HEAD_2 +#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 +#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL +//MMSCH_VFID_FIFO_TAIL_2 +#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 +#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL +//MMSCH_VM_BUSY_STATUS_0 +#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 +#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL +//MMSCH_VM_BUSY_STATUS_1 +#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 +#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL +//MMSCH_VM_BUSY_STATUS_2 +#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 +#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_jpegnpdec +//UVD_JPEG_CNTL +#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 +#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 +#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 +#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 +#define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8 +#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L +#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L +#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L +#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L +#define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L +//UVD_JPEG_RB_BASE +#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 +#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 +#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL +#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L +//UVD_JPEG_RB_WPTR +#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L +//UVD_JPEG_RB_RPTR +#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L +//UVD_JPEG_RB_SIZE +#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L +//UVD_JPEG_DEC_SCRATCH0 +#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL +//UVD_JPEG_INT_EN +#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 +#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 +#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 +#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 +#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 +#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 +#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 +#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa +#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb +#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc +#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd +#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe +#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf +#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L +#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L +#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L +#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L +#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L +#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L +#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L +#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L +#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L +#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L +#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L +#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L +#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L +//UVD_JPEG_INT_STAT +#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 +#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 +#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 +#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 +#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 +#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 +#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 +#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa +#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb +#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc +#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd +#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe +#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf +#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L +#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L +#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L +#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L +#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L +#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L +#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L +#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L +#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L +#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L +#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L +#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L +#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L +//UVD_JPEG_PITCH +#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 +#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL +//UVD_JPEG_UV_PITCH +#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 +#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL +//JPEG_DEC_Y_GFX8_TILING_SURFACE +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L +//JPEG_DEC_UV_GFX8_TILING_SURFACE +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L +//JPEG_DEC_GFX8_ADDR_CONFIG +#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +//JPEG_DEC_Y_GFX10_TILING_SURFACE +#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_DEC_UV_GFX10_TILING_SURFACE +#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_DEC_GFX10_ADDR_CONFIG +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//JPEG_DEC_ADDR_MODE +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 +#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL +#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L +//UVD_JPEG_OUTPUT_XY +//UVD_JPEG_GPCOM_CMD +#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 +#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL +//UVD_JPEG_GPCOM_DATA0 +#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 +#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_GPCOM_DATA1 +#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 +#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_JPEG_SCRATCH1 +#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 +#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL +//UVD_JPEG_DEC_SOFT_RST +#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 +#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 +#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L +#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L + + +// addressBlock: uvd0_uvd_jpeg_enc_dec +//UVD_JPEG_ENC_INT_EN +#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 +#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 +#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 +#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 +#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 +#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 +#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 +#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L +#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L +#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L +#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L +#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L +#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L +#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L +//UVD_JPEG_ENC_INT_STATUS +#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 +#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 +#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 +#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 +#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 +#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 +#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 +#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L +#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L +#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L +#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L +#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L +#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L +#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L +//UVD_JPEG_ENC_ENGINE_CNTL +#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 +#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 +#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 +#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 +#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 +#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 +#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L +#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L +#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L +#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L +#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L +#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L +//UVD_JPEG_ENC_SCRATCH1 +#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 +#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec +//UVD_JPEG_ENC_STATUS +#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 +#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 +#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 +#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 +#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L +#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L +#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L +#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L +//UVD_JPEG_ENC_PITCH +#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 +#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 +#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL +#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L +//UVD_JPEG_ENC_LUMA_BASE +#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 +#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_CHROMAU_BASE +#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 +#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_CHROMAV_BASE +#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 +#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL +//JPEG_ENC_Y_GFX10_TILING_SURFACE +#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_ENC_UV_GFX10_TILING_SURFACE +#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_ENC_GFX10_ADDR_CONFIG +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//JPEG_ENC_ADDR_MODE +#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 +#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 +#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc +#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L +#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL +#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L +//UVD_JPEG_ENC_GPCOM_CMD +#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 +#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL +//UVD_JPEG_ENC_GPCOM_DATA0 +#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 +#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_GPCOM_DATA1 +#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 +#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_CGC_CNTL +#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 +#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L +//UVD_JPEG_ENC_SCRATCH0 +#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_SOFT_RST +#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 +#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 +#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L +#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L + + +// addressBlock: uvd0_uvd_jrbc_dec +//UVD_JRBC_RB_WPTR +#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC_RB_CNTL +#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC_IB_SIZE +#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_URGENT_CNTL +#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_JRBC_RB_REF_DATA +#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC_RB_COND_RD_TIMER +#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC_SOFT_RESET +#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC_STATUS +#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_JRBC_RB_RPTR +#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_JRBC_RB_BUF_STATUS +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC_IB_BUF_STATUS +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC_IB_SIZE_UPDATE +#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_IB_COND_RD_TIMER +#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC_IB_REF_DATA +#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JPEG_PREEMPT_CMD +#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 +#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 +#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 +#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L +#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L +#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L +//UVD_JPEG_PREEMPT_FENCE_DATA0 +#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 +#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_PREEMPT_FENCE_DATA1 +#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 +#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL +//UVD_JRBC_RB_SIZE +#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L +//UVD_JRBC_SCRATCH0 +#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_jrbc_enc_dec +//UVD_JRBC_ENC_RB_WPTR +#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC_ENC_RB_CNTL +#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC_ENC_IB_SIZE +#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_ENC_URGENT_CNTL +#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_JRBC_ENC_RB_REF_DATA +#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC_ENC_RB_COND_RD_TIMER +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC_ENC_SOFT_RESET +#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC_ENC_STATUS +#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_JRBC_ENC_RB_RPTR +#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_JRBC_ENC_RB_BUF_STATUS +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC_ENC_IB_BUF_STATUS +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC_ENC_IB_SIZE_UPDATE +#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC_ENC_IB_COND_RD_TIMER +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC_ENC_IB_REF_DATA +#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_PREEMPT_CMD +#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 +#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 +#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 +#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L +#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L +#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L +//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 +#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 +#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 +#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 +#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL +//UVD_JRBC_ENC_RB_SIZE +#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L +//UVD_JRBC_ENC_SCRATCH0 +#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_jmi_dec +//UVD_JMI_CTRL +#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 +#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 +#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 +#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 +#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 +#define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 +#define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 +#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L +#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L +#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L +#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L +#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L +#define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L +#define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L +//UVD_LMI_JRBC_CTRL +#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_LMI_JPEG_CTRL +#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_JMI_EJRBC_CTRL +#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_LMI_EJPEG_CTRL +#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_LMI_JRBC_IB_VMID +#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 +#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL +#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L +#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_LMI_JRBC_RB_VMID +#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 +#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL +#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L +#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_LMI_JPEG_VMID +#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 +#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 +#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 +#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL +#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L +#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L +//UVD_JMI_ENC_JRBC_IB_VMID +#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 +#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 +#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL +#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L +#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_JMI_ENC_JRBC_RB_VMID +#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 +#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 +#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL +#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L +#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_JMI_ENC_JPEG_VMID +#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 +#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 +#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa +#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf +#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 +#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 +#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL +#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L +#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L +#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L +#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L +#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L +//UVD_JMI_PERFMON_CTRL +#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 +#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 +#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L +#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L +//UVD_JMI_PERFMON_COUNT_LO +#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 +#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL +//UVD_JMI_PERFMON_COUNT_HI +#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 +#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL +//UVD_LMI_JPEG_READ_64BIT_BAR_LOW +#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW +#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH +#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW +#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH +#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_PREEMPT_VMID +#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL +//UVD_LMI_ENC_JPEG_PREEMPT_VMID +#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 +#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL +//UVD_LMI_JPEG2_VMID +#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 +#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 +#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL +#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L +//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW +#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH +#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW +#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH +#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_CTRL2 +#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L +//UVD_JMI_DEC_SWAP_CNTL +#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa +#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L +#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L +//UVD_JMI_ENC_SWAP_CNTL +#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 +#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 +#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 +#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa +#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc +#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe +#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 +#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 +#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 +#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 +#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL +#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L +#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L +#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L +#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L +#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L +#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L +#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L +#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L +#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L +#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L +//UVD_JMI_CNTL +#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 +#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 +#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L +#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L +//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW +#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH +#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_JMI_DEC_SWAP_CNTL2 +#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 +#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 +#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L +#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL + + +// addressBlock: uvd0_uvd_jpeg_common_dec +//JPEG_SOFT_RESET_STATUS +#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 +#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 +#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 +#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 +#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 +#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 +#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L +#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L +#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L +#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L +#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L +#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L +//JPEG_SYS_INT_EN +#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 +#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 +#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 +#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 +#define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 +#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 +#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L +#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L +#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L +#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L +#define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L +#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L +//JPEG_SYS_INT_STATUS +#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 +#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 +#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 +#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 +#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 +#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 +#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L +#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L +#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L +#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L +#define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L +#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L +//JPEG_SYS_INT_ACK +#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 +#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 +#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 +#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 +#define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 +#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 +#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L +#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L +#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L +#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L +#define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L +#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L +//JPEG_MASTINT_EN +#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L +//JPEG_IH_CTRL +#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 +#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 +#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 +#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 +#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 +#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 +#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L +#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L +#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L +#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L +#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L +#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L +//JRBBM_ARB_CTRL +#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 +#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 +#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 +#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L +#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L +#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L + + +// addressBlock: uvd0_uvd_jpeg_common_sclk_dec +//JPEG_CGC_GATE +#define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 +#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 +#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 +#define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 +#define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 +#define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L +#define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L +#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L +#define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L +#define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L +//JPEG_CGC_CTRL +#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 +#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 +#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa +#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb +#define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc +#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 +#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 +#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 +#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 +#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 +#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL +#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L +#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L +#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L +#define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L +#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L +#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L +#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L +#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L +#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L +//JPEG_CGC_STATUS +#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 +#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 +#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 +#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 +#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 +#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 +#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 +#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 +#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 +#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L +#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L +#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L +#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L +#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L +#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L +#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L +#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L +#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L +//JPEG_COMN_CGC_MEM_CTRL +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 +#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 +#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L +#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L +#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L +//JPEG_DEC_CGC_MEM_CTRL +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L +#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L +//JPEG2_DEC_CGC_MEM_CTRL +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L +#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L +//JPEG_ENC_CGC_MEM_CTRL +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L +//JPEG_SOFT_RESET2 +#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 +#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L +//JPEG_PERF_BANK_CONF +#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 +#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 +#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 +#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL +#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L +#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L +//JPEG_PERF_BANK_EVENT_SEL +#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 +#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 +#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 +#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 +#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL +#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L +#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L +#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L +//JPEG_PERF_BANK_COUNT0 +#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT1 +#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT2 +#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT3 +#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_pg_dec +//UVD_PGFSM_CONFIG +#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 +#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 +#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 +#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 +#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 +#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa +#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc +#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe +#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 +#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 +#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 +#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 +#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L +#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL +#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L +#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L +#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L +#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L +#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L +#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L +#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L +#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L +#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L +#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L +//UVD_PGFSM_STATUS +#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 +#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 +#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 +#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 +#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 +#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa +#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc +#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe +#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 +#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 +#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 +#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 +#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L +#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL +#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L +#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L +#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L +#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L +#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L +#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L +#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L +#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L +#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L +#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L +//UVD_POWER_STATUS +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 +#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 +#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 +#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 +#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb +#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L +#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L +#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L +#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L +#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L +#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L +#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L +//UVD_PG_IND_INDEX +#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 +#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL +//UVD_PG_IND_DATA +#define UVD_PG_IND_DATA__DATA__SHIFT 0x0 +#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL +//CC_UVD_HARVESTING +#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 +#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 +#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L +#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L +//UVD_JPEG_POWER_STATUS +#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 +#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 +#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 +#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 +#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f +#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L +#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L +#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L +#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L +#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L +//UVD_DPG_LMA_CTL +#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 +#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 +#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 +#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 +#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 +#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L +#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L +#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L +#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L +#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L +//UVD_DPG_LMA_DATA +#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 +#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL +//UVD_DPG_LMA_MASK +#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 +#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL +//UVD_DPG_PAUSE +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L +//UVD_SCRATCH1 +#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 +#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH2 +#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 +#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH3 +#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 +#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH4 +#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 +#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH5 +#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 +#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH6 +#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 +#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH7 +#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 +#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH8 +#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 +#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH9 +#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 +#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH10 +#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 +#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH11 +#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 +#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH12 +#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 +#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH13 +#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 +#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH14 +#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 +#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL +//UVD_FREE_COUNTER_REG +#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 +#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_DPG_VCPU_CACHE_OFFSET0 +#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_VMID +#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL +//UVD_PF_STATUS +#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 +#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 +#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 +#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 +#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 +#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 +#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 +#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 +#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 +#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 +#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa +#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb +#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc +#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd +#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe +#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf +#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 +#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 +#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 +#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L +#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L +#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L +#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L +#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L +#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L +#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L +#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L +#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L +#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L +#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L +#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L +#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L +#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L +#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L +#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L +#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L +#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L +#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L +//UVD_DPG_CLK_EN_VCPU_REPORT +#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 +#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 +#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L +#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL +//UVD_GFX8_ADDR_CONFIG +#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +//UVD_GFX10_ADDR_CONFIG +#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//UVD_GPCNT2_CNTL +#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 +#define UVD_GPCNT2_CNTL__START__SHIFT 0x1 +#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 +#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L +#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L +#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L +//UVD_GPCNT2_TARGET_LOWER +#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 +#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL +//UVD_GPCNT2_STATUS_LOWER +#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 +#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL +//UVD_GPCNT2_TARGET_UPPER +#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 +#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL +//UVD_GPCNT2_STATUS_UPPER +#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 +#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL +//UVD_GPCNT3_CNTL +#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 +#define UVD_GPCNT3_CNTL__START__SHIFT 0x1 +#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 +#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 +#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa +#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L +#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L +#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L +#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L +#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L +//UVD_GPCNT3_TARGET_LOWER +#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 +#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL +//UVD_GPCNT3_STATUS_LOWER +#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 +#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL +//UVD_GPCNT3_TARGET_UPPER +#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 +#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL +//UVD_GPCNT3_STATUS_UPPER +#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 +#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL + + +// addressBlock: uvd0_uvddec +//UVD_STATUS +#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 +#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 +#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f +#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L +#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL +#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L +#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L +//UVD_ENC_PIPE_BUSY +#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 +#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 +#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 +#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 +#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 +#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 +#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 +#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 +#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 +#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 +#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa +#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb +#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 +#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e +#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L +#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L +#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L +#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L +#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L +#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L +#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L +#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L +#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L +#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L +#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L +#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L +#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L +//UVD_SOFT_RESET +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 +#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa +#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb +#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 +#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L +#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L +#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L +#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L +#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L +//UVD_SOFT_RESET2 +#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 +#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L +#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_MMSCH_SOFT_RESET +#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 +#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 +#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f +#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L +#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L +#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L +//UVD_CGC_GATE +#define UVD_CGC_GATE__SYS__SHIFT 0x0 +#define UVD_CGC_GATE__UDEC__SHIFT 0x1 +#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 +#define UVD_CGC_GATE__REGS__SHIFT 0x3 +#define UVD_CGC_GATE__RBC__SHIFT 0x4 +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 +#define UVD_CGC_GATE__IDCT__SHIFT 0x7 +#define UVD_CGC_GATE__MPRD__SHIFT 0x8 +#define UVD_CGC_GATE__MPC__SHIFT 0x9 +#define UVD_CGC_GATE__LBSI__SHIFT 0xa +#define UVD_CGC_GATE__LRBBM__SHIFT 0xb +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 +#define UVD_CGC_GATE__WCB__SHIFT 0x11 +#define UVD_CGC_GATE__VCPU__SHIFT 0x12 +#define UVD_CGC_GATE__MMSCH__SHIFT 0x14 +#define UVD_CGC_GATE__SYS_MASK 0x00000001L +#define UVD_CGC_GATE__UDEC_MASK 0x00000002L +#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L +#define UVD_CGC_GATE__REGS_MASK 0x00000008L +#define UVD_CGC_GATE__RBC_MASK 0x00000010L +#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L +#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L +#define UVD_CGC_GATE__IDCT_MASK 0x00000080L +#define UVD_CGC_GATE__MPRD_MASK 0x00000100L +#define UVD_CGC_GATE__MPC_MASK 0x00000200L +#define UVD_CGC_GATE__LBSI_MASK 0x00000400L +#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L +#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L +#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L +#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L +#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L +#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L +#define UVD_CGC_GATE__WCB_MASK 0x00020000L +#define UVD_CGC_GATE__VCPU_MASK 0x00040000L +#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L +//UVD_CGC_STATUS +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a +#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b +#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c +#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L +#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L +#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L +#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L +//UVD_CGC_CTRL +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d +#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L +#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L +//UVD_CGC_UDEC_STATUS +#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 +#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 +#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 +#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 +#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 +#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 +#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 +#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 +#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 +#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 +#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa +#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb +#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc +#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd +#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe +#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L +#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L +#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L +#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L +#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L +#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L +#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L +#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L +#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L +#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L +#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L +#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L +#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L +#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L +#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L +//UVD_SUVD_CGC_GATE +#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L +//UVD_SUVD_CGC_STATUS +#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 +#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 +#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 +#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 +#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 +#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe +#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf +#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 +#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 +#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 +#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 +#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 +#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 +#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a +#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b +#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c +#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L +#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L +#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L +#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L +#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L +#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L +#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L +#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L +#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L +#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L +#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L +#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L +#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L +#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L +#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L +#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L +//UVD_SUVD_CGC_CTRL +#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +//UVD_GPCOM_VCPU_CMD +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L +//UVD_GPCOM_VCPU_DATA0 +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_GPCOM_VCPU_DATA1 +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_GPCOM_SYS_CMD +#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L +//UVD_GPCOM_SYS_DATA0 +#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_GPCOM_SYS_DATA1 +#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 +#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_VCPU_INT_EN +#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 +#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 +#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 +#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 +#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 +#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 +#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 +#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 +#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa +#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb +#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc +#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 +#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 +#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 +#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 +#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 +#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a +#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b +#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c +#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d +#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e +#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f +#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L +#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L +#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L +#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L +#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L +#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L +#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L +#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L +#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L +#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L +#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L +#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L +#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L +#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L +#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L +#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L +#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L +#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L +#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L +#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L +#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L +#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L +//UVD_VCPU_INT_ACK +#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 +#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 +#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 +#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 +#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 +#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 +#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 +#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 +#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa +#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb +#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc +#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 +#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 +#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 +#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 +#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 +#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a +#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b +#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c +#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d +#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e +#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f +#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L +#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L +#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L +#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L +#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L +#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L +#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L +#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L +#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L +#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L +#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L +#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L +#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L +#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L +#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L +#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L +#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L +#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L +#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L +#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L +#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L +#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L +//UVD_VCPU_INT_ROUTE +#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 +#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 +#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 +#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L +#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L +#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L +//UVD_ENC_VCPU_INT_EN +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L +//UVD_ENC_VCPU_INT_ACK +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L +//UVD_MASTINT_EN +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L +#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L +//UVD_SYS_INT_EN +#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 +#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 +#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 +#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 +#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 +#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb +#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc +#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 +#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 +#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 +#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 +#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b +#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c +#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d +#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f +#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L +#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L +#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L +#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L +#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L +#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L +#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L +#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L +#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L +#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L +#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L +#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L +#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L +#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L +#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L +//UVD_SYS_INT_STATUS +#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 +#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 +#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 +#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 +#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb +#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc +#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 +#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 +#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 +#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 +#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b +#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c +#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d +#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f +#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L +#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L +#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L +#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L +#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L +#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L +#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L +#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L +#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L +#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L +#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L +#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L +#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L +#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L +//UVD_SYS_INT_ACK +#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 +#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 +#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 +#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 +#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb +#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc +#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 +#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 +#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 +#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b +#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c +#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d +#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f +#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L +#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L +#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L +#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L +#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L +#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L +#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L +#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L +#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L +#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L +#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L +#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L +#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L +//UVD_JOB_DONE +#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 +#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L +//UVD_CBUF_ID +#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 +#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL +//UVD_CONTEXT_ID +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL +//UVD_CONTEXT_ID2 +#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 +#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL +//UVD_NO_OP +#define UVD_NO_OP__NO_OP__SHIFT 0x0 +#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL +//UVD_RB_BASE_LO +#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI +#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE +#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR +#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR +#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_BASE_LO2 +#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI2 +#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE2 +#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR2 +#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR2 +#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_BASE_LO3 +#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI3 +#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE3 +#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR3 +#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR3 +#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_BASE_LO4 +#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI4 +#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE4 +#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_RPTR4 +#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR4 +#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L +//UVD_OUT_RB_BASE_LO +#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_OUT_RB_BASE_HI +#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_OUT_RB_SIZE +#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L +//UVD_OUT_RB_RPTR +#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_OUT_RB_WPTR +#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_ARB_CTRL +#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 +#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 +#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 +#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 +#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 +#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 +#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 +#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 +#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 +#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L +#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L +#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L +#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L +#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L +#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L +#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L +#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L +#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L +//UVD_CTX_INDEX +#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 +#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL +//UVD_CTX_DATA +#define UVD_CTX_DATA__DATA__SHIFT 0x0 +#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL +//UVD_CXW_WR +#define UVD_CXW_WR__DAT__SHIFT 0x0 +#define UVD_CXW_WR__STAT__SHIFT 0x1f +#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL +#define UVD_CXW_WR__STAT_MASK 0x80000000L +//UVD_CXW_WR_INT_ID +#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 +#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL +//UVD_CXW_WR_INT_CTX_ID +#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 +#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL +//UVD_CXW_INT_ID +#define UVD_CXW_INT_ID__ID__SHIFT 0x0 +#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL +//UVD_TOP_CTRL +#define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 +#define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 +#define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL +#define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L +//UVD_YBASE +#define UVD_YBASE__DUM__SHIFT 0x0 +#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL +//UVD_UVBASE +#define UVD_UVBASE__DUM__SHIFT 0x0 +#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL +//UVD_PITCH +#define UVD_PITCH__DUM__SHIFT 0x0 +#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL +//UVD_WIDTH +#define UVD_WIDTH__DUM__SHIFT 0x0 +#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL +//UVD_HEIGHT +#define UVD_HEIGHT__DUM__SHIFT 0x0 +#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL +//UVD_PICCOUNT +#define UVD_PICCOUNT__DUM__SHIFT 0x0 +#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL +//UVD_SCRATCH_NP +#define UVD_SCRATCH_NP__DATA__SHIFT 0x0 +#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL +//UVD_VERSION +#define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 +#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 +#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL +#define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L +//UVD_GP_SCRATCH0 +#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH1 +#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH2 +#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH3 +#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH4 +#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH5 +#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH6 +#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH7 +#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH8 +#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH9 +#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH10 +#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH11 +#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH12 +#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH13 +#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH14 +#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH15 +#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH16 +#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH17 +#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH18 +#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH19 +#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH20 +#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH21 +#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH22 +#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH23 +#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_ecpudec +//UVD_VCPU_CACHE_OFFSET0 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET1 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE1 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET2 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE2 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET3 +#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE3 +#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET4 +#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE4 +#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET5 +#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE5 +#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET6 +#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE6 +#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET7 +#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE7 +#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET8 +#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE8 +#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL +//UVD_VCPU_NONCACHE_OFFSET0 +#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL +//UVD_VCPU_NONCACHE_SIZE0 +#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL +//UVD_VCPU_NONCACHE_OFFSET1 +#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL +//UVD_VCPU_NONCACHE_SIZE1 +#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL +//UVD_VCPU_CNTL +#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 +#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 +#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa +#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb +#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 +#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 +#define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c +#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL +#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L +#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L +#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L +#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L +#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L +#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L +#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L +#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L +//UVD_VCPU_PRID +#define UVD_VCPU_PRID__PRID__SHIFT 0x0 +#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL +//UVD_VCPU_TRCE +#define UVD_VCPU_TRCE__PC__SHIFT 0x0 +#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL +//UVD_VCPU_TRCE_RD +#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 +#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: uvd0_uvd_mpcdec +//UVD_MP_SWAP_CNTL +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e +#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L +#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL +#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L +#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L +#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L +#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L +#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L +#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L +#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L +#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L +#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L +#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L +#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L +#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L +#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L +#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L +//UVD_MPC_LUMA_SRCH +#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 +#define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_LUMA_HIT +#define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 +#define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_LUMA_HITPEND +#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 +#define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_CHROMA_SRCH +#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 +#define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_CHROMA_HIT +#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 +#define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_CHROMA_HITPEND +#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 +#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL +//UVD_MPC_CNTL +#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 +#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 +#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 +#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 +#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 +#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 +#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L +#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L +#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L +#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L +#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L +#define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L +//UVD_MPC_PITCH +#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 +#define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL +//UVD_MPC_SET_MUXA0 +#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc +#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL +#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L +#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L +#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L +//UVD_MPC_SET_MUXA1 +#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc +#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL +#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L +//UVD_MPC_SET_MUXB0 +#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 +#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 +#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc +#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 +#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 +#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL +#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L +#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L +#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L +//UVD_MPC_SET_MUXB1 +#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 +#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 +#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc +#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL +#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L +#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L +//UVD_MPC_SET_MUX +#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 +#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 +#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 +#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L +#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L +#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L +//UVD_MPC_SET_ALU +#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 +#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 +#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L +#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L +//UVD_MPC_PERF0 +#define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 +#define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL +//UVD_MPC_PERF1 +#define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 +#define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL + + +// addressBlock: uvd0_uvd_rbcdec +//UVD_RBC_IB_SIZE +#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_RBC_IB_SIZE_UPDATE +#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_RBC_RB_CNTL +#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c +#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL +#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L +#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L +#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L +#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L +#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L +//UVD_RBC_RB_RPTR_ADDR +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 +#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL +//UVD_RBC_RB_RPTR +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_RBC_RB_WPTR +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RBC_VCPU_ACCESS +#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 +#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L +//UVD_RBC_READ_REQ_URGENT_CNTL +#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_RBC_RB_WPTR_CNTL +#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 +#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL +//UVD_RBC_WPTR_STATUS +#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 +#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L +//UVD_RBC_WPTR_POLL_CNTL +#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 +#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL +#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//UVD_RBC_WPTR_POLL_ADDR +#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 +#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL +//UVD_SEMA_CMD +#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 +#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 +#define UVD_SEMA_CMD__MODE__SHIFT 0x6 +#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 +#define UVD_SEMA_CMD__VMID__SHIFT 0x8 +#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL +#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L +#define UVD_SEMA_CMD__MODE_MASK 0x00000040L +#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L +#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L +//UVD_SEMA_ADDR_LOW +#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 +#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL +//UVD_SEMA_ADDR_HIGH +#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 +#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL +//UVD_ENGINE_CNTL +#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 +#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 +#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 +#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L +#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L +#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L +//UVD_SEMA_TIMEOUT_STATUS +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L +#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L +//UVD_SEMA_CNTL +#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 +#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L +#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L +//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL +#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L +//UVD_JOB_START +#define UVD_JOB_START__JOB_START__SHIFT 0x0 +#define UVD_JOB_START__JOB_START_MASK 0x00000001L +//UVD_RBC_BUF_STATUS +#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 +#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 +#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 +#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 +#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL +#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L +#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L +#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L +#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L +#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L + + +// addressBlock: uvd0_uvdgendec +//UVD_LCM_CGC_CNTRL +#define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT 0x12 +#define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT 0x13 +#define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT 0x14 +#define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT 0x1c +#define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK 0x00040000L +#define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK 0x00080000L +#define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK 0x0FF00000L +#define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK 0xF0000000L + + +// addressBlock: uvd0_lmi_adpdec +//UVD_LMI_RBC_RB_64BIT_BAR_LOW +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_IB_64BIT_BAR_LOW +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_LBSI_64BIT_BAR_LOW +#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_LBSI_64BIT_BAR_HIGH +#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW +#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW +#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC_VMID +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L +//UVD_LMI_MMSCH_CTRL +#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 +#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 +#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 +#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc +#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L +#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L +#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L +#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L +//UVD_LMI_ARB_CTRL2 +#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 +#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa +#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 +#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L +#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L +#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L +//UVD_LMI_VCPU_CACHE_VMIDS_MULTI +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L +//UVD_LMI_VCPU_NC_VMIDS_MULTI +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L +//UVD_LMI_LAT_CTRL +#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 +#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 +#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 +#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa +#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb +#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 +#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL +#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L +#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L +#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L +#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L +#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L +//UVD_LMI_LAT_CNTR +#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 +#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 +#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL +#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L +//UVD_LMI_AVG_LAT_CNTR +#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 +#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L +//UVD_LMI_SPH +#define UVD_LMI_SPH__ADDR__SHIFT 0x0 +#define UVD_LMI_SPH__STS__SHIFT 0x1c +#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e +#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f +#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL +#define UVD_LMI_SPH__STS_MASK 0x30000000L +#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L +#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L +//UVD_LMI_VCPU_CACHE_VMID +#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL +//UVD_LMI_CTRL2 +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 +#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 +#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 +#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a +#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L +#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L +#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L +#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L +#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L +//UVD_LMI_URGENT_CTRL +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L +//UVD_LMI_CTRL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a +#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b +#define UVD_LMI_CTRL__RFU__SHIFT 0x1e +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L +#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L +#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L +#define UVD_LMI_CTRL__RFU_MASK 0xC0000000L +//UVD_LMI_STATUS +#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 +#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 +#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 +#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 +#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa +#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd +#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 +#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 +#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 +#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 +#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 +#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L +#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L +#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L +#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L +#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L +#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L +#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L +#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L +#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L +#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L +//UVD_LMI_PERFMON_CTRL +#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 +#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 +#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L +#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L +//UVD_LMI_PERFMON_COUNT_LO +#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 +#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL +//UVD_LMI_PERFMON_COUNT_HI +#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 +#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL +//UVD_LMI_RBC_RB_VMID +#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 +#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL +//UVD_LMI_RBC_IB_VMID +#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 +#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL +//UVD_LMI_MC_CREDITS +#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 +#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 +#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 +#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 +#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL +#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L +#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L +#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L + + +// addressBlock: uvd0_uvdnpdec +//MDM_DMA_CMD +#define MDM_DMA_CMD__MDM_DMA_CMD__SHIFT 0x0 +#define MDM_DMA_CMD__MDM_DMA_CMD_MASK 0xFFFFFFFFL +//MDM_DMA_STATUS +#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY__SHIFT 0x0 +#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY__SHIFT 0x1 +#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY__SHIFT 0x2 +#define MDM_DMA_STATUS__RB_DMA_WR_BUSY__SHIFT 0x3 +#define MDM_DMA_STATUS__RB_DMA_RD_BUSY__SHIFT 0x4 +#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY__SHIFT 0x5 +#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY__SHIFT 0x6 +#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY_MASK 0x00000001L +#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY_MASK 0x00000002L +#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY_MASK 0x00000004L +#define MDM_DMA_STATUS__RB_DMA_WR_BUSY_MASK 0x00000008L +#define MDM_DMA_STATUS__RB_DMA_RD_BUSY_MASK 0x00000010L +#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY_MASK 0x00000020L +#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY_MASK 0x00000040L +//MDM_DMA_CTL +#define MDM_DMA_CTL__MDM_BYPASS__SHIFT 0x0 +#define MDM_DMA_CTL__FOUR_CMD__SHIFT 0x1 +#define MDM_DMA_CTL__ENCODE_MODE__SHIFT 0x2 +#define MDM_DMA_CTL__VP9_DEC_MODE__SHIFT 0x3 +#define MDM_DMA_CTL__SW_DRST__SHIFT 0x1f +#define MDM_DMA_CTL__MDM_BYPASS_MASK 0x00000001L +#define MDM_DMA_CTL__FOUR_CMD_MASK 0x00000002L +#define MDM_DMA_CTL__ENCODE_MODE_MASK 0x00000004L +#define MDM_DMA_CTL__VP9_DEC_MODE_MASK 0x00000008L +#define MDM_DMA_CTL__SW_DRST_MASK 0x80000000L +//MDM_ENC_PIPE_BUSY +#define MDM_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 +#define MDM_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 +#define MDM_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 +#define MDM_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 +#define MDM_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 +#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 +#define MDM_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 +#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 +#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 +#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 +#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa +#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb +#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY__SHIFT 0xc +#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY__SHIFT 0xd +#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 +#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 +#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 +#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 +#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 +#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 +#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 +#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c +#define MDM_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L +#define MDM_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L +#define MDM_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L +#define MDM_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L +#define MDM_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L +#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L +#define MDM_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L +#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L +#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L +#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L +#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L +#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L +#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY_MASK 0x00001000L +#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY_MASK 0x00002000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L +#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L +#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L +#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L +#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L +#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L +//MDM_WIG_PIPE_BUSY +#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY__SHIFT 0x0 +#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY__SHIFT 0x1 +#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY__SHIFT 0x2 +#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL__SHIFT 0x3 +#define MDM_WIG_PIPE_BUSY__LCM_BUSY__SHIFT 0x4 +#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x5 +#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x6 +#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x7 +#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0x8 +#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0x9 +#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0xa +#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0xb +#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0xc +#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0xd +#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0xe +#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0xf +#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x10 +#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x11 +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x12 +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x13 +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x14 +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x15 +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x16 +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY__SHIFT 0x17 +#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x18 +#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x19 +#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY__SHIFT 0x1a +#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY__SHIFT 0x1b +#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY__SHIFT 0x1c +#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY__SHIFT 0x1d +#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY_MASK 0x00000001L +#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY_MASK 0x00000002L +#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY_MASK 0x00000004L +#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL_MASK 0x00000008L +#define MDM_WIG_PIPE_BUSY__LCM_BUSY_MASK 0x00000010L +#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000020L +#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000040L +#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000080L +#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000100L +#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000200L +#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00000400L +#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00000800L +#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00001000L +#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00002000L +#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00004000L +#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00008000L +#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00010000L +#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00020000L +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x00040000L +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x00080000L +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x00100000L +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x00200000L +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x00400000L +#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY_MASK 0x00800000L +#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x01000000L +#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x02000000L +#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY_MASK 0x04000000L +#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY_MASK 0x08000000L +#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY_MASK 0x10000000L +#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY_MASK 0x20000000L + + +// addressBlock: lmi_adp_indirect +//UVD_LMI_CRC0 +#define UVD_LMI_CRC0__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC1 +#define UVD_LMI_CRC1__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC2 +#define UVD_LMI_CRC2__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC3 +#define UVD_LMI_CRC3__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 24cfe84d7322..e88541d67aa0 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -1789,6 +1789,92 @@ struct atom_smc_dpm_info_v4_5 }; +struct atom_smc_dpm_info_v4_6 +{ + struct atom_common_table_header table_header; + // section: board parameters + uint32_t i2c_padding[3]; // old i2c control are moved to new area + + uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. + uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. + + uint8_t vddgfxvrmapping; // use vr_mapping* bitfields + uint8_t vddsocvrmapping; // use vr_mapping* bitfields + uint8_t vddmemvrmapping; // use vr_mapping* bitfields + uint8_t boardvrmapping; // use vr_mapping* bitfields + + uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode + uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) + uint8_t padding8_v[2]; + + // telemetry settings + uint16_t gfxmaxcurrent; // in amps + uint8_t gfxoffset; // in amps + uint8_t padding_telemetrygfx; + + uint16_t socmaxcurrent; // in amps + uint8_t socoffset; // in amps + uint8_t padding_telemetrysoc; + + uint16_t memmaxcurrent; // in amps + uint8_t memoffset; // in amps + uint8_t padding_telemetrymem; + + uint16_t boardmaxcurrent; // in amps + uint8_t boardoffset; // in amps + uint8_t padding_telemetryboardinput; + + // gpio settings + uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event + uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event + uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event + uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event + + // gfxclk pll spread spectrum + uint8_t pllgfxclkspreadenabled; // on or off + uint8_t pllgfxclkspreadpercent; // q4.4 + uint16_t pllgfxclkspreadfreq; // khz + + // uclk spread spectrum + uint8_t uclkspreadenabled; // on or off + uint8_t uclkspreadpercent; // q4.4 + uint16_t uclkspreadfreq; // khz + + // fclk spread spectrum + uint8_t fclkspreadenabled; // on or off + uint8_t fclkspreadpercent; // q4.4 + uint16_t fclkspreadfreq; // khz + + + // gfxclk fll spread spectrum + uint8_t fllgfxclkspreadenabled; // on or off + uint8_t fllgfxclkspreadpercent; // q4.4 + uint16_t fllgfxclkspreadfreq; // khz + + // i2c controller structure + struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; + + // memory section + uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. + + uint8_t drambitwidth; // for dram use only. see dram bit width type defines + uint8_t paddingmem[3]; + + // total board power + uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power + uint16_t boardpadding; + + // section: xgmi training + uint8_t xgmilinkspeed[4]; + uint8_t xgmilinkwidth[4]; + + uint16_t xgmifclkfreq[4]; + uint16_t xgmisocvoltage[4]; + + // reserved + uint32_t boardreserved[10]; +}; + /* *************************************************************************** Data Table asic_profiling_info structure diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 5b1ebb7f995a..27cf0afaa0b4 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -142,6 +142,7 @@ enum PP_SMC_POWER_PROFILE { PP_SMC_POWER_PROFILE_VR = 0x4, PP_SMC_POWER_PROFILE_COMPUTE = 0x5, PP_SMC_POWER_PROFILE_CUSTOM = 0x6, + PP_SMC_POWER_PROFILE_COUNT, }; enum { @@ -171,6 +172,13 @@ enum PP_HWMON_TEMP { PP_TEMP_MAX }; +enum pp_mp1_state { + PP_MP1_STATE_NONE, + PP_MP1_STATE_SHUTDOWN, + PP_MP1_STATE_UNLOAD, + PP_MP1_STATE_RESET, +}; + #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 @@ -266,6 +274,8 @@ struct amd_pm_funcs { int (*get_power_profile_mode)(void *handle, char *buf); int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size); + int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); + int (*smu_i2c_bus_access)(void *handle, bool acquire); /* export to DC */ u32 (*get_sclk)(void *handle, bool low); u32 (*get_mclk)(void *handle, bool low); @@ -301,6 +311,7 @@ struct amd_pm_funcs { int (*set_asic_baco_state)(void *handle, int state); int (*get_ppfeature_status)(void *handle, char *buf); int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); + int (*asic_reset_mode_2)(void *handle); }; #endif diff --git a/drivers/gpu/drm/amd/include/navi12_ip_offset.h b/drivers/gpu/drm/amd/include/navi12_ip_offset.h new file mode 100644 index 000000000000..6c2cc6296c06 --- /dev/null +++ b/drivers/gpu/drm/amd/include/navi12_ip_offset.h @@ -0,0 +1,1119 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _navi12_ip_offset_HEADER +#define _navi12_ip_offset_HEADER + +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 5 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + + +static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, + { { 0x00016E00, 0x02401C00, 0, 0, 0 } }, + { { 0x00017000, 0x02402000, 0, 0, 0 } }, + { { 0x00017200, 0x02402400, 0, 0, 0 } }, + { { 0x0001B000, 0x0242D800, 0, 0, 0 } }, + { { 0x00017E00, 0x0240BC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, + { { 0x00054000, 0x02425C00, 0, 0, 0 } }, + { { 0x00094000, 0x02426000, 0, 0, 0 } }, + { { 0x000D4000, 0x02426400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; + + +#define ATHUB_BASE__INST0_SEG0 0x00000C00 +#define ATHUB_BASE__INST0_SEG1 0x02408C00 +#define ATHUB_BASE__INST0_SEG2 0 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0x02401800 +#define CLK_BASE__INST0_SEG2 0 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 + +#define CLK_BASE__INST1_SEG0 0x00016E00 +#define CLK_BASE__INST1_SEG1 0x02401C00 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 + +#define CLK_BASE__INST2_SEG0 0x00017000 +#define CLK_BASE__INST2_SEG1 0x02402000 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 + +#define CLK_BASE__INST3_SEG0 0x00017200 +#define CLK_BASE__INST3_SEG1 0x02402400 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 + +#define CLK_BASE__INST4_SEG0 0x0001B000 +#define CLK_BASE__INST4_SEG1 0x0242D800 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 + +#define CLK_BASE__INST5_SEG0 0x00017E00 +#define CLK_BASE__INST5_SEG1 0x0240BC00 +#define CLK_BASE__INST5_SEG2 0 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 + +#define CLK_BASE__INST6_SEG0 0 +#define CLK_BASE__INST6_SEG1 0 +#define CLK_BASE__INST6_SEG2 0 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x0240B800 +#define DF_BASE__INST0_SEG2 0 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 + +#define DIO_BASE__INST0_SEG0 0x02404000 +#define DIO_BASE__INST0_SEG1 0 +#define DIO_BASE__INST0_SEG2 0 +#define DIO_BASE__INST0_SEG3 0 +#define DIO_BASE__INST0_SEG4 0 + +#define DIO_BASE__INST1_SEG0 0 +#define DIO_BASE__INST1_SEG1 0 +#define DIO_BASE__INST1_SEG2 0 +#define DIO_BASE__INST1_SEG3 0 +#define DIO_BASE__INST1_SEG4 0 + +#define DIO_BASE__INST2_SEG0 0 +#define DIO_BASE__INST2_SEG1 0 +#define DIO_BASE__INST2_SEG2 0 +#define DIO_BASE__INST2_SEG3 0 +#define DIO_BASE__INST2_SEG4 0 + +#define DIO_BASE__INST3_SEG0 0 +#define DIO_BASE__INST3_SEG1 0 +#define DIO_BASE__INST3_SEG2 0 +#define DIO_BASE__INST3_SEG3 0 +#define DIO_BASE__INST3_SEG4 0 + +#define DIO_BASE__INST4_SEG0 0 +#define DIO_BASE__INST4_SEG1 0 +#define DIO_BASE__INST4_SEG2 0 +#define DIO_BASE__INST4_SEG3 0 +#define DIO_BASE__INST4_SEG4 0 + +#define DIO_BASE__INST5_SEG0 0 +#define DIO_BASE__INST5_SEG1 0 +#define DIO_BASE__INST5_SEG2 0 +#define DIO_BASE__INST5_SEG3 0 +#define DIO_BASE__INST5_SEG4 0 + +#define DIO_BASE__INST6_SEG0 0 +#define DIO_BASE__INST6_SEG1 0 +#define DIO_BASE__INST6_SEG2 0 +#define DIO_BASE__INST6_SEG3 0 +#define DIO_BASE__INST6_SEG4 0 + +#define DMU_BASE__INST0_SEG0 0x00000012 +#define DMU_BASE__INST0_SEG1 0x000000C0 +#define DMU_BASE__INST0_SEG2 0x000034C0 +#define DMU_BASE__INST0_SEG3 0x00009000 +#define DMU_BASE__INST0_SEG4 0x02403C00 + +#define DMU_BASE__INST1_SEG0 0 +#define DMU_BASE__INST1_SEG1 0 +#define DMU_BASE__INST1_SEG2 0 +#define DMU_BASE__INST1_SEG3 0 +#define DMU_BASE__INST1_SEG4 0 + +#define DMU_BASE__INST2_SEG0 0 +#define DMU_BASE__INST2_SEG1 0 +#define DMU_BASE__INST2_SEG2 0 +#define DMU_BASE__INST2_SEG3 0 +#define DMU_BASE__INST2_SEG4 0 + +#define DMU_BASE__INST3_SEG0 0 +#define DMU_BASE__INST3_SEG1 0 +#define DMU_BASE__INST3_SEG2 0 +#define DMU_BASE__INST3_SEG3 0 +#define DMU_BASE__INST3_SEG4 0 + +#define DMU_BASE__INST4_SEG0 0 +#define DMU_BASE__INST4_SEG1 0 +#define DMU_BASE__INST4_SEG2 0 +#define DMU_BASE__INST4_SEG3 0 +#define DMU_BASE__INST4_SEG4 0 + +#define DMU_BASE__INST5_SEG0 0 +#define DMU_BASE__INST5_SEG1 0 +#define DMU_BASE__INST5_SEG2 0 +#define DMU_BASE__INST5_SEG3 0 +#define DMU_BASE__INST5_SEG4 0 + +#define DMU_BASE__INST6_SEG0 0 +#define DMU_BASE__INST6_SEG1 0 +#define DMU_BASE__INST6_SEG2 0 +#define DMU_BASE__INST6_SEG3 0 +#define DMU_BASE__INST6_SEG4 0 + +#define DPCS_BASE__INST0_SEG0 0x00000012 +#define DPCS_BASE__INST0_SEG1 0x000000C0 +#define DPCS_BASE__INST0_SEG2 0x000034C0 +#define DPCS_BASE__INST0_SEG3 0x00009000 +#define DPCS_BASE__INST0_SEG4 0x02403C00 + +#define DPCS_BASE__INST1_SEG0 0 +#define DPCS_BASE__INST1_SEG1 0 +#define DPCS_BASE__INST1_SEG2 0 +#define DPCS_BASE__INST1_SEG3 0 +#define DPCS_BASE__INST1_SEG4 0 + +#define DPCS_BASE__INST2_SEG0 0 +#define DPCS_BASE__INST2_SEG1 0 +#define DPCS_BASE__INST2_SEG2 0 +#define DPCS_BASE__INST2_SEG3 0 +#define DPCS_BASE__INST2_SEG4 0 + +#define DPCS_BASE__INST3_SEG0 0 +#define DPCS_BASE__INST3_SEG1 0 +#define DPCS_BASE__INST3_SEG2 0 +#define DPCS_BASE__INST3_SEG3 0 +#define DPCS_BASE__INST3_SEG4 0 + +#define DPCS_BASE__INST4_SEG0 0 +#define DPCS_BASE__INST4_SEG1 0 +#define DPCS_BASE__INST4_SEG2 0 +#define DPCS_BASE__INST4_SEG3 0 +#define DPCS_BASE__INST4_SEG4 0 + +#define DPCS_BASE__INST5_SEG0 0 +#define DPCS_BASE__INST5_SEG1 0 +#define DPCS_BASE__INST5_SEG2 0 +#define DPCS_BASE__INST5_SEG3 0 +#define DPCS_BASE__INST5_SEG4 0 + +#define DPCS_BASE__INST6_SEG0 0 +#define DPCS_BASE__INST6_SEG1 0 +#define DPCS_BASE__INST6_SEG2 0 +#define DPCS_BASE__INST6_SEG3 0 +#define DPCS_BASE__INST6_SEG4 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0x02401400 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 + +#define GC_BASE__INST0_SEG0 0x00001260 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x02402C00 +#define GC_BASE__INST0_SEG3 0 +#define GC_BASE__INST0_SEG4 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 + +#define HDA_BASE__INST0_SEG0 0x004C0000 +#define HDA_BASE__INST0_SEG1 0x02404800 +#define HDA_BASE__INST0_SEG2 0 +#define HDA_BASE__INST0_SEG3 0 +#define HDA_BASE__INST0_SEG4 0 + +#define HDA_BASE__INST1_SEG0 0 +#define HDA_BASE__INST1_SEG1 0 +#define HDA_BASE__INST1_SEG2 0 +#define HDA_BASE__INST1_SEG3 0 +#define HDA_BASE__INST1_SEG4 0 + +#define HDA_BASE__INST2_SEG0 0 +#define HDA_BASE__INST2_SEG1 0 +#define HDA_BASE__INST2_SEG2 0 +#define HDA_BASE__INST2_SEG3 0 +#define HDA_BASE__INST2_SEG4 0 + +#define HDA_BASE__INST3_SEG0 0 +#define HDA_BASE__INST3_SEG1 0 +#define HDA_BASE__INST3_SEG2 0 +#define HDA_BASE__INST3_SEG3 0 +#define HDA_BASE__INST3_SEG4 0 + +#define HDA_BASE__INST4_SEG0 0 +#define HDA_BASE__INST4_SEG1 0 +#define HDA_BASE__INST4_SEG2 0 +#define HDA_BASE__INST4_SEG3 0 +#define HDA_BASE__INST4_SEG4 0 + +#define HDA_BASE__INST5_SEG0 0 +#define HDA_BASE__INST5_SEG1 0 +#define HDA_BASE__INST5_SEG2 0 +#define HDA_BASE__INST5_SEG3 0 +#define HDA_BASE__INST5_SEG4 0 + +#define HDA_BASE__INST6_SEG0 0 +#define HDA_BASE__INST6_SEG1 0 +#define HDA_BASE__INST6_SEG2 0 +#define HDA_BASE__INST6_SEG3 0 +#define HDA_BASE__INST6_SEG4 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x0240A400 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 + +#define MMHUB_BASE__INST0_SEG0 0x0001A000 +#define MMHUB_BASE__INST0_SEG1 0x02408800 +#define MMHUB_BASE__INST0_SEG2 0 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0x00DC0000 +#define MP0_BASE__INST0_SEG2 0x00E00000 +#define MP0_BASE__INST0_SEG3 0x00E40000 +#define MP0_BASE__INST0_SEG4 0x0243FC00 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 + +#define MP1_BASE__INST0_SEG0 0x00016200 +#define MP1_BASE__INST0_SEG1 0x00E80000 +#define MP1_BASE__INST0_SEG2 0x00EC0000 +#define MP1_BASE__INST0_SEG3 0x00F00000 +#define MP1_BASE__INST0_SEG4 0x02400400 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 + +#define NBIF0_BASE__INST0_SEG0 0x00000000 +#define NBIF0_BASE__INST0_SEG1 0x00000014 +#define NBIF0_BASE__INST0_SEG2 0x00000D20 +#define NBIF0_BASE__INST0_SEG3 0x00010400 +#define NBIF0_BASE__INST0_SEG4 0x0241B000 + +#define NBIF0_BASE__INST1_SEG0 0 +#define NBIF0_BASE__INST1_SEG1 0 +#define NBIF0_BASE__INST1_SEG2 0 +#define NBIF0_BASE__INST1_SEG3 0 +#define NBIF0_BASE__INST1_SEG4 0 + +#define NBIF0_BASE__INST2_SEG0 0 +#define NBIF0_BASE__INST2_SEG1 0 +#define NBIF0_BASE__INST2_SEG2 0 +#define NBIF0_BASE__INST2_SEG3 0 +#define NBIF0_BASE__INST2_SEG4 0 + +#define NBIF0_BASE__INST3_SEG0 0 +#define NBIF0_BASE__INST3_SEG1 0 +#define NBIF0_BASE__INST3_SEG2 0 +#define NBIF0_BASE__INST3_SEG3 0 +#define NBIF0_BASE__INST3_SEG4 0 + +#define NBIF0_BASE__INST4_SEG0 0 +#define NBIF0_BASE__INST4_SEG1 0 +#define NBIF0_BASE__INST4_SEG2 0 +#define NBIF0_BASE__INST4_SEG3 0 +#define NBIF0_BASE__INST4_SEG4 0 + +#define NBIF0_BASE__INST5_SEG0 0 +#define NBIF0_BASE__INST5_SEG1 0 +#define NBIF0_BASE__INST5_SEG2 0 +#define NBIF0_BASE__INST5_SEG3 0 +#define NBIF0_BASE__INST5_SEG4 0 + +#define NBIF0_BASE__INST6_SEG0 0 +#define NBIF0_BASE__INST6_SEG1 0 +#define NBIF0_BASE__INST6_SEG2 0 +#define NBIF0_BASE__INST6_SEG3 0 +#define NBIF0_BASE__INST6_SEG4 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x0240A000 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 + +#define PCIE0_BASE__INST0_SEG0 0x02411800 +#define PCIE0_BASE__INST0_SEG1 0x04440000 +#define PCIE0_BASE__INST0_SEG2 0 +#define PCIE0_BASE__INST0_SEG3 0 +#define PCIE0_BASE__INST0_SEG4 0 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 + +#define SDMA_BASE__INST0_SEG0 0x00001260 +#define SDMA_BASE__INST0_SEG1 0x0000A000 +#define SDMA_BASE__INST0_SEG2 0x02402C00 +#define SDMA_BASE__INST0_SEG3 0 +#define SDMA_BASE__INST0_SEG4 0 + +#define SDMA_BASE__INST1_SEG0 0x00001260 +#define SDMA_BASE__INST1_SEG1 0x0000A000 +#define SDMA_BASE__INST1_SEG2 0x02402C00 +#define SDMA_BASE__INST1_SEG3 0 +#define SDMA_BASE__INST1_SEG4 0 + +#define SDMA_BASE__INST2_SEG0 0 +#define SDMA_BASE__INST2_SEG1 0 +#define SDMA_BASE__INST2_SEG2 0 +#define SDMA_BASE__INST2_SEG3 0 +#define SDMA_BASE__INST2_SEG4 0 + +#define SDMA_BASE__INST3_SEG0 0 +#define SDMA_BASE__INST3_SEG1 0 +#define SDMA_BASE__INST3_SEG2 0 +#define SDMA_BASE__INST3_SEG3 0 +#define SDMA_BASE__INST3_SEG4 0 + +#define SDMA_BASE__INST4_SEG0 0 +#define SDMA_BASE__INST4_SEG1 0 +#define SDMA_BASE__INST4_SEG2 0 +#define SDMA_BASE__INST4_SEG3 0 +#define SDMA_BASE__INST4_SEG4 0 + +#define SDMA_BASE__INST5_SEG0 0 +#define SDMA_BASE__INST5_SEG1 0 +#define SDMA_BASE__INST5_SEG2 0 +#define SDMA_BASE__INST5_SEG3 0 +#define SDMA_BASE__INST5_SEG4 0 + +#define SDMA_BASE__INST6_SEG0 0 +#define SDMA_BASE__INST6_SEG1 0 +#define SDMA_BASE__INST6_SEG2 0 +#define SDMA_BASE__INST6_SEG3 0 +#define SDMA_BASE__INST6_SEG4 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0x00016A00 +#define SMUIO_BASE__INST0_SEG2 0x00440000 +#define SMUIO_BASE__INST0_SEG3 0x02401000 +#define SMUIO_BASE__INST0_SEG4 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0x02400C00 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0x02425800 +#define UMC_BASE__INST0_SEG2 0 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 + +#define UMC_BASE__INST1_SEG0 0x00054000 +#define UMC_BASE__INST1_SEG1 0x02425C00 +#define UMC_BASE__INST1_SEG2 0 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 + +#define UMC_BASE__INST2_SEG0 0x00094000 +#define UMC_BASE__INST2_SEG1 0x02426000 +#define UMC_BASE__INST2_SEG2 0 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 + +#define UMC_BASE__INST3_SEG0 0x000D4000 +#define UMC_BASE__INST3_SEG1 0x02426400 +#define UMC_BASE__INST3_SEG2 0 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 + +#define UMC_BASE__INST5_SEG0 0 +#define UMC_BASE__INST5_SEG1 0 +#define UMC_BASE__INST5_SEG2 0 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 + +#define UMC_BASE__INST6_SEG0 0 +#define UMC_BASE__INST6_SEG1 0 +#define UMC_BASE__INST6_SEG2 0 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 + +#define USB0_BASE__INST0_SEG0 0x0242A800 +#define USB0_BASE__INST0_SEG1 0x05B00000 +#define USB0_BASE__INST0_SEG2 0 +#define USB0_BASE__INST0_SEG3 0 +#define USB0_BASE__INST0_SEG4 0 + +#define USB0_BASE__INST1_SEG0 0 +#define USB0_BASE__INST1_SEG1 0 +#define USB0_BASE__INST1_SEG2 0 +#define USB0_BASE__INST1_SEG3 0 +#define USB0_BASE__INST1_SEG4 0 + +#define USB0_BASE__INST2_SEG0 0 +#define USB0_BASE__INST2_SEG1 0 +#define USB0_BASE__INST2_SEG2 0 +#define USB0_BASE__INST2_SEG3 0 +#define USB0_BASE__INST2_SEG4 0 + +#define USB0_BASE__INST3_SEG0 0 +#define USB0_BASE__INST3_SEG1 0 +#define USB0_BASE__INST3_SEG2 0 +#define USB0_BASE__INST3_SEG3 0 +#define USB0_BASE__INST3_SEG4 0 + +#define USB0_BASE__INST4_SEG0 0 +#define USB0_BASE__INST4_SEG1 0 +#define USB0_BASE__INST4_SEG2 0 +#define USB0_BASE__INST4_SEG3 0 +#define USB0_BASE__INST4_SEG4 0 + +#define USB0_BASE__INST5_SEG0 0 +#define USB0_BASE__INST5_SEG1 0 +#define USB0_BASE__INST5_SEG2 0 +#define USB0_BASE__INST5_SEG3 0 +#define USB0_BASE__INST5_SEG4 0 + +#define USB0_BASE__INST6_SEG0 0 +#define USB0_BASE__INST6_SEG1 0 +#define USB0_BASE__INST6_SEG2 0 +#define USB0_BASE__INST6_SEG3 0 +#define USB0_BASE__INST6_SEG4 0 + +#define UVD0_BASE__INST0_SEG0 0x00007800 +#define UVD0_BASE__INST0_SEG1 0x00007E00 +#define UVD0_BASE__INST0_SEG2 0x02403000 +#define UVD0_BASE__INST0_SEG3 0 +#define UVD0_BASE__INST0_SEG4 0 + +#define UVD0_BASE__INST1_SEG0 0 +#define UVD0_BASE__INST1_SEG1 0 +#define UVD0_BASE__INST1_SEG2 0 +#define UVD0_BASE__INST1_SEG3 0 +#define UVD0_BASE__INST1_SEG4 0 + +#define UVD0_BASE__INST2_SEG0 0 +#define UVD0_BASE__INST2_SEG1 0 +#define UVD0_BASE__INST2_SEG2 0 +#define UVD0_BASE__INST2_SEG3 0 +#define UVD0_BASE__INST2_SEG4 0 + +#define UVD0_BASE__INST3_SEG0 0 +#define UVD0_BASE__INST3_SEG1 0 +#define UVD0_BASE__INST3_SEG2 0 +#define UVD0_BASE__INST3_SEG3 0 +#define UVD0_BASE__INST3_SEG4 0 + +#define UVD0_BASE__INST4_SEG0 0 +#define UVD0_BASE__INST4_SEG1 0 +#define UVD0_BASE__INST4_SEG2 0 +#define UVD0_BASE__INST4_SEG3 0 +#define UVD0_BASE__INST4_SEG4 0 + +#define UVD0_BASE__INST5_SEG0 0 +#define UVD0_BASE__INST5_SEG1 0 +#define UVD0_BASE__INST5_SEG2 0 +#define UVD0_BASE__INST5_SEG3 0 +#define UVD0_BASE__INST5_SEG4 0 + +#define UVD0_BASE__INST6_SEG0 0 +#define UVD0_BASE__INST6_SEG1 0 +#define UVD0_BASE__INST6_SEG2 0 +#define UVD0_BASE__INST6_SEG3 0 +#define UVD0_BASE__INST6_SEG4 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/navi14_ip_offset.h b/drivers/gpu/drm/amd/include/navi14_ip_offset.h new file mode 100644 index 000000000000..ecdd9eabe0dc --- /dev/null +++ b/drivers/gpu/drm/amd/include/navi14_ip_offset.h @@ -0,0 +1,1119 @@ +/* + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _navi14_ip_offset_HEADER +#define _navi14_ip_offset_HEADER + +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 5 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + + +static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, + { { 0x00016E00, 0x02401C00, 0, 0, 0 } }, + { { 0x00017000, 0x02402000, 0, 0, 0 } }, + { { 0x00017200, 0x02402400, 0, 0, 0 } }, + { { 0x0001B000, 0x0242D800, 0, 0, 0 } }, + { { 0x00017E00, 0x0240BC00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, + { { 0x00054000, 0x02425C00, 0, 0, 0 } }, + { { 0x00094000, 0x02426000, 0, 0, 0 } }, + { { 0x000D4000, 0x02426400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; + + +#define ATHUB_BASE__INST0_SEG0 0x00000C00 +#define ATHUB_BASE__INST0_SEG1 0x02408C00 +#define ATHUB_BASE__INST0_SEG2 0 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0x02401800 +#define CLK_BASE__INST0_SEG2 0 +#define CLK_BASE__INST0_SEG3 0 +#define CLK_BASE__INST0_SEG4 0 + +#define CLK_BASE__INST1_SEG0 0x00016E00 +#define CLK_BASE__INST1_SEG1 0x02401C00 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 + +#define CLK_BASE__INST2_SEG0 0x00017000 +#define CLK_BASE__INST2_SEG1 0x02402000 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 + +#define CLK_BASE__INST3_SEG0 0x00017200 +#define CLK_BASE__INST3_SEG1 0x02402400 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 + +#define CLK_BASE__INST4_SEG0 0x0001B000 +#define CLK_BASE__INST4_SEG1 0x0242D800 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 + +#define CLK_BASE__INST5_SEG0 0x00017E00 +#define CLK_BASE__INST5_SEG1 0x0240BC00 +#define CLK_BASE__INST5_SEG2 0 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 + +#define CLK_BASE__INST6_SEG0 0 +#define CLK_BASE__INST6_SEG1 0 +#define CLK_BASE__INST6_SEG2 0 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x0240B800 +#define DF_BASE__INST0_SEG2 0 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 + +#define DIO_BASE__INST0_SEG0 0x02404000 +#define DIO_BASE__INST0_SEG1 0 +#define DIO_BASE__INST0_SEG2 0 +#define DIO_BASE__INST0_SEG3 0 +#define DIO_BASE__INST0_SEG4 0 + +#define DIO_BASE__INST1_SEG0 0 +#define DIO_BASE__INST1_SEG1 0 +#define DIO_BASE__INST1_SEG2 0 +#define DIO_BASE__INST1_SEG3 0 +#define DIO_BASE__INST1_SEG4 0 + +#define DIO_BASE__INST2_SEG0 0 +#define DIO_BASE__INST2_SEG1 0 +#define DIO_BASE__INST2_SEG2 0 +#define DIO_BASE__INST2_SEG3 0 +#define DIO_BASE__INST2_SEG4 0 + +#define DIO_BASE__INST3_SEG0 0 +#define DIO_BASE__INST3_SEG1 0 +#define DIO_BASE__INST3_SEG2 0 +#define DIO_BASE__INST3_SEG3 0 +#define DIO_BASE__INST3_SEG4 0 + +#define DIO_BASE__INST4_SEG0 0 +#define DIO_BASE__INST4_SEG1 0 +#define DIO_BASE__INST4_SEG2 0 +#define DIO_BASE__INST4_SEG3 0 +#define DIO_BASE__INST4_SEG4 0 + +#define DIO_BASE__INST5_SEG0 0 +#define DIO_BASE__INST5_SEG1 0 +#define DIO_BASE__INST5_SEG2 0 +#define DIO_BASE__INST5_SEG3 0 +#define DIO_BASE__INST5_SEG4 0 + +#define DIO_BASE__INST6_SEG0 0 +#define DIO_BASE__INST6_SEG1 0 +#define DIO_BASE__INST6_SEG2 0 +#define DIO_BASE__INST6_SEG3 0 +#define DIO_BASE__INST6_SEG4 0 + +#define DMU_BASE__INST0_SEG0 0x00000012 +#define DMU_BASE__INST0_SEG1 0x000000C0 +#define DMU_BASE__INST0_SEG2 0x000034C0 +#define DMU_BASE__INST0_SEG3 0x00009000 +#define DMU_BASE__INST0_SEG4 0x02403C00 + +#define DMU_BASE__INST1_SEG0 0 +#define DMU_BASE__INST1_SEG1 0 +#define DMU_BASE__INST1_SEG2 0 +#define DMU_BASE__INST1_SEG3 0 +#define DMU_BASE__INST1_SEG4 0 + +#define DMU_BASE__INST2_SEG0 0 +#define DMU_BASE__INST2_SEG1 0 +#define DMU_BASE__INST2_SEG2 0 +#define DMU_BASE__INST2_SEG3 0 +#define DMU_BASE__INST2_SEG4 0 + +#define DMU_BASE__INST3_SEG0 0 +#define DMU_BASE__INST3_SEG1 0 +#define DMU_BASE__INST3_SEG2 0 +#define DMU_BASE__INST3_SEG3 0 +#define DMU_BASE__INST3_SEG4 0 + +#define DMU_BASE__INST4_SEG0 0 +#define DMU_BASE__INST4_SEG1 0 +#define DMU_BASE__INST4_SEG2 0 +#define DMU_BASE__INST4_SEG3 0 +#define DMU_BASE__INST4_SEG4 0 + +#define DMU_BASE__INST5_SEG0 0 +#define DMU_BASE__INST5_SEG1 0 +#define DMU_BASE__INST5_SEG2 0 +#define DMU_BASE__INST5_SEG3 0 +#define DMU_BASE__INST5_SEG4 0 + +#define DMU_BASE__INST6_SEG0 0 +#define DMU_BASE__INST6_SEG1 0 +#define DMU_BASE__INST6_SEG2 0 +#define DMU_BASE__INST6_SEG3 0 +#define DMU_BASE__INST6_SEG4 0 + +#define DPCS_BASE__INST0_SEG0 0x00000012 +#define DPCS_BASE__INST0_SEG1 0x000000C0 +#define DPCS_BASE__INST0_SEG2 0x000034C0 +#define DPCS_BASE__INST0_SEG3 0x00009000 +#define DPCS_BASE__INST0_SEG4 0x02403C00 + +#define DPCS_BASE__INST1_SEG0 0 +#define DPCS_BASE__INST1_SEG1 0 +#define DPCS_BASE__INST1_SEG2 0 +#define DPCS_BASE__INST1_SEG3 0 +#define DPCS_BASE__INST1_SEG4 0 + +#define DPCS_BASE__INST2_SEG0 0 +#define DPCS_BASE__INST2_SEG1 0 +#define DPCS_BASE__INST2_SEG2 0 +#define DPCS_BASE__INST2_SEG3 0 +#define DPCS_BASE__INST2_SEG4 0 + +#define DPCS_BASE__INST3_SEG0 0 +#define DPCS_BASE__INST3_SEG1 0 +#define DPCS_BASE__INST3_SEG2 0 +#define DPCS_BASE__INST3_SEG3 0 +#define DPCS_BASE__INST3_SEG4 0 + +#define DPCS_BASE__INST4_SEG0 0 +#define DPCS_BASE__INST4_SEG1 0 +#define DPCS_BASE__INST4_SEG2 0 +#define DPCS_BASE__INST4_SEG3 0 +#define DPCS_BASE__INST4_SEG4 0 + +#define DPCS_BASE__INST5_SEG0 0 +#define DPCS_BASE__INST5_SEG1 0 +#define DPCS_BASE__INST5_SEG2 0 +#define DPCS_BASE__INST5_SEG3 0 +#define DPCS_BASE__INST5_SEG4 0 + +#define DPCS_BASE__INST6_SEG0 0 +#define DPCS_BASE__INST6_SEG1 0 +#define DPCS_BASE__INST6_SEG2 0 +#define DPCS_BASE__INST6_SEG3 0 +#define DPCS_BASE__INST6_SEG4 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0x02401400 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 + +#define GC_BASE__INST0_SEG0 0x00001260 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x02402C00 +#define GC_BASE__INST0_SEG3 0 +#define GC_BASE__INST0_SEG4 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 + +#define HDA_BASE__INST0_SEG0 0x004C0000 +#define HDA_BASE__INST0_SEG1 0x02404800 +#define HDA_BASE__INST0_SEG2 0 +#define HDA_BASE__INST0_SEG3 0 +#define HDA_BASE__INST0_SEG4 0 + +#define HDA_BASE__INST1_SEG0 0 +#define HDA_BASE__INST1_SEG1 0 +#define HDA_BASE__INST1_SEG2 0 +#define HDA_BASE__INST1_SEG3 0 +#define HDA_BASE__INST1_SEG4 0 + +#define HDA_BASE__INST2_SEG0 0 +#define HDA_BASE__INST2_SEG1 0 +#define HDA_BASE__INST2_SEG2 0 +#define HDA_BASE__INST2_SEG3 0 +#define HDA_BASE__INST2_SEG4 0 + +#define HDA_BASE__INST3_SEG0 0 +#define HDA_BASE__INST3_SEG1 0 +#define HDA_BASE__INST3_SEG2 0 +#define HDA_BASE__INST3_SEG3 0 +#define HDA_BASE__INST3_SEG4 0 + +#define HDA_BASE__INST4_SEG0 0 +#define HDA_BASE__INST4_SEG1 0 +#define HDA_BASE__INST4_SEG2 0 +#define HDA_BASE__INST4_SEG3 0 +#define HDA_BASE__INST4_SEG4 0 + +#define HDA_BASE__INST5_SEG0 0 +#define HDA_BASE__INST5_SEG1 0 +#define HDA_BASE__INST5_SEG2 0 +#define HDA_BASE__INST5_SEG3 0 +#define HDA_BASE__INST5_SEG4 0 + +#define HDA_BASE__INST6_SEG0 0 +#define HDA_BASE__INST6_SEG1 0 +#define HDA_BASE__INST6_SEG2 0 +#define HDA_BASE__INST6_SEG3 0 +#define HDA_BASE__INST6_SEG4 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x0240A400 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 + +#define MMHUB_BASE__INST0_SEG0 0x0001A000 +#define MMHUB_BASE__INST0_SEG1 0x02408800 +#define MMHUB_BASE__INST0_SEG2 0 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0x00DC0000 +#define MP0_BASE__INST0_SEG2 0x00E00000 +#define MP0_BASE__INST0_SEG3 0x00E40000 +#define MP0_BASE__INST0_SEG4 0x0243FC00 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 + +#define MP1_BASE__INST0_SEG0 0x00016000 +#define MP1_BASE__INST0_SEG1 0x00DC0000 +#define MP1_BASE__INST0_SEG2 0x00E00000 +#define MP1_BASE__INST0_SEG3 0x00E40000 +#define MP1_BASE__INST0_SEG4 0x0243FC00 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 + +#define NBIF0_BASE__INST0_SEG0 0x00000000 +#define NBIF0_BASE__INST0_SEG1 0x00000014 +#define NBIF0_BASE__INST0_SEG2 0x00000D20 +#define NBIF0_BASE__INST0_SEG3 0x00010400 +#define NBIF0_BASE__INST0_SEG4 0x0241B000 + +#define NBIF0_BASE__INST1_SEG0 0 +#define NBIF0_BASE__INST1_SEG1 0 +#define NBIF0_BASE__INST1_SEG2 0 +#define NBIF0_BASE__INST1_SEG3 0 +#define NBIF0_BASE__INST1_SEG4 0 + +#define NBIF0_BASE__INST2_SEG0 0 +#define NBIF0_BASE__INST2_SEG1 0 +#define NBIF0_BASE__INST2_SEG2 0 +#define NBIF0_BASE__INST2_SEG3 0 +#define NBIF0_BASE__INST2_SEG4 0 + +#define NBIF0_BASE__INST3_SEG0 0 +#define NBIF0_BASE__INST3_SEG1 0 +#define NBIF0_BASE__INST3_SEG2 0 +#define NBIF0_BASE__INST3_SEG3 0 +#define NBIF0_BASE__INST3_SEG4 0 + +#define NBIF0_BASE__INST4_SEG0 0 +#define NBIF0_BASE__INST4_SEG1 0 +#define NBIF0_BASE__INST4_SEG2 0 +#define NBIF0_BASE__INST4_SEG3 0 +#define NBIF0_BASE__INST4_SEG4 0 + +#define NBIF0_BASE__INST5_SEG0 0 +#define NBIF0_BASE__INST5_SEG1 0 +#define NBIF0_BASE__INST5_SEG2 0 +#define NBIF0_BASE__INST5_SEG3 0 +#define NBIF0_BASE__INST5_SEG4 0 + +#define NBIF0_BASE__INST6_SEG0 0 +#define NBIF0_BASE__INST6_SEG1 0 +#define NBIF0_BASE__INST6_SEG2 0 +#define NBIF0_BASE__INST6_SEG3 0 +#define NBIF0_BASE__INST6_SEG4 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x0240A000 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 + +#define PCIE0_BASE__INST0_SEG0 0x00000000 +#define PCIE0_BASE__INST0_SEG1 0x00000014 +#define PCIE0_BASE__INST0_SEG2 0x00000D20 +#define PCIE0_BASE__INST0_SEG3 0x00010400 +#define PCIE0_BASE__INST0_SEG4 0x0241B000 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 + +#define SDMA_BASE__INST0_SEG0 0x00001260 +#define SDMA_BASE__INST0_SEG1 0x0000A000 +#define SDMA_BASE__INST0_SEG2 0x02402C00 +#define SDMA_BASE__INST0_SEG3 0 +#define SDMA_BASE__INST0_SEG4 0 + +#define SDMA_BASE__INST1_SEG0 0x00001260 +#define SDMA_BASE__INST1_SEG1 0x0000A000 +#define SDMA_BASE__INST1_SEG2 0x02402C00 +#define SDMA_BASE__INST1_SEG3 0 +#define SDMA_BASE__INST1_SEG4 0 + +#define SDMA_BASE__INST2_SEG0 0 +#define SDMA_BASE__INST2_SEG1 0 +#define SDMA_BASE__INST2_SEG2 0 +#define SDMA_BASE__INST2_SEG3 0 +#define SDMA_BASE__INST2_SEG4 0 + +#define SDMA_BASE__INST3_SEG0 0 +#define SDMA_BASE__INST3_SEG1 0 +#define SDMA_BASE__INST3_SEG2 0 +#define SDMA_BASE__INST3_SEG3 0 +#define SDMA_BASE__INST3_SEG4 0 + +#define SDMA_BASE__INST4_SEG0 0 +#define SDMA_BASE__INST4_SEG1 0 +#define SDMA_BASE__INST4_SEG2 0 +#define SDMA_BASE__INST4_SEG3 0 +#define SDMA_BASE__INST4_SEG4 0 + +#define SDMA_BASE__INST5_SEG0 0 +#define SDMA_BASE__INST5_SEG1 0 +#define SDMA_BASE__INST5_SEG2 0 +#define SDMA_BASE__INST5_SEG3 0 +#define SDMA_BASE__INST5_SEG4 0 + +#define SDMA_BASE__INST6_SEG0 0 +#define SDMA_BASE__INST6_SEG1 0 +#define SDMA_BASE__INST6_SEG2 0 +#define SDMA_BASE__INST6_SEG3 0 +#define SDMA_BASE__INST6_SEG4 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0x00016A00 +#define SMUIO_BASE__INST0_SEG2 0x00440000 +#define SMUIO_BASE__INST0_SEG3 0x02401000 +#define SMUIO_BASE__INST0_SEG4 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0x02400C00 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0x02425800 +#define UMC_BASE__INST0_SEG2 0 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 + +#define UMC_BASE__INST1_SEG0 0x00054000 +#define UMC_BASE__INST1_SEG1 0x02425C00 +#define UMC_BASE__INST1_SEG2 0 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 + +#define UMC_BASE__INST2_SEG0 0x00094000 +#define UMC_BASE__INST2_SEG1 0x02426000 +#define UMC_BASE__INST2_SEG2 0 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 + +#define UMC_BASE__INST3_SEG0 0x000D4000 +#define UMC_BASE__INST3_SEG1 0x02426400 +#define UMC_BASE__INST3_SEG2 0 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 + +#define UMC_BASE__INST5_SEG0 0 +#define UMC_BASE__INST5_SEG1 0 +#define UMC_BASE__INST5_SEG2 0 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 + +#define UMC_BASE__INST6_SEG0 0 +#define UMC_BASE__INST6_SEG1 0 +#define UMC_BASE__INST6_SEG2 0 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 + +#define USB0_BASE__INST0_SEG0 0x0242A800 +#define USB0_BASE__INST0_SEG1 0x05B00000 +#define USB0_BASE__INST0_SEG2 0 +#define USB0_BASE__INST0_SEG3 0 +#define USB0_BASE__INST0_SEG4 0 + +#define USB0_BASE__INST1_SEG0 0 +#define USB0_BASE__INST1_SEG1 0 +#define USB0_BASE__INST1_SEG2 0 +#define USB0_BASE__INST1_SEG3 0 +#define USB0_BASE__INST1_SEG4 0 + +#define USB0_BASE__INST2_SEG0 0 +#define USB0_BASE__INST2_SEG1 0 +#define USB0_BASE__INST2_SEG2 0 +#define USB0_BASE__INST2_SEG3 0 +#define USB0_BASE__INST2_SEG4 0 + +#define USB0_BASE__INST3_SEG0 0 +#define USB0_BASE__INST3_SEG1 0 +#define USB0_BASE__INST3_SEG2 0 +#define USB0_BASE__INST3_SEG3 0 +#define USB0_BASE__INST3_SEG4 0 + +#define USB0_BASE__INST4_SEG0 0 +#define USB0_BASE__INST4_SEG1 0 +#define USB0_BASE__INST4_SEG2 0 +#define USB0_BASE__INST4_SEG3 0 +#define USB0_BASE__INST4_SEG4 0 + +#define USB0_BASE__INST5_SEG0 0 +#define USB0_BASE__INST5_SEG1 0 +#define USB0_BASE__INST5_SEG2 0 +#define USB0_BASE__INST5_SEG3 0 +#define USB0_BASE__INST5_SEG4 0 + +#define USB0_BASE__INST6_SEG0 0 +#define USB0_BASE__INST6_SEG1 0 +#define USB0_BASE__INST6_SEG2 0 +#define USB0_BASE__INST6_SEG3 0 +#define USB0_BASE__INST6_SEG4 0 + +#define UVD0_BASE__INST0_SEG0 0x00007800 +#define UVD0_BASE__INST0_SEG1 0x00007E00 +#define UVD0_BASE__INST0_SEG2 0x02403000 +#define UVD0_BASE__INST0_SEG3 0 +#define UVD0_BASE__INST0_SEG4 0 + +#define UVD0_BASE__INST1_SEG0 0 +#define UVD0_BASE__INST1_SEG1 0 +#define UVD0_BASE__INST1_SEG2 0 +#define UVD0_BASE__INST1_SEG3 0 +#define UVD0_BASE__INST1_SEG4 0 + +#define UVD0_BASE__INST2_SEG0 0 +#define UVD0_BASE__INST2_SEG1 0 +#define UVD0_BASE__INST2_SEG2 0 +#define UVD0_BASE__INST2_SEG3 0 +#define UVD0_BASE__INST2_SEG4 0 + +#define UVD0_BASE__INST3_SEG0 0 +#define UVD0_BASE__INST3_SEG1 0 +#define UVD0_BASE__INST3_SEG2 0 +#define UVD0_BASE__INST3_SEG3 0 +#define UVD0_BASE__INST3_SEG4 0 + +#define UVD0_BASE__INST4_SEG0 0 +#define UVD0_BASE__INST4_SEG1 0 +#define UVD0_BASE__INST4_SEG2 0 +#define UVD0_BASE__INST4_SEG3 0 +#define UVD0_BASE__INST4_SEG4 0 + +#define UVD0_BASE__INST5_SEG0 0 +#define UVD0_BASE__INST5_SEG1 0 +#define UVD0_BASE__INST5_SEG2 0 +#define UVD0_BASE__INST5_SEG3 0 +#define UVD0_BASE__INST5_SEG4 0 + +#define UVD0_BASE__INST6_SEG0 0 +#define UVD0_BASE__INST6_SEG1 0 +#define UVD0_BASE__INST6_SEG2 0 +#define UVD0_BASE__INST6_SEG3 0 +#define UVD0_BASE__INST6_SEG4 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h b/drivers/gpu/drm/amd/include/renoir_ip_offset.h new file mode 100644 index 000000000000..554714c8e000 --- /dev/null +++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h @@ -0,0 +1,1364 @@ +/* + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _renoir_ip_offset_HEADER +#define _renoir_ip_offset_HEADER + +#define MAX_INSTANCE 7 +#define MAX_SEGMENT 5 + + +struct IP_BASE_INSTANCE +{ + unsigned int segment[MAX_SEGMENT]; +}; + +struct IP_BASE +{ + struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; +}; + + +static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE MP1_BASE ={ { { { 0x00016200, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } }, + { { 0x00054000, 0x02425C00, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; +static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0 } } } }; + + +#define ACP_BASE__INST0_SEG0 0x02403800 +#define ACP_BASE__INST0_SEG1 0x00480000 +#define ACP_BASE__INST0_SEG2 0 +#define ACP_BASE__INST0_SEG3 0 +#define ACP_BASE__INST0_SEG4 0 + +#define ACP_BASE__INST1_SEG0 0 +#define ACP_BASE__INST1_SEG1 0 +#define ACP_BASE__INST1_SEG2 0 +#define ACP_BASE__INST1_SEG3 0 +#define ACP_BASE__INST1_SEG4 0 + +#define ACP_BASE__INST2_SEG0 0 +#define ACP_BASE__INST2_SEG1 0 +#define ACP_BASE__INST2_SEG2 0 +#define ACP_BASE__INST2_SEG3 0 +#define ACP_BASE__INST2_SEG4 0 + +#define ACP_BASE__INST3_SEG0 0 +#define ACP_BASE__INST3_SEG1 0 +#define ACP_BASE__INST3_SEG2 0 +#define ACP_BASE__INST3_SEG3 0 +#define ACP_BASE__INST3_SEG4 0 + +#define ACP_BASE__INST4_SEG0 0 +#define ACP_BASE__INST4_SEG1 0 +#define ACP_BASE__INST4_SEG2 0 +#define ACP_BASE__INST4_SEG3 0 +#define ACP_BASE__INST4_SEG4 0 + +#define ACP_BASE__INST5_SEG0 0 +#define ACP_BASE__INST5_SEG1 0 +#define ACP_BASE__INST5_SEG2 0 +#define ACP_BASE__INST5_SEG3 0 +#define ACP_BASE__INST5_SEG4 0 + +#define ACP_BASE__INST6_SEG0 0 +#define ACP_BASE__INST6_SEG1 0 +#define ACP_BASE__INST6_SEG2 0 +#define ACP_BASE__INST6_SEG3 0 +#define ACP_BASE__INST6_SEG4 0 + +#define ATHUB_BASE__INST0_SEG0 0x00000C20 +#define ATHUB_BASE__INST0_SEG1 0x02408C00 +#define ATHUB_BASE__INST0_SEG2 0 +#define ATHUB_BASE__INST0_SEG3 0 +#define ATHUB_BASE__INST0_SEG4 0 + +#define ATHUB_BASE__INST1_SEG0 0 +#define ATHUB_BASE__INST1_SEG1 0 +#define ATHUB_BASE__INST1_SEG2 0 +#define ATHUB_BASE__INST1_SEG3 0 +#define ATHUB_BASE__INST1_SEG4 0 + +#define ATHUB_BASE__INST2_SEG0 0 +#define ATHUB_BASE__INST2_SEG1 0 +#define ATHUB_BASE__INST2_SEG2 0 +#define ATHUB_BASE__INST2_SEG3 0 +#define ATHUB_BASE__INST2_SEG4 0 + +#define ATHUB_BASE__INST3_SEG0 0 +#define ATHUB_BASE__INST3_SEG1 0 +#define ATHUB_BASE__INST3_SEG2 0 +#define ATHUB_BASE__INST3_SEG3 0 +#define ATHUB_BASE__INST3_SEG4 0 + +#define ATHUB_BASE__INST4_SEG0 0 +#define ATHUB_BASE__INST4_SEG1 0 +#define ATHUB_BASE__INST4_SEG2 0 +#define ATHUB_BASE__INST4_SEG3 0 +#define ATHUB_BASE__INST4_SEG4 0 + +#define ATHUB_BASE__INST5_SEG0 0 +#define ATHUB_BASE__INST5_SEG1 0 +#define ATHUB_BASE__INST5_SEG2 0 +#define ATHUB_BASE__INST5_SEG3 0 +#define ATHUB_BASE__INST5_SEG4 0 + +#define ATHUB_BASE__INST6_SEG0 0 +#define ATHUB_BASE__INST6_SEG1 0 +#define ATHUB_BASE__INST6_SEG2 0 +#define ATHUB_BASE__INST6_SEG3 0 +#define ATHUB_BASE__INST6_SEG4 0 + +#define CLK_BASE__INST0_SEG0 0x00016C00 +#define CLK_BASE__INST0_SEG1 0x00016E00 +#define CLK_BASE__INST0_SEG2 0x00017000 +#define CLK_BASE__INST0_SEG3 0x00017E00 +#define CLK_BASE__INST0_SEG4 0 + +#define CLK_BASE__INST1_SEG0 0 +#define CLK_BASE__INST1_SEG1 0 +#define CLK_BASE__INST1_SEG2 0 +#define CLK_BASE__INST1_SEG3 0 +#define CLK_BASE__INST1_SEG4 0 + +#define CLK_BASE__INST2_SEG0 0 +#define CLK_BASE__INST2_SEG1 0 +#define CLK_BASE__INST2_SEG2 0 +#define CLK_BASE__INST2_SEG3 0 +#define CLK_BASE__INST2_SEG4 0 + +#define CLK_BASE__INST3_SEG0 0 +#define CLK_BASE__INST3_SEG1 0 +#define CLK_BASE__INST3_SEG2 0 +#define CLK_BASE__INST3_SEG3 0 +#define CLK_BASE__INST3_SEG4 0 + +#define CLK_BASE__INST4_SEG0 0 +#define CLK_BASE__INST4_SEG1 0 +#define CLK_BASE__INST4_SEG2 0 +#define CLK_BASE__INST4_SEG3 0 +#define CLK_BASE__INST4_SEG4 0 + +#define CLK_BASE__INST5_SEG0 0 +#define CLK_BASE__INST5_SEG1 0 +#define CLK_BASE__INST5_SEG2 0 +#define CLK_BASE__INST5_SEG3 0 +#define CLK_BASE__INST5_SEG4 0 + +#define CLK_BASE__INST6_SEG0 0 +#define CLK_BASE__INST6_SEG1 0 +#define CLK_BASE__INST6_SEG2 0 +#define CLK_BASE__INST6_SEG3 0 +#define CLK_BASE__INST6_SEG4 0 + +#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0 +#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400 +#define DBGU_IO0_BASE__INST0_SEG2 0 +#define DBGU_IO0_BASE__INST0_SEG3 0 +#define DBGU_IO0_BASE__INST0_SEG4 0 + +#define DBGU_IO0_BASE__INST1_SEG0 0 +#define DBGU_IO0_BASE__INST1_SEG1 0 +#define DBGU_IO0_BASE__INST1_SEG2 0 +#define DBGU_IO0_BASE__INST1_SEG3 0 +#define DBGU_IO0_BASE__INST1_SEG4 0 + +#define DBGU_IO0_BASE__INST2_SEG0 0 +#define DBGU_IO0_BASE__INST2_SEG1 0 +#define DBGU_IO0_BASE__INST2_SEG2 0 +#define DBGU_IO0_BASE__INST2_SEG3 0 +#define DBGU_IO0_BASE__INST2_SEG4 0 + +#define DBGU_IO0_BASE__INST3_SEG0 0 +#define DBGU_IO0_BASE__INST3_SEG1 0 +#define DBGU_IO0_BASE__INST3_SEG2 0 +#define DBGU_IO0_BASE__INST3_SEG3 0 +#define DBGU_IO0_BASE__INST3_SEG4 0 + +#define DBGU_IO0_BASE__INST4_SEG0 0 +#define DBGU_IO0_BASE__INST4_SEG1 0 +#define DBGU_IO0_BASE__INST4_SEG2 0 +#define DBGU_IO0_BASE__INST4_SEG3 0 +#define DBGU_IO0_BASE__INST4_SEG4 0 + +#define DBGU_IO0_BASE__INST5_SEG0 0 +#define DBGU_IO0_BASE__INST5_SEG1 0 +#define DBGU_IO0_BASE__INST5_SEG2 0 +#define DBGU_IO0_BASE__INST5_SEG3 0 +#define DBGU_IO0_BASE__INST5_SEG4 0 + +#define DBGU_IO0_BASE__INST6_SEG0 0 +#define DBGU_IO0_BASE__INST6_SEG1 0 +#define DBGU_IO0_BASE__INST6_SEG2 0 +#define DBGU_IO0_BASE__INST6_SEG3 0 +#define DBGU_IO0_BASE__INST6_SEG4 0 + +#define DF_BASE__INST0_SEG0 0x00007000 +#define DF_BASE__INST0_SEG1 0x0240B800 +#define DF_BASE__INST0_SEG2 0 +#define DF_BASE__INST0_SEG3 0 +#define DF_BASE__INST0_SEG4 0 + +#define DF_BASE__INST1_SEG0 0 +#define DF_BASE__INST1_SEG1 0 +#define DF_BASE__INST1_SEG2 0 +#define DF_BASE__INST1_SEG3 0 +#define DF_BASE__INST1_SEG4 0 + +#define DF_BASE__INST2_SEG0 0 +#define DF_BASE__INST2_SEG1 0 +#define DF_BASE__INST2_SEG2 0 +#define DF_BASE__INST2_SEG3 0 +#define DF_BASE__INST2_SEG4 0 + +#define DF_BASE__INST3_SEG0 0 +#define DF_BASE__INST3_SEG1 0 +#define DF_BASE__INST3_SEG2 0 +#define DF_BASE__INST3_SEG3 0 +#define DF_BASE__INST3_SEG4 0 + +#define DF_BASE__INST4_SEG0 0 +#define DF_BASE__INST4_SEG1 0 +#define DF_BASE__INST4_SEG2 0 +#define DF_BASE__INST4_SEG3 0 +#define DF_BASE__INST4_SEG4 0 + +#define DF_BASE__INST5_SEG0 0 +#define DF_BASE__INST5_SEG1 0 +#define DF_BASE__INST5_SEG2 0 +#define DF_BASE__INST5_SEG3 0 +#define DF_BASE__INST5_SEG4 0 + +#define DF_BASE__INST6_SEG0 0 +#define DF_BASE__INST6_SEG1 0 +#define DF_BASE__INST6_SEG2 0 +#define DF_BASE__INST6_SEG3 0 +#define DF_BASE__INST6_SEG4 0 + +#define DIO_BASE__INST0_SEG0 0x02404000 +#define DIO_BASE__INST0_SEG1 0 +#define DIO_BASE__INST0_SEG2 0 +#define DIO_BASE__INST0_SEG3 0 +#define DIO_BASE__INST0_SEG4 0 + +#define DIO_BASE__INST1_SEG0 0 +#define DIO_BASE__INST1_SEG1 0 +#define DIO_BASE__INST1_SEG2 0 +#define DIO_BASE__INST1_SEG3 0 +#define DIO_BASE__INST1_SEG4 0 + +#define DIO_BASE__INST2_SEG0 0 +#define DIO_BASE__INST2_SEG1 0 +#define DIO_BASE__INST2_SEG2 0 +#define DIO_BASE__INST2_SEG3 0 +#define DIO_BASE__INST2_SEG4 0 + +#define DIO_BASE__INST3_SEG0 0 +#define DIO_BASE__INST3_SEG1 0 +#define DIO_BASE__INST3_SEG2 0 +#define DIO_BASE__INST3_SEG3 0 +#define DIO_BASE__INST3_SEG4 0 + +#define DIO_BASE__INST4_SEG0 0 +#define DIO_BASE__INST4_SEG1 0 +#define DIO_BASE__INST4_SEG2 0 +#define DIO_BASE__INST4_SEG3 0 +#define DIO_BASE__INST4_SEG4 0 + +#define DIO_BASE__INST5_SEG0 0 +#define DIO_BASE__INST5_SEG1 0 +#define DIO_BASE__INST5_SEG2 0 +#define DIO_BASE__INST5_SEG3 0 +#define DIO_BASE__INST5_SEG4 0 + +#define DIO_BASE__INST6_SEG0 0 +#define DIO_BASE__INST6_SEG1 0 +#define DIO_BASE__INST6_SEG2 0 +#define DIO_BASE__INST6_SEG3 0 +#define DIO_BASE__INST6_SEG4 0 + +#define DMU_BASE__INST0_SEG0 0x00000012 +#define DMU_BASE__INST0_SEG1 0x000000C0 +#define DMU_BASE__INST0_SEG2 0x000034C0 +#define DMU_BASE__INST0_SEG3 0x00009000 +#define DMU_BASE__INST0_SEG4 0x02403C00 + +#define DMU_BASE__INST1_SEG0 0 +#define DMU_BASE__INST1_SEG1 0 +#define DMU_BASE__INST1_SEG2 0 +#define DMU_BASE__INST1_SEG3 0 +#define DMU_BASE__INST1_SEG4 0 + +#define DMU_BASE__INST2_SEG0 0 +#define DMU_BASE__INST2_SEG1 0 +#define DMU_BASE__INST2_SEG2 0 +#define DMU_BASE__INST2_SEG3 0 +#define DMU_BASE__INST2_SEG4 0 + +#define DMU_BASE__INST3_SEG0 0 +#define DMU_BASE__INST3_SEG1 0 +#define DMU_BASE__INST3_SEG2 0 +#define DMU_BASE__INST3_SEG3 0 +#define DMU_BASE__INST3_SEG4 0 + +#define DMU_BASE__INST4_SEG0 0 +#define DMU_BASE__INST4_SEG1 0 +#define DMU_BASE__INST4_SEG2 0 +#define DMU_BASE__INST4_SEG3 0 +#define DMU_BASE__INST4_SEG4 0 + +#define DMU_BASE__INST5_SEG0 0 +#define DMU_BASE__INST5_SEG1 0 +#define DMU_BASE__INST5_SEG2 0 +#define DMU_BASE__INST5_SEG3 0 +#define DMU_BASE__INST5_SEG4 0 + +#define DMU_BASE__INST6_SEG0 0 +#define DMU_BASE__INST6_SEG1 0 +#define DMU_BASE__INST6_SEG2 0 +#define DMU_BASE__INST6_SEG3 0 +#define DMU_BASE__INST6_SEG4 0 + +#define DPCS_BASE__INST0_SEG0 0x00000012 +#define DPCS_BASE__INST0_SEG1 0x000000C0 +#define DPCS_BASE__INST0_SEG2 0x000034C0 +#define DPCS_BASE__INST0_SEG3 0x00009000 +#define DPCS_BASE__INST0_SEG4 0x02403C00 + +#define DPCS_BASE__INST1_SEG0 0 +#define DPCS_BASE__INST1_SEG1 0 +#define DPCS_BASE__INST1_SEG2 0 +#define DPCS_BASE__INST1_SEG3 0 +#define DPCS_BASE__INST1_SEG4 0 + +#define DPCS_BASE__INST2_SEG0 0 +#define DPCS_BASE__INST2_SEG1 0 +#define DPCS_BASE__INST2_SEG2 0 +#define DPCS_BASE__INST2_SEG3 0 +#define DPCS_BASE__INST2_SEG4 0 + +#define DPCS_BASE__INST3_SEG0 0 +#define DPCS_BASE__INST3_SEG1 0 +#define DPCS_BASE__INST3_SEG2 0 +#define DPCS_BASE__INST3_SEG3 0 +#define DPCS_BASE__INST3_SEG4 0 + +#define DPCS_BASE__INST4_SEG0 0 +#define DPCS_BASE__INST4_SEG1 0 +#define DPCS_BASE__INST4_SEG2 0 +#define DPCS_BASE__INST4_SEG3 0 +#define DPCS_BASE__INST4_SEG4 0 + +#define DPCS_BASE__INST5_SEG0 0 +#define DPCS_BASE__INST5_SEG1 0 +#define DPCS_BASE__INST5_SEG2 0 +#define DPCS_BASE__INST5_SEG3 0 +#define DPCS_BASE__INST5_SEG4 0 + +#define DPCS_BASE__INST6_SEG0 0 +#define DPCS_BASE__INST6_SEG1 0 +#define DPCS_BASE__INST6_SEG2 0 +#define DPCS_BASE__INST6_SEG3 0 +#define DPCS_BASE__INST6_SEG4 0 + +#define FUSE_BASE__INST0_SEG0 0x00017400 +#define FUSE_BASE__INST0_SEG1 0x02401400 +#define FUSE_BASE__INST0_SEG2 0 +#define FUSE_BASE__INST0_SEG3 0 +#define FUSE_BASE__INST0_SEG4 0 + +#define FUSE_BASE__INST1_SEG0 0 +#define FUSE_BASE__INST1_SEG1 0 +#define FUSE_BASE__INST1_SEG2 0 +#define FUSE_BASE__INST1_SEG3 0 +#define FUSE_BASE__INST1_SEG4 0 + +#define FUSE_BASE__INST2_SEG0 0 +#define FUSE_BASE__INST2_SEG1 0 +#define FUSE_BASE__INST2_SEG2 0 +#define FUSE_BASE__INST2_SEG3 0 +#define FUSE_BASE__INST2_SEG4 0 + +#define FUSE_BASE__INST3_SEG0 0 +#define FUSE_BASE__INST3_SEG1 0 +#define FUSE_BASE__INST3_SEG2 0 +#define FUSE_BASE__INST3_SEG3 0 +#define FUSE_BASE__INST3_SEG4 0 + +#define FUSE_BASE__INST4_SEG0 0 +#define FUSE_BASE__INST4_SEG1 0 +#define FUSE_BASE__INST4_SEG2 0 +#define FUSE_BASE__INST4_SEG3 0 +#define FUSE_BASE__INST4_SEG4 0 + +#define FUSE_BASE__INST5_SEG0 0 +#define FUSE_BASE__INST5_SEG1 0 +#define FUSE_BASE__INST5_SEG2 0 +#define FUSE_BASE__INST5_SEG3 0 +#define FUSE_BASE__INST5_SEG4 0 + +#define FUSE_BASE__INST6_SEG0 0 +#define FUSE_BASE__INST6_SEG1 0 +#define FUSE_BASE__INST6_SEG2 0 +#define FUSE_BASE__INST6_SEG3 0 +#define FUSE_BASE__INST6_SEG4 0 + +#define GC_BASE__INST0_SEG0 0x00002000 +#define GC_BASE__INST0_SEG1 0x0000A000 +#define GC_BASE__INST0_SEG2 0x02402C00 +#define GC_BASE__INST0_SEG3 0 +#define GC_BASE__INST0_SEG4 0 + +#define GC_BASE__INST1_SEG0 0 +#define GC_BASE__INST1_SEG1 0 +#define GC_BASE__INST1_SEG2 0 +#define GC_BASE__INST1_SEG3 0 +#define GC_BASE__INST1_SEG4 0 + +#define GC_BASE__INST2_SEG0 0 +#define GC_BASE__INST2_SEG1 0 +#define GC_BASE__INST2_SEG2 0 +#define GC_BASE__INST2_SEG3 0 +#define GC_BASE__INST2_SEG4 0 + +#define GC_BASE__INST3_SEG0 0 +#define GC_BASE__INST3_SEG1 0 +#define GC_BASE__INST3_SEG2 0 +#define GC_BASE__INST3_SEG3 0 +#define GC_BASE__INST3_SEG4 0 + +#define GC_BASE__INST4_SEG0 0 +#define GC_BASE__INST4_SEG1 0 +#define GC_BASE__INST4_SEG2 0 +#define GC_BASE__INST4_SEG3 0 +#define GC_BASE__INST4_SEG4 0 + +#define GC_BASE__INST5_SEG0 0 +#define GC_BASE__INST5_SEG1 0 +#define GC_BASE__INST5_SEG2 0 +#define GC_BASE__INST5_SEG3 0 +#define GC_BASE__INST5_SEG4 0 + +#define GC_BASE__INST6_SEG0 0 +#define GC_BASE__INST6_SEG1 0 +#define GC_BASE__INST6_SEG2 0 +#define GC_BASE__INST6_SEG3 0 +#define GC_BASE__INST6_SEG4 0 + +#define HDA_BASE__INST0_SEG0 0x02404800 +#define HDA_BASE__INST0_SEG1 0x004C0000 +#define HDA_BASE__INST0_SEG2 0 +#define HDA_BASE__INST0_SEG3 0 +#define HDA_BASE__INST0_SEG4 0 + +#define HDA_BASE__INST1_SEG0 0 +#define HDA_BASE__INST1_SEG1 0 +#define HDA_BASE__INST1_SEG2 0 +#define HDA_BASE__INST1_SEG3 0 +#define HDA_BASE__INST1_SEG4 0 + +#define HDA_BASE__INST2_SEG0 0 +#define HDA_BASE__INST2_SEG1 0 +#define HDA_BASE__INST2_SEG2 0 +#define HDA_BASE__INST2_SEG3 0 +#define HDA_BASE__INST2_SEG4 0 + +#define HDA_BASE__INST3_SEG0 0 +#define HDA_BASE__INST3_SEG1 0 +#define HDA_BASE__INST3_SEG2 0 +#define HDA_BASE__INST3_SEG3 0 +#define HDA_BASE__INST3_SEG4 0 + +#define HDA_BASE__INST4_SEG0 0 +#define HDA_BASE__INST4_SEG1 0 +#define HDA_BASE__INST4_SEG2 0 +#define HDA_BASE__INST4_SEG3 0 +#define HDA_BASE__INST4_SEG4 0 + +#define HDA_BASE__INST5_SEG0 0 +#define HDA_BASE__INST5_SEG1 0 +#define HDA_BASE__INST5_SEG2 0 +#define HDA_BASE__INST5_SEG3 0 +#define HDA_BASE__INST5_SEG4 0 + +#define HDA_BASE__INST6_SEG0 0 +#define HDA_BASE__INST6_SEG1 0 +#define HDA_BASE__INST6_SEG2 0 +#define HDA_BASE__INST6_SEG3 0 +#define HDA_BASE__INST6_SEG4 0 + +#define HDP_BASE__INST0_SEG0 0x00000F20 +#define HDP_BASE__INST0_SEG1 0x0240A400 +#define HDP_BASE__INST0_SEG2 0 +#define HDP_BASE__INST0_SEG3 0 +#define HDP_BASE__INST0_SEG4 0 + +#define HDP_BASE__INST1_SEG0 0 +#define HDP_BASE__INST1_SEG1 0 +#define HDP_BASE__INST1_SEG2 0 +#define HDP_BASE__INST1_SEG3 0 +#define HDP_BASE__INST1_SEG4 0 + +#define HDP_BASE__INST2_SEG0 0 +#define HDP_BASE__INST2_SEG1 0 +#define HDP_BASE__INST2_SEG2 0 +#define HDP_BASE__INST2_SEG3 0 +#define HDP_BASE__INST2_SEG4 0 + +#define HDP_BASE__INST3_SEG0 0 +#define HDP_BASE__INST3_SEG1 0 +#define HDP_BASE__INST3_SEG2 0 +#define HDP_BASE__INST3_SEG3 0 +#define HDP_BASE__INST3_SEG4 0 + +#define HDP_BASE__INST4_SEG0 0 +#define HDP_BASE__INST4_SEG1 0 +#define HDP_BASE__INST4_SEG2 0 +#define HDP_BASE__INST4_SEG3 0 +#define HDP_BASE__INST4_SEG4 0 + +#define HDP_BASE__INST5_SEG0 0 +#define HDP_BASE__INST5_SEG1 0 +#define HDP_BASE__INST5_SEG2 0 +#define HDP_BASE__INST5_SEG3 0 +#define HDP_BASE__INST5_SEG4 0 + +#define HDP_BASE__INST6_SEG0 0 +#define HDP_BASE__INST6_SEG1 0 +#define HDP_BASE__INST6_SEG2 0 +#define HDP_BASE__INST6_SEG3 0 +#define HDP_BASE__INST6_SEG4 0 + +#define IOHC0_BASE__INST0_SEG0 0x00010000 +#define IOHC0_BASE__INST0_SEG1 0x02406000 +#define IOHC0_BASE__INST0_SEG2 0x04EC0000 +#define IOHC0_BASE__INST0_SEG3 0 +#define IOHC0_BASE__INST0_SEG4 0 + +#define IOHC0_BASE__INST1_SEG0 0 +#define IOHC0_BASE__INST1_SEG1 0 +#define IOHC0_BASE__INST1_SEG2 0 +#define IOHC0_BASE__INST1_SEG3 0 +#define IOHC0_BASE__INST1_SEG4 0 + +#define IOHC0_BASE__INST2_SEG0 0 +#define IOHC0_BASE__INST2_SEG1 0 +#define IOHC0_BASE__INST2_SEG2 0 +#define IOHC0_BASE__INST2_SEG3 0 +#define IOHC0_BASE__INST2_SEG4 0 + +#define IOHC0_BASE__INST3_SEG0 0 +#define IOHC0_BASE__INST3_SEG1 0 +#define IOHC0_BASE__INST3_SEG2 0 +#define IOHC0_BASE__INST3_SEG3 0 +#define IOHC0_BASE__INST3_SEG4 0 + +#define IOHC0_BASE__INST4_SEG0 0 +#define IOHC0_BASE__INST4_SEG1 0 +#define IOHC0_BASE__INST4_SEG2 0 +#define IOHC0_BASE__INST4_SEG3 0 +#define IOHC0_BASE__INST4_SEG4 0 + +#define IOHC0_BASE__INST5_SEG0 0 +#define IOHC0_BASE__INST5_SEG1 0 +#define IOHC0_BASE__INST5_SEG2 0 +#define IOHC0_BASE__INST5_SEG3 0 +#define IOHC0_BASE__INST5_SEG4 0 + +#define IOHC0_BASE__INST6_SEG0 0 +#define IOHC0_BASE__INST6_SEG1 0 +#define IOHC0_BASE__INST6_SEG2 0 +#define IOHC0_BASE__INST6_SEG3 0 +#define IOHC0_BASE__INST6_SEG4 0 + +#define ISP_BASE__INST0_SEG0 0x00018000 +#define ISP_BASE__INST0_SEG1 0x0240B000 +#define ISP_BASE__INST0_SEG2 0 +#define ISP_BASE__INST0_SEG3 0 +#define ISP_BASE__INST0_SEG4 0 + +#define ISP_BASE__INST1_SEG0 0 +#define ISP_BASE__INST1_SEG1 0 +#define ISP_BASE__INST1_SEG2 0 +#define ISP_BASE__INST1_SEG3 0 +#define ISP_BASE__INST1_SEG4 0 + +#define ISP_BASE__INST2_SEG0 0 +#define ISP_BASE__INST2_SEG1 0 +#define ISP_BASE__INST2_SEG2 0 +#define ISP_BASE__INST2_SEG3 0 +#define ISP_BASE__INST2_SEG4 0 + +#define ISP_BASE__INST3_SEG0 0 +#define ISP_BASE__INST3_SEG1 0 +#define ISP_BASE__INST3_SEG2 0 +#define ISP_BASE__INST3_SEG3 0 +#define ISP_BASE__INST3_SEG4 0 + +#define ISP_BASE__INST4_SEG0 0 +#define ISP_BASE__INST4_SEG1 0 +#define ISP_BASE__INST4_SEG2 0 +#define ISP_BASE__INST4_SEG3 0 +#define ISP_BASE__INST4_SEG4 0 + +#define ISP_BASE__INST5_SEG0 0 +#define ISP_BASE__INST5_SEG1 0 +#define ISP_BASE__INST5_SEG2 0 +#define ISP_BASE__INST5_SEG3 0 +#define ISP_BASE__INST5_SEG4 0 + +#define ISP_BASE__INST6_SEG0 0 +#define ISP_BASE__INST6_SEG1 0 +#define ISP_BASE__INST6_SEG2 0 +#define ISP_BASE__INST6_SEG3 0 +#define ISP_BASE__INST6_SEG4 0 + +#define L2IMU0_BASE__INST0_SEG0 0x00007DC0 +#define L2IMU0_BASE__INST0_SEG1 0x02407000 +#define L2IMU0_BASE__INST0_SEG2 0x00900000 +#define L2IMU0_BASE__INST0_SEG3 0x04FC0000 +#define L2IMU0_BASE__INST0_SEG4 0x055C0000 + +#define L2IMU0_BASE__INST1_SEG0 0 +#define L2IMU0_BASE__INST1_SEG1 0 +#define L2IMU0_BASE__INST1_SEG2 0 +#define L2IMU0_BASE__INST1_SEG3 0 +#define L2IMU0_BASE__INST1_SEG4 0 + +#define L2IMU0_BASE__INST2_SEG0 0 +#define L2IMU0_BASE__INST2_SEG1 0 +#define L2IMU0_BASE__INST2_SEG2 0 +#define L2IMU0_BASE__INST2_SEG3 0 +#define L2IMU0_BASE__INST2_SEG4 0 + +#define L2IMU0_BASE__INST3_SEG0 0 +#define L2IMU0_BASE__INST3_SEG1 0 +#define L2IMU0_BASE__INST3_SEG2 0 +#define L2IMU0_BASE__INST3_SEG3 0 +#define L2IMU0_BASE__INST3_SEG4 0 + +#define L2IMU0_BASE__INST4_SEG0 0 +#define L2IMU0_BASE__INST4_SEG1 0 +#define L2IMU0_BASE__INST4_SEG2 0 +#define L2IMU0_BASE__INST4_SEG3 0 +#define L2IMU0_BASE__INST4_SEG4 0 + +#define L2IMU0_BASE__INST5_SEG0 0 +#define L2IMU0_BASE__INST5_SEG1 0 +#define L2IMU0_BASE__INST5_SEG2 0 +#define L2IMU0_BASE__INST5_SEG3 0 +#define L2IMU0_BASE__INST5_SEG4 0 + +#define L2IMU0_BASE__INST6_SEG0 0 +#define L2IMU0_BASE__INST6_SEG1 0 +#define L2IMU0_BASE__INST6_SEG2 0 +#define L2IMU0_BASE__INST6_SEG3 0 +#define L2IMU0_BASE__INST6_SEG4 0 + +#define MMHUB_BASE__INST0_SEG0 0x0001A000 +#define MMHUB_BASE__INST0_SEG1 0x02408800 +#define MMHUB_BASE__INST0_SEG2 0 +#define MMHUB_BASE__INST0_SEG3 0 +#define MMHUB_BASE__INST0_SEG4 0 + +#define MMHUB_BASE__INST1_SEG0 0 +#define MMHUB_BASE__INST1_SEG1 0 +#define MMHUB_BASE__INST1_SEG2 0 +#define MMHUB_BASE__INST1_SEG3 0 +#define MMHUB_BASE__INST1_SEG4 0 + +#define MMHUB_BASE__INST2_SEG0 0 +#define MMHUB_BASE__INST2_SEG1 0 +#define MMHUB_BASE__INST2_SEG2 0 +#define MMHUB_BASE__INST2_SEG3 0 +#define MMHUB_BASE__INST2_SEG4 0 + +#define MMHUB_BASE__INST3_SEG0 0 +#define MMHUB_BASE__INST3_SEG1 0 +#define MMHUB_BASE__INST3_SEG2 0 +#define MMHUB_BASE__INST3_SEG3 0 +#define MMHUB_BASE__INST3_SEG4 0 + +#define MMHUB_BASE__INST4_SEG0 0 +#define MMHUB_BASE__INST4_SEG1 0 +#define MMHUB_BASE__INST4_SEG2 0 +#define MMHUB_BASE__INST4_SEG3 0 +#define MMHUB_BASE__INST4_SEG4 0 + +#define MMHUB_BASE__INST5_SEG0 0 +#define MMHUB_BASE__INST5_SEG1 0 +#define MMHUB_BASE__INST5_SEG2 0 +#define MMHUB_BASE__INST5_SEG3 0 +#define MMHUB_BASE__INST5_SEG4 0 + +#define MMHUB_BASE__INST6_SEG0 0 +#define MMHUB_BASE__INST6_SEG1 0 +#define MMHUB_BASE__INST6_SEG2 0 +#define MMHUB_BASE__INST6_SEG3 0 +#define MMHUB_BASE__INST6_SEG4 0 + +#define MP0_BASE__INST0_SEG0 0x00016000 +#define MP0_BASE__INST0_SEG1 0x0243FC00 +#define MP0_BASE__INST0_SEG2 0x00DC0000 +#define MP0_BASE__INST0_SEG3 0x00E00000 +#define MP0_BASE__INST0_SEG4 0x00E40000 + +#define MP0_BASE__INST1_SEG0 0 +#define MP0_BASE__INST1_SEG1 0 +#define MP0_BASE__INST1_SEG2 0 +#define MP0_BASE__INST1_SEG3 0 +#define MP0_BASE__INST1_SEG4 0 + +#define MP0_BASE__INST2_SEG0 0 +#define MP0_BASE__INST2_SEG1 0 +#define MP0_BASE__INST2_SEG2 0 +#define MP0_BASE__INST2_SEG3 0 +#define MP0_BASE__INST2_SEG4 0 + +#define MP0_BASE__INST3_SEG0 0 +#define MP0_BASE__INST3_SEG1 0 +#define MP0_BASE__INST3_SEG2 0 +#define MP0_BASE__INST3_SEG3 0 +#define MP0_BASE__INST3_SEG4 0 + +#define MP0_BASE__INST4_SEG0 0 +#define MP0_BASE__INST4_SEG1 0 +#define MP0_BASE__INST4_SEG2 0 +#define MP0_BASE__INST4_SEG3 0 +#define MP0_BASE__INST4_SEG4 0 + +#define MP0_BASE__INST5_SEG0 0 +#define MP0_BASE__INST5_SEG1 0 +#define MP0_BASE__INST5_SEG2 0 +#define MP0_BASE__INST5_SEG3 0 +#define MP0_BASE__INST5_SEG4 0 + +#define MP0_BASE__INST6_SEG0 0 +#define MP0_BASE__INST6_SEG1 0 +#define MP0_BASE__INST6_SEG2 0 +#define MP0_BASE__INST6_SEG3 0 +#define MP0_BASE__INST6_SEG4 0 + +#define MP1_BASE__INST0_SEG0 0x00016200 +#define MP1_BASE__INST0_SEG1 0x02400400 +#define MP1_BASE__INST0_SEG2 0x00E80000 +#define MP1_BASE__INST0_SEG3 0x00EC0000 +#define MP1_BASE__INST0_SEG4 0x00F00000 + +#define MP1_BASE__INST1_SEG0 0 +#define MP1_BASE__INST1_SEG1 0 +#define MP1_BASE__INST1_SEG2 0 +#define MP1_BASE__INST1_SEG3 0 +#define MP1_BASE__INST1_SEG4 0 + +#define MP1_BASE__INST2_SEG0 0 +#define MP1_BASE__INST2_SEG1 0 +#define MP1_BASE__INST2_SEG2 0 +#define MP1_BASE__INST2_SEG3 0 +#define MP1_BASE__INST2_SEG4 0 + +#define MP1_BASE__INST3_SEG0 0 +#define MP1_BASE__INST3_SEG1 0 +#define MP1_BASE__INST3_SEG2 0 +#define MP1_BASE__INST3_SEG3 0 +#define MP1_BASE__INST3_SEG4 0 + +#define MP1_BASE__INST4_SEG0 0 +#define MP1_BASE__INST4_SEG1 0 +#define MP1_BASE__INST4_SEG2 0 +#define MP1_BASE__INST4_SEG3 0 +#define MP1_BASE__INST4_SEG4 0 + +#define MP1_BASE__INST5_SEG0 0 +#define MP1_BASE__INST5_SEG1 0 +#define MP1_BASE__INST5_SEG2 0 +#define MP1_BASE__INST5_SEG3 0 +#define MP1_BASE__INST5_SEG4 0 + +#define MP1_BASE__INST6_SEG0 0 +#define MP1_BASE__INST6_SEG1 0 +#define MP1_BASE__INST6_SEG2 0 +#define MP1_BASE__INST6_SEG3 0 +#define MP1_BASE__INST6_SEG4 0 + +#define NBIF0_BASE__INST0_SEG0 0x00000000 +#define NBIF0_BASE__INST0_SEG1 0x00000014 +#define NBIF0_BASE__INST0_SEG2 0x00000D20 +#define NBIF0_BASE__INST0_SEG3 0x00010400 +#define NBIF0_BASE__INST0_SEG4 0x0241B000 + +#define NBIF0_BASE__INST1_SEG0 0 +#define NBIF0_BASE__INST1_SEG1 0 +#define NBIF0_BASE__INST1_SEG2 0 +#define NBIF0_BASE__INST1_SEG3 0 +#define NBIF0_BASE__INST1_SEG4 0 + +#define NBIF0_BASE__INST2_SEG0 0 +#define NBIF0_BASE__INST2_SEG1 0 +#define NBIF0_BASE__INST2_SEG2 0 +#define NBIF0_BASE__INST2_SEG3 0 +#define NBIF0_BASE__INST2_SEG4 0 + +#define NBIF0_BASE__INST3_SEG0 0 +#define NBIF0_BASE__INST3_SEG1 0 +#define NBIF0_BASE__INST3_SEG2 0 +#define NBIF0_BASE__INST3_SEG3 0 +#define NBIF0_BASE__INST3_SEG4 0 + +#define NBIF0_BASE__INST4_SEG0 0 +#define NBIF0_BASE__INST4_SEG1 0 +#define NBIF0_BASE__INST4_SEG2 0 +#define NBIF0_BASE__INST4_SEG3 0 +#define NBIF0_BASE__INST4_SEG4 0 + +#define NBIF0_BASE__INST5_SEG0 0 +#define NBIF0_BASE__INST5_SEG1 0 +#define NBIF0_BASE__INST5_SEG2 0 +#define NBIF0_BASE__INST5_SEG3 0 +#define NBIF0_BASE__INST5_SEG4 0 + +#define NBIF0_BASE__INST6_SEG0 0 +#define NBIF0_BASE__INST6_SEG1 0 +#define NBIF0_BASE__INST6_SEG2 0 +#define NBIF0_BASE__INST6_SEG3 0 +#define NBIF0_BASE__INST6_SEG4 0 + +#define OSSSYS_BASE__INST0_SEG0 0x000010A0 +#define OSSSYS_BASE__INST0_SEG1 0x0240A000 +#define OSSSYS_BASE__INST0_SEG2 0 +#define OSSSYS_BASE__INST0_SEG3 0 +#define OSSSYS_BASE__INST0_SEG4 0 + +#define OSSSYS_BASE__INST1_SEG0 0 +#define OSSSYS_BASE__INST1_SEG1 0 +#define OSSSYS_BASE__INST1_SEG2 0 +#define OSSSYS_BASE__INST1_SEG3 0 +#define OSSSYS_BASE__INST1_SEG4 0 + +#define OSSSYS_BASE__INST2_SEG0 0 +#define OSSSYS_BASE__INST2_SEG1 0 +#define OSSSYS_BASE__INST2_SEG2 0 +#define OSSSYS_BASE__INST2_SEG3 0 +#define OSSSYS_BASE__INST2_SEG4 0 + +#define OSSSYS_BASE__INST3_SEG0 0 +#define OSSSYS_BASE__INST3_SEG1 0 +#define OSSSYS_BASE__INST3_SEG2 0 +#define OSSSYS_BASE__INST3_SEG3 0 +#define OSSSYS_BASE__INST3_SEG4 0 + +#define OSSSYS_BASE__INST4_SEG0 0 +#define OSSSYS_BASE__INST4_SEG1 0 +#define OSSSYS_BASE__INST4_SEG2 0 +#define OSSSYS_BASE__INST4_SEG3 0 +#define OSSSYS_BASE__INST4_SEG4 0 + +#define OSSSYS_BASE__INST5_SEG0 0 +#define OSSSYS_BASE__INST5_SEG1 0 +#define OSSSYS_BASE__INST5_SEG2 0 +#define OSSSYS_BASE__INST5_SEG3 0 +#define OSSSYS_BASE__INST5_SEG4 0 + +#define OSSSYS_BASE__INST6_SEG0 0 +#define OSSSYS_BASE__INST6_SEG1 0 +#define OSSSYS_BASE__INST6_SEG2 0 +#define OSSSYS_BASE__INST6_SEG3 0 +#define OSSSYS_BASE__INST6_SEG4 0 + +#define PCIE0_BASE__INST0_SEG0 0x02411800 +#define PCIE0_BASE__INST0_SEG1 0x04440000 +#define PCIE0_BASE__INST0_SEG2 0 +#define PCIE0_BASE__INST0_SEG3 0 +#define PCIE0_BASE__INST0_SEG4 0 + +#define PCIE0_BASE__INST1_SEG0 0 +#define PCIE0_BASE__INST1_SEG1 0 +#define PCIE0_BASE__INST1_SEG2 0 +#define PCIE0_BASE__INST1_SEG3 0 +#define PCIE0_BASE__INST1_SEG4 0 + +#define PCIE0_BASE__INST2_SEG0 0 +#define PCIE0_BASE__INST2_SEG1 0 +#define PCIE0_BASE__INST2_SEG2 0 +#define PCIE0_BASE__INST2_SEG3 0 +#define PCIE0_BASE__INST2_SEG4 0 + +#define PCIE0_BASE__INST3_SEG0 0 +#define PCIE0_BASE__INST3_SEG1 0 +#define PCIE0_BASE__INST3_SEG2 0 +#define PCIE0_BASE__INST3_SEG3 0 +#define PCIE0_BASE__INST3_SEG4 0 + +#define PCIE0_BASE__INST4_SEG0 0 +#define PCIE0_BASE__INST4_SEG1 0 +#define PCIE0_BASE__INST4_SEG2 0 +#define PCIE0_BASE__INST4_SEG3 0 +#define PCIE0_BASE__INST4_SEG4 0 + +#define PCIE0_BASE__INST5_SEG0 0 +#define PCIE0_BASE__INST5_SEG1 0 +#define PCIE0_BASE__INST5_SEG2 0 +#define PCIE0_BASE__INST5_SEG3 0 +#define PCIE0_BASE__INST5_SEG4 0 + +#define PCIE0_BASE__INST6_SEG0 0 +#define PCIE0_BASE__INST6_SEG1 0 +#define PCIE0_BASE__INST6_SEG2 0 +#define PCIE0_BASE__INST6_SEG3 0 +#define PCIE0_BASE__INST6_SEG4 0 + +#define SDMA0_BASE__INST0_SEG0 0x00001260 +#define SDMA0_BASE__INST0_SEG1 0x0240A800 +#define SDMA0_BASE__INST0_SEG2 0 +#define SDMA0_BASE__INST0_SEG3 0 +#define SDMA0_BASE__INST0_SEG4 0 + +#define SDMA0_BASE__INST1_SEG0 0 +#define SDMA0_BASE__INST1_SEG1 0 +#define SDMA0_BASE__INST1_SEG2 0 +#define SDMA0_BASE__INST1_SEG3 0 +#define SDMA0_BASE__INST1_SEG4 0 + +#define SDMA0_BASE__INST2_SEG0 0 +#define SDMA0_BASE__INST2_SEG1 0 +#define SDMA0_BASE__INST2_SEG2 0 +#define SDMA0_BASE__INST2_SEG3 0 +#define SDMA0_BASE__INST2_SEG4 0 + +#define SDMA0_BASE__INST3_SEG0 0 +#define SDMA0_BASE__INST3_SEG1 0 +#define SDMA0_BASE__INST3_SEG2 0 +#define SDMA0_BASE__INST3_SEG3 0 +#define SDMA0_BASE__INST3_SEG4 0 + +#define SDMA0_BASE__INST4_SEG0 0 +#define SDMA0_BASE__INST4_SEG1 0 +#define SDMA0_BASE__INST4_SEG2 0 +#define SDMA0_BASE__INST4_SEG3 0 +#define SDMA0_BASE__INST4_SEG4 0 + +#define SDMA0_BASE__INST5_SEG0 0 +#define SDMA0_BASE__INST5_SEG1 0 +#define SDMA0_BASE__INST5_SEG2 0 +#define SDMA0_BASE__INST5_SEG3 0 +#define SDMA0_BASE__INST5_SEG4 0 + +#define SDMA0_BASE__INST6_SEG0 0 +#define SDMA0_BASE__INST6_SEG1 0 +#define SDMA0_BASE__INST6_SEG2 0 +#define SDMA0_BASE__INST6_SEG3 0 +#define SDMA0_BASE__INST6_SEG4 0 + +#define SMUIO_BASE__INST0_SEG0 0x00016800 +#define SMUIO_BASE__INST0_SEG1 0x00016A00 +#define SMUIO_BASE__INST0_SEG2 0x02401000 +#define SMUIO_BASE__INST0_SEG3 0x00440000 +#define SMUIO_BASE__INST0_SEG4 0 + +#define SMUIO_BASE__INST1_SEG0 0 +#define SMUIO_BASE__INST1_SEG1 0 +#define SMUIO_BASE__INST1_SEG2 0 +#define SMUIO_BASE__INST1_SEG3 0 +#define SMUIO_BASE__INST1_SEG4 0 + +#define SMUIO_BASE__INST2_SEG0 0 +#define SMUIO_BASE__INST2_SEG1 0 +#define SMUIO_BASE__INST2_SEG2 0 +#define SMUIO_BASE__INST2_SEG3 0 +#define SMUIO_BASE__INST2_SEG4 0 + +#define SMUIO_BASE__INST3_SEG0 0 +#define SMUIO_BASE__INST3_SEG1 0 +#define SMUIO_BASE__INST3_SEG2 0 +#define SMUIO_BASE__INST3_SEG3 0 +#define SMUIO_BASE__INST3_SEG4 0 + +#define SMUIO_BASE__INST4_SEG0 0 +#define SMUIO_BASE__INST4_SEG1 0 +#define SMUIO_BASE__INST4_SEG2 0 +#define SMUIO_BASE__INST4_SEG3 0 +#define SMUIO_BASE__INST4_SEG4 0 + +#define SMUIO_BASE__INST5_SEG0 0 +#define SMUIO_BASE__INST5_SEG1 0 +#define SMUIO_BASE__INST5_SEG2 0 +#define SMUIO_BASE__INST5_SEG3 0 +#define SMUIO_BASE__INST5_SEG4 0 + +#define SMUIO_BASE__INST6_SEG0 0 +#define SMUIO_BASE__INST6_SEG1 0 +#define SMUIO_BASE__INST6_SEG2 0 +#define SMUIO_BASE__INST6_SEG3 0 +#define SMUIO_BASE__INST6_SEG4 0 + +#define THM_BASE__INST0_SEG0 0x00016600 +#define THM_BASE__INST0_SEG1 0x02400C00 +#define THM_BASE__INST0_SEG2 0 +#define THM_BASE__INST0_SEG3 0 +#define THM_BASE__INST0_SEG4 0 + +#define THM_BASE__INST1_SEG0 0 +#define THM_BASE__INST1_SEG1 0 +#define THM_BASE__INST1_SEG2 0 +#define THM_BASE__INST1_SEG3 0 +#define THM_BASE__INST1_SEG4 0 + +#define THM_BASE__INST2_SEG0 0 +#define THM_BASE__INST2_SEG1 0 +#define THM_BASE__INST2_SEG2 0 +#define THM_BASE__INST2_SEG3 0 +#define THM_BASE__INST2_SEG4 0 + +#define THM_BASE__INST3_SEG0 0 +#define THM_BASE__INST3_SEG1 0 +#define THM_BASE__INST3_SEG2 0 +#define THM_BASE__INST3_SEG3 0 +#define THM_BASE__INST3_SEG4 0 + +#define THM_BASE__INST4_SEG0 0 +#define THM_BASE__INST4_SEG1 0 +#define THM_BASE__INST4_SEG2 0 +#define THM_BASE__INST4_SEG3 0 +#define THM_BASE__INST4_SEG4 0 + +#define THM_BASE__INST5_SEG0 0 +#define THM_BASE__INST5_SEG1 0 +#define THM_BASE__INST5_SEG2 0 +#define THM_BASE__INST5_SEG3 0 +#define THM_BASE__INST5_SEG4 0 + +#define THM_BASE__INST6_SEG0 0 +#define THM_BASE__INST6_SEG1 0 +#define THM_BASE__INST6_SEG2 0 +#define THM_BASE__INST6_SEG3 0 +#define THM_BASE__INST6_SEG4 0 + +#define UMC_BASE__INST0_SEG0 0x00014000 +#define UMC_BASE__INST0_SEG1 0x02425800 +#define UMC_BASE__INST0_SEG2 0 +#define UMC_BASE__INST0_SEG3 0 +#define UMC_BASE__INST0_SEG4 0 + +#define UMC_BASE__INST1_SEG0 0x00054000 +#define UMC_BASE__INST1_SEG1 0x02425C00 +#define UMC_BASE__INST1_SEG2 0 +#define UMC_BASE__INST1_SEG3 0 +#define UMC_BASE__INST1_SEG4 0 + +#define UMC_BASE__INST2_SEG0 0 +#define UMC_BASE__INST2_SEG1 0 +#define UMC_BASE__INST2_SEG2 0 +#define UMC_BASE__INST2_SEG3 0 +#define UMC_BASE__INST2_SEG4 0 + +#define UMC_BASE__INST3_SEG0 0 +#define UMC_BASE__INST3_SEG1 0 +#define UMC_BASE__INST3_SEG2 0 +#define UMC_BASE__INST3_SEG3 0 +#define UMC_BASE__INST3_SEG4 0 + +#define UMC_BASE__INST4_SEG0 0 +#define UMC_BASE__INST4_SEG1 0 +#define UMC_BASE__INST4_SEG2 0 +#define UMC_BASE__INST4_SEG3 0 +#define UMC_BASE__INST4_SEG4 0 + +#define UMC_BASE__INST5_SEG0 0 +#define UMC_BASE__INST5_SEG1 0 +#define UMC_BASE__INST5_SEG2 0 +#define UMC_BASE__INST5_SEG3 0 +#define UMC_BASE__INST5_SEG4 0 + +#define UMC_BASE__INST6_SEG0 0 +#define UMC_BASE__INST6_SEG1 0 +#define UMC_BASE__INST6_SEG2 0 +#define UMC_BASE__INST6_SEG3 0 +#define UMC_BASE__INST6_SEG4 0 + +#define USB0_BASE__INST0_SEG0 0x0242A800 +#define USB0_BASE__INST0_SEG1 0x05B00000 +#define USB0_BASE__INST0_SEG2 0 +#define USB0_BASE__INST0_SEG3 0 +#define USB0_BASE__INST0_SEG4 0 + +#define USB0_BASE__INST1_SEG0 0 +#define USB0_BASE__INST1_SEG1 0 +#define USB0_BASE__INST1_SEG2 0 +#define USB0_BASE__INST1_SEG3 0 +#define USB0_BASE__INST1_SEG4 0 + +#define USB0_BASE__INST2_SEG0 0 +#define USB0_BASE__INST2_SEG1 0 +#define USB0_BASE__INST2_SEG2 0 +#define USB0_BASE__INST2_SEG3 0 +#define USB0_BASE__INST2_SEG4 0 + +#define USB0_BASE__INST3_SEG0 0 +#define USB0_BASE__INST3_SEG1 0 +#define USB0_BASE__INST3_SEG2 0 +#define USB0_BASE__INST3_SEG3 0 +#define USB0_BASE__INST3_SEG4 0 + +#define USB0_BASE__INST4_SEG0 0 +#define USB0_BASE__INST4_SEG1 0 +#define USB0_BASE__INST4_SEG2 0 +#define USB0_BASE__INST4_SEG3 0 +#define USB0_BASE__INST4_SEG4 0 + +#define USB0_BASE__INST5_SEG0 0 +#define USB0_BASE__INST5_SEG1 0 +#define USB0_BASE__INST5_SEG2 0 +#define USB0_BASE__INST5_SEG3 0 +#define USB0_BASE__INST5_SEG4 0 + +#define USB0_BASE__INST6_SEG0 0 +#define USB0_BASE__INST6_SEG1 0 +#define USB0_BASE__INST6_SEG2 0 +#define USB0_BASE__INST6_SEG3 0 +#define USB0_BASE__INST6_SEG4 0 + +#define UVD0_BASE__INST0_SEG0 0x00007800 +#define UVD0_BASE__INST0_SEG1 0x00007E00 +#define UVD0_BASE__INST0_SEG2 0x02403000 +#define UVD0_BASE__INST0_SEG3 0 +#define UVD0_BASE__INST0_SEG4 0 + +#define UVD0_BASE__INST1_SEG0 0 +#define UVD0_BASE__INST1_SEG1 0 +#define UVD0_BASE__INST1_SEG2 0 +#define UVD0_BASE__INST1_SEG3 0 +#define UVD0_BASE__INST1_SEG4 0 + +#define UVD0_BASE__INST2_SEG0 0 +#define UVD0_BASE__INST2_SEG1 0 +#define UVD0_BASE__INST2_SEG2 0 +#define UVD0_BASE__INST2_SEG3 0 +#define UVD0_BASE__INST2_SEG4 0 + +#define UVD0_BASE__INST3_SEG0 0 +#define UVD0_BASE__INST3_SEG1 0 +#define UVD0_BASE__INST3_SEG2 0 +#define UVD0_BASE__INST3_SEG3 0 +#define UVD0_BASE__INST3_SEG4 0 + +#define UVD0_BASE__INST4_SEG0 0 +#define UVD0_BASE__INST4_SEG1 0 +#define UVD0_BASE__INST4_SEG2 0 +#define UVD0_BASE__INST4_SEG3 0 +#define UVD0_BASE__INST4_SEG4 0 + +#define UVD0_BASE__INST5_SEG0 0 +#define UVD0_BASE__INST5_SEG1 0 +#define UVD0_BASE__INST5_SEG2 0 +#define UVD0_BASE__INST5_SEG3 0 +#define UVD0_BASE__INST5_SEG4 0 + +#define UVD0_BASE__INST6_SEG0 0 +#define UVD0_BASE__INST6_SEG1 0 +#define UVD0_BASE__INST6_SEG2 0 +#define UVD0_BASE__INST6_SEG3 0 +#define UVD0_BASE__INST6_SEG4 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h index 12e196c15bbe..1794ad1fc4fc 100644 --- a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h +++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h @@ -42,7 +42,6 @@ enum soc15_ih_clientid { SOC15_IH_CLIENTID_SE1SH = 0x0b, SOC15_IH_CLIENTID_SE2SH = 0x0c, SOC15_IH_CLIENTID_SE3SH = 0x0d, - SOC15_IH_CLIENTID_SYSHUB = 0x0e, SOC15_IH_CLIENTID_UVD1 = 0x0e, SOC15_IH_CLIENTID_THM = 0x0f, SOC15_IH_CLIENTID_UVD = 0x10, @@ -63,7 +62,15 @@ enum soc15_ih_clientid { SOC15_IH_CLIENTID_MAX, - SOC15_IH_CLIENTID_VCN = SOC15_IH_CLIENTID_UVD + SOC15_IH_CLIENTID_VCN = SOC15_IH_CLIENTID_UVD, + SOC15_IH_CLIENTID_VCN1 = SOC15_IH_CLIENTID_UVD1, + SOC15_IH_CLIENTID_SDMA2 = SOC15_IH_CLIENTID_ACP, + SOC15_IH_CLIENTID_SDMA3 = SOC15_IH_CLIENTID_DCE, + SOC15_IH_CLIENTID_SDMA4 = SOC15_IH_CLIENTID_ISP, + SOC15_IH_CLIENTID_SDMA5 = SOC15_IH_CLIENTID_VCE0, + SOC15_IH_CLIENTID_SDMA6 = SOC15_IH_CLIENTID_XDMA, + SOC15_IH_CLIENTID_SDMA7 = SOC15_IH_CLIENTID_VCE1, + SOC15_IH_CLIENTID_VMC1 = SOC15_IH_CLIENTID_PCIE0, }; #endif diff --git a/drivers/gpu/drm/amd/include/v9_structs.h b/drivers/gpu/drm/amd/include/v9_structs.h index 8b383dbe1cda..a0c672889fe4 100644 --- a/drivers/gpu/drm/amd/include/v9_structs.h +++ b/drivers/gpu/drm/amd/include/v9_structs.h @@ -196,10 +196,10 @@ struct v9_mqd { uint32_t compute_wave_restore_addr_lo; uint32_t compute_wave_restore_addr_hi; uint32_t compute_wave_restore_control; - uint32_t reserved_39; - uint32_t reserved_40; - uint32_t reserved_41; - uint32_t reserved_42; + uint32_t compute_static_thread_mgmt_se4; + uint32_t compute_static_thread_mgmt_se5; + uint32_t compute_static_thread_mgmt_se6; + uint32_t compute_static_thread_mgmt_se7; uint32_t reserved_43; uint32_t reserved_44; uint32_t reserved_45; |